From: Niklas Cassel <niklas.cassel@axis.com>
To: Niklas Cassel <niklass@axis.com>,
Jesper Nilsson <jespern@axis.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@axis.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 13/17] bindings: PCI: artpec: Add support for endpoint mode
Date: Fri, 3 Nov 2017 14:47:17 +0100 [thread overview]
Message-ID: <20171103134722.5532-14-niklas.cassel@axis.com> (raw)
In-Reply-To: <20171103134722.5532-1-niklas.cassel@axis.com>
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index 4e4aee4439ea..33eef7ae5a23 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
-- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
+- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
+ "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
- reg: base addresses and lengths of the PCIe controller (DBI),
the PHY controller, and configuration address space.
- reg-names: Must include the following entries:
--
2.14.2
next prev parent reply other threads:[~2017-11-03 13:49 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-03 13:47 [PATCH v4 00/17] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 01/17] PCI: dwc: Use the DMA-API to get the MSI address Niklas Cassel
2017-11-08 0:56 ` Bjorn Helgaas
2017-11-08 12:45 ` Joao Pinto
2017-11-08 17:27 ` Bjorn Helgaas
2017-11-09 9:20 ` Niklas Cassel
2017-11-21 12:18 ` Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 02/17] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 03/17] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 04/17] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 05/17] PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 06/17] PCI: designware-ep: Add generic function for raising MSI irq Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 07/17] PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 08/17] PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 09/17] PCI: dwc: dra7xx: Help compiler to remove unused code Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 10/17] PCI: dwc: artpec6: Remove unused defines Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 11/17] PCI: dwc: artpec6: Use BIT and GENMASK macros Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 12/17] PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions Niklas Cassel
2017-11-03 13:47 ` Niklas Cassel [this message]
2017-11-03 13:47 ` [PATCH v4 14/17] PCI: dwc: artpec6: Add support for endpoint mode Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 15/17] PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 16/17] bindings: PCI: artpec: Add support for the ARTPEC-7 SoC Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 17/17] PCI: dwc: artpec6: " Niklas Cassel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171103134722.5532-14-niklas.cassel@axis.com \
--to=niklas.cassel@axis.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=jespern@axis.com \
--cc=linux-arm-kernel@axis.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=niklass@axis.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).