* [PATCH v2 0/4] Building for 32-bit RISC-V kernel
@ 2018-06-25 8:49 Zong Li
2018-06-25 8:49 ` [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 Zong Li
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Zong Li @ 2018-06-25 8:49 UTC (permalink / raw)
To: palmer, hch, linux-riscv, linux-kernel, zongbox; +Cc: Zong Li, greentime
These patches for building 32-bit RISC-V kernel.
- Fix the compile errors and warnings on RV32I.
- Fix some incompatible problem on RV32I.
- Add format.h for compatible of print format.
The fixed width integer types format for Elf_Addr will move to
generic header by another patch. For now, there are some warning
about unexpected argument of type on RV32I.
Change in v1:
- Fix some error in v1
- Remove implementation of fixed width integer types format for Elf_Addr.
Zong Li (4):
RISC-V: Add conditional macro for zone of DMA32
RISC-V: Select GENERIC_UCMPDI2 on RV32I
RISC-V: Add definiion of extract symbol's index and type for 32-bit
RISC-V: Change variable type for 32-bit compatible
arch/riscv/Kconfig | 1 +
arch/riscv/include/uapi/asm/elf.h | 9 +++++++--
arch/riscv/kernel/module.c | 22 +++++++++++-----------
arch/riscv/mm/init.c | 2 ++
4 files changed, 21 insertions(+), 13 deletions(-)
--
2.16.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 2018-06-25 8:49 [PATCH v2 0/4] Building for 32-bit RISC-V kernel Zong Li @ 2018-06-25 8:49 ` Zong Li 2018-06-29 7:08 ` Christoph Hellwig 2018-06-25 8:49 ` [PATCH v2 2/4] RISC-V: Select GENERIC_UCMPDI2 on RV32I Zong Li ` (3 subsequent siblings) 4 siblings, 1 reply; 15+ messages in thread From: Zong Li @ 2018-06-25 8:49 UTC (permalink / raw) To: palmer, hch, linux-riscv, linux-kernel, zongbox; +Cc: Zong Li, greentime The DMA32 is for 64-bit usage. Signed-off-by: Zong Li <zong@andestech.com> --- arch/riscv/mm/init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index c77df8142be2..58a522f9bcc3 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -28,7 +28,9 @@ static void __init zone_sizes_init(void) { unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, }; +#ifdef CONFIG_ZONE_DMA32 max_zone_pfns[ZONE_DMA32] = PFN_DOWN(min(4UL * SZ_1G, max_low_pfn)); +#endif max_zone_pfns[ZONE_NORMAL] = max_low_pfn; free_area_init_nodes(max_zone_pfns); -- 2.16.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 2018-06-25 8:49 ` [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 Zong Li @ 2018-06-29 7:08 ` Christoph Hellwig 0 siblings, 0 replies; 15+ messages in thread From: Christoph Hellwig @ 2018-06-29 7:08 UTC (permalink / raw) To: Zong Li; +Cc: palmer, hch, linux-riscv, linux-kernel, zongbox, greentime On Mon, Jun 25, 2018 at 04:49:37PM +0800, Zong Li wrote: > The DMA32 is for 64-bit usage. > > Signed-off-by: Zong Li <zong@andestech.com> Looks good, Reviewed-by: Christoph Hellwig <hch@lst.de> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/4] RISC-V: Select GENERIC_UCMPDI2 on RV32I 2018-06-25 8:49 [PATCH v2 0/4] Building for 32-bit RISC-V kernel Zong Li 2018-06-25 8:49 ` [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 Zong Li @ 2018-06-25 8:49 ` Zong Li 2018-06-29 7:08 ` Christoph Hellwig 2018-06-25 8:49 ` [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit Zong Li ` (2 subsequent siblings) 4 siblings, 1 reply; 15+ messages in thread From: Zong Li @ 2018-06-25 8:49 UTC (permalink / raw) To: palmer, hch, linux-riscv, linux-kernel, zongbox; +Cc: Zong Li, greentime On 32-bit, it need to use __ucmpdi2, otherwise, it can't find the __ucmpdi2 symbol. Signed-off-by: Zong Li <zong@andestech.com> --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6debcc4afc72..3e683be9b7a8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -122,6 +122,7 @@ config ARCH_RV32I select GENERIC_ASHLDI3 select GENERIC_ASHRDI3 select GENERIC_LSHRDI3 + select GENERIC_UCMPDI2 config ARCH_RV64I bool "RV64I" -- 2.16.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: Select GENERIC_UCMPDI2 on RV32I 2018-06-25 8:49 ` [PATCH v2 2/4] RISC-V: Select GENERIC_UCMPDI2 on RV32I Zong Li @ 2018-06-29 7:08 ` Christoph Hellwig 0 siblings, 0 replies; 15+ messages in thread From: Christoph Hellwig @ 2018-06-29 7:08 UTC (permalink / raw) To: Zong Li; +Cc: palmer, hch, linux-riscv, linux-kernel, zongbox, greentime On Mon, Jun 25, 2018 at 04:49:38PM +0800, Zong Li wrote: > On 32-bit, it need to use __ucmpdi2, otherwise, it can't find the __ucmpdi2 > symbol. > > Signed-off-by: Zong Li <zong@andestech.com> Looks good, Reviewed-by: Christoph Hellwig <hch@lst.de> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit 2018-06-25 8:49 [PATCH v2 0/4] Building for 32-bit RISC-V kernel Zong Li 2018-06-25 8:49 ` [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 Zong Li 2018-06-25 8:49 ` [PATCH v2 2/4] RISC-V: Select GENERIC_UCMPDI2 on RV32I Zong Li @ 2018-06-25 8:49 ` Zong Li 2018-06-29 7:12 ` Christoph Hellwig 2018-06-25 8:49 ` [PATCH v2 4/4] RISC-V: Change variable type for 32-bit compatible Zong Li 2018-06-29 7:23 ` [PATCH v2 0/4] Building for 32-bit RISC-V kernel Christoph Hellwig 4 siblings, 1 reply; 15+ messages in thread From: Zong Li @ 2018-06-25 8:49 UTC (permalink / raw) To: palmer, hch, linux-riscv, linux-kernel, zongbox; +Cc: Zong Li, greentime Use generic marco to get the index and type of symbol. Signed-off-by: Zong Li <zong@andestech.com> --- arch/riscv/include/uapi/asm/elf.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index 5cae4c30cd8e..1e0dfc36aab9 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -21,8 +21,13 @@ typedef struct user_regs_struct elf_gregset_t; typedef union __riscv_fp_state elf_fpregset_t; -#define ELF_RISCV_R_SYM(r_info) ((r_info) >> 32) -#define ELF_RISCV_R_TYPE(r_info) ((r_info) & 0xffffffff) +#if __riscv_xlen == 64 +#define ELF_RISCV_R_SYM(r_info) ELF64_R_SYM(r_info) +#define ELF_RISCV_R_TYPE(r_info) ELF64_R_TYPE(r_info) +#else +#define ELF_RISCV_R_SYM(r_info) ELF32_R_SYM(r_info) +#define ELF_RISCV_R_TYPE(r_info) ELF32_R_TYPE(r_info) +#endif /* * RISC-V relocation types -- 2.16.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit 2018-06-25 8:49 ` [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit Zong Li @ 2018-06-29 7:12 ` Christoph Hellwig 2018-06-29 16:53 ` Zong Li 0 siblings, 1 reply; 15+ messages in thread From: Christoph Hellwig @ 2018-06-29 7:12 UTC (permalink / raw) To: Zong Li; +Cc: palmer, hch, linux-riscv, linux-kernel, zongbox, greentime On Mon, Jun 25, 2018 at 04:49:39PM +0800, Zong Li wrote: > Use generic marco to get the index and type of symbol. Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM and ELF_RISCV_R_TYPE move to module.c? In that case we could just use CONFIG_64BIT. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit 2018-06-29 7:12 ` Christoph Hellwig @ 2018-06-29 16:53 ` Zong Li 2018-07-04 20:58 ` Palmer Dabbelt 0 siblings, 1 reply; 15+ messages in thread From: Zong Li @ 2018-06-29 16:53 UTC (permalink / raw) To: hch Cc: Zong Li, Palmer Dabbelt, linux-riscv, Linux Kernel Mailing List, greentime Christoph Hellwig <hch@infradead.org> 於 2018年6月29日 週五 下午3:12寫道： > > On Mon, Jun 25, 2018 at 04:49:39PM +0800, Zong Li wrote: > > Use generic marco to get the index and type of symbol. > > Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM > and ELF_RISCV_R_TYPE move to module.c? In that case we could just > use CONFIG_64BIT. Make sense. I even think the all definitions can be move to include/asm/elf.h. How do you think about that? ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit 2018-06-29 16:53 ` Zong Li @ 2018-07-04 20:58 ` Palmer Dabbelt 2018-07-05 13:33 ` Zong Li 0 siblings, 1 reply; 15+ messages in thread From: Palmer Dabbelt @ 2018-07-04 20:58 UTC (permalink / raw) To: zongbox; +Cc: Christoph Hellwig, zong, linux-riscv, linux-kernel, greentime On Fri, 29 Jun 2018 09:53:49 PDT (-0700), zongbox@gmail.com wrote: > Christoph Hellwig <hch@infradead.org> 於 2018年6月29日 週五 下午3:12寫道： >> >> On Mon, Jun 25, 2018 at 04:49:39PM +0800, Zong Li wrote: >> > Use generic marco to get the index and type of symbol. >> >> Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM >> and ELF_RISCV_R_TYPE move to module.c? In that case we could just >> use CONFIG_64BIT. > > Make sense. I even think the all definitions can be move to include/asm/elf.h. > How do you think about that? Sorry I've been slow about reviewing this, but I think just in the interest of getting a sane RV32I port up and running quickly (so we can try to get glibc in shape) I'm going to take this for now. Do you mind submitting a cleanup patch? ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit 2018-07-04 20:58 ` Palmer Dabbelt @ 2018-07-05 13:33 ` Zong Li 2018-07-05 16:42 ` Palmer Dabbelt 0 siblings, 1 reply; 15+ messages in thread From: Zong Li @ 2018-07-05 13:33 UTC (permalink / raw) To: Palmer Dabbelt Cc: hch, Zong Li, linux-riscv, Linux Kernel Mailing List, greentime Palmer Dabbelt <palmer@sifive.com> 於 2018年7月5日 週四 上午4:58寫道： > > On Fri, 29 Jun 2018 09:53:49 PDT (-0700), zongbox@gmail.com wrote: > > Christoph Hellwig <hch@infradead.org> 於 2018年6月29日 週五 下午3:12寫道： > >> > >> On Mon, Jun 25, 2018 at 04:49:39PM +0800, Zong Li wrote: > >> > Use generic marco to get the index and type of symbol. > >> > >> Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM > >> and ELF_RISCV_R_TYPE move to module.c? In that case we could just > >> use CONFIG_64BIT. > > > > Make sense. I even think the all definitions can be move to include/asm/elf.h. > > How do you think about that? > > Sorry I've been slow about reviewing this, but I think just in the interest of > getting a sane RV32I port up and running quickly (so we can try to get glibc in > shape) I'm going to take this for now. > > Do you mind submitting a cleanup patch? I will send a patch to clean up. Thanks everyone to review this patchset. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit 2018-07-05 13:33 ` Zong Li @ 2018-07-05 16:42 ` Palmer Dabbelt 0 siblings, 0 replies; 15+ messages in thread From: Palmer Dabbelt @ 2018-07-05 16:42 UTC (permalink / raw) To: zongbox; +Cc: Christoph Hellwig, zong, linux-riscv, linux-kernel, greentime On Thu, 05 Jul 2018 06:33:07 PDT (-0700), zongbox@gmail.com wrote: > Palmer Dabbelt <palmer@sifive.com> 於 2018年7月5日 週四 上午4:58寫道： >> >> On Fri, 29 Jun 2018 09:53:49 PDT (-0700), zongbox@gmail.com wrote: >> > Christoph Hellwig <hch@infradead.org> 於 2018年6月29日 週五 下午3:12寫道： >> >> >> >> On Mon, Jun 25, 2018 at 04:49:39PM +0800, Zong Li wrote: >> >> > Use generic marco to get the index and type of symbol. >> >> >> >> Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM >> >> and ELF_RISCV_R_TYPE move to module.c? In that case we could just >> >> use CONFIG_64BIT. >> > >> > Make sense. I even think the all definitions can be move to include/asm/elf.h. >> > How do you think about that? >> >> Sorry I've been slow about reviewing this, but I think just in the interest of >> getting a sane RV32I port up and running quickly (so we can try to get glibc in >> shape) I'm going to take this for now. >> >> Do you mind submitting a cleanup patch? > > I will send a patch to clean up. Thanks everyone to review this patchset. Well, thanks for doing the work :). ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 4/4] RISC-V: Change variable type for 32-bit compatible 2018-06-25 8:49 [PATCH v2 0/4] Building for 32-bit RISC-V kernel Zong Li ` (2 preceding siblings ...) 2018-06-25 8:49 ` [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit Zong Li @ 2018-06-25 8:49 ` Zong Li 2018-06-29 7:12 ` Christoph Hellwig 2018-06-29 7:23 ` [PATCH v2 0/4] Building for 32-bit RISC-V kernel Christoph Hellwig 4 siblings, 1 reply; 15+ messages in thread From: Zong Li @ 2018-06-25 8:49 UTC (permalink / raw) To: palmer, hch, linux-riscv, linux-kernel, zongbox; +Cc: Zong Li, greentime Signed-off-by: Zong Li <zong@andestech.com> --- arch/riscv/kernel/module.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 29d265d0cf45..a346e0921995 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -39,7 +39,7 @@ static int apply_r_riscv_64_rela(struct module *me, u32 *location, Elf_Addr v) static int apply_r_riscv_branch_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; u32 imm12 = (offset & 0x1000) << (31 - 12); u32 imm11 = (offset & 0x800) >> (11 - 7); u32 imm10_5 = (offset & 0x7e0) << (30 - 10); @@ -52,7 +52,7 @@ static int apply_r_riscv_branch_rela(struct module *me, u32 *location, static int apply_r_riscv_jal_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; u32 imm20 = (offset & 0x100000) << (31 - 20); u32 imm19_12 = (offset & 0xff000); u32 imm11 = (offset & 0x800) << (20 - 11); @@ -65,7 +65,7 @@ static int apply_r_riscv_jal_rela(struct module *me, u32 *location, static int apply_r_riscv_rcv_branch_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; u16 imm8 = (offset & 0x100) << (12 - 8); u16 imm7_6 = (offset & 0xc0) >> (6 - 5); u16 imm5 = (offset & 0x20) >> (5 - 2); @@ -80,7 +80,7 @@ static int apply_r_riscv_rcv_branch_rela(struct module *me, u32 *location, static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; u16 imm11 = (offset & 0x800) << (12 - 11); u16 imm10 = (offset & 0x400) >> (10 - 8); u16 imm9_8 = (offset & 0x300) << (12 - 11); @@ -98,7 +98,7 @@ static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location, static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; s32 hi20; if (offset != (s32)offset) { @@ -180,7 +180,7 @@ static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location, static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; s32 hi20; /* Always emit the got entry */ @@ -202,7 +202,7 @@ static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location, static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; s32 fill_v = offset; u32 hi20, lo12; @@ -229,7 +229,7 @@ static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, static int apply_r_riscv_call_rela(struct module *me, u32 *location, Elf_Addr v) { - s64 offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - (void *)location; s32 fill_v = offset; u32 hi20, lo12; @@ -349,7 +349,7 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, unsigned int j; for (j = 0; j < sechdrs[relsec].sh_size / sizeof(*rel); j++) { - u64 hi20_loc = + unsigned long hi20_loc = sechdrs[sechdrs[relsec].sh_info].sh_addr + rel[j].r_offset; u32 hi20_type = ELF_RISCV_R_TYPE(rel[j].r_info); @@ -362,12 +362,12 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, Elf_Sym *hi20_sym = (Elf_Sym *)sechdrs[symindex].sh_addr + ELF_RISCV_R_SYM(rel[j].r_info); - u64 hi20_sym_val = + unsigned long hi20_sym_val = hi20_sym->st_value + rel[j].r_addend; /* Calculate lo12 */ - u64 offset = hi20_sym_val - hi20_loc; + size_t offset = hi20_sym_val - hi20_loc; if (IS_ENABLED(CONFIG_MODULE_SECTIONS) && hi20_type == R_RISCV_GOT_HI20) { offset = module_emit_got_entry( -- 2.16.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 4/4] RISC-V: Change variable type for 32-bit compatible 2018-06-25 8:49 ` [PATCH v2 4/4] RISC-V: Change variable type for 32-bit compatible Zong Li @ 2018-06-29 7:12 ` Christoph Hellwig 0 siblings, 0 replies; 15+ messages in thread From: Christoph Hellwig @ 2018-06-29 7:12 UTC (permalink / raw) To: Zong Li; +Cc: palmer, hch, linux-riscv, linux-kernel, zongbox, greentime On Mon, Jun 25, 2018 at 04:49:40PM +0800, Zong Li wrote: > Signed-off-by: Zong Li <zong@andestech.com> Looks good, Reviewed-by: Christoph Hellwig <hch@lst.de> ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 0/4] Building for 32-bit RISC-V kernel 2018-06-25 8:49 [PATCH v2 0/4] Building for 32-bit RISC-V kernel Zong Li ` (3 preceding siblings ...) 2018-06-25 8:49 ` [PATCH v2 4/4] RISC-V: Change variable type for 32-bit compatible Zong Li @ 2018-06-29 7:23 ` Christoph Hellwig 2018-06-29 17:06 ` Zong Li 4 siblings, 1 reply; 15+ messages in thread From: Christoph Hellwig @ 2018-06-29 7:23 UTC (permalink / raw) To: Zong Li; +Cc: palmer, hch, linux-riscv, linux-kernel, zongbox, greentime Btw, what kind of userspace do you use for riscv32? Do you have an easy to use root file system available somewhere (or a way to build one)? ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 0/4] Building for 32-bit RISC-V kernel 2018-06-29 7:23 ` [PATCH v2 0/4] Building for 32-bit RISC-V kernel Christoph Hellwig @ 2018-06-29 17:06 ` Zong Li 0 siblings, 0 replies; 15+ messages in thread From: Zong Li @ 2018-06-29 17:06 UTC (permalink / raw) To: hch Cc: Zong Li, Palmer Dabbelt, linux-riscv, Linux Kernel Mailing List, greentime Christoph Hellwig <hch@infradead.org> 於 2018年6月29日 週五 下午3:23寫道： > > Btw, what kind of userspace do you use for riscv32? Do you have an > easy to use root file system available somewhere (or a way to build > one)? I'm porting 32 bit riscv glibc now, and it is almost completion but still has few fail cases of glibc testsuite. I built the root file system consist of busybox, bash and dropbear and so on. I can push the rootfs I used or a build script to github if somebody need it. ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-07-05 16:42 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-06-25 8:49 [PATCH v2 0/4] Building for 32-bit RISC-V kernel Zong Li 2018-06-25 8:49 ` [PATCH v2 1/4] RISC-V: Add conditional macro for zone of DMA32 Zong Li 2018-06-29 7:08 ` Christoph Hellwig 2018-06-25 8:49 ` [PATCH v2 2/4] RISC-V: Select GENERIC_UCMPDI2 on RV32I Zong Li 2018-06-29 7:08 ` Christoph Hellwig 2018-06-25 8:49 ` [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit Zong Li 2018-06-29 7:12 ` Christoph Hellwig 2018-06-29 16:53 ` Zong Li 2018-07-04 20:58 ` Palmer Dabbelt 2018-07-05 13:33 ` Zong Li 2018-07-05 16:42 ` Palmer Dabbelt 2018-06-25 8:49 ` [PATCH v2 4/4] RISC-V: Change variable type for 32-bit compatible Zong Li 2018-06-29 7:12 ` Christoph Hellwig 2018-06-29 7:23 ` [PATCH v2 0/4] Building for 32-bit RISC-V kernel Christoph Hellwig 2018-06-29 17:06 ` Zong Li
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