* [PATCH V3 0/3] PCI: Add basic Compute eXpress Link DVSEC decode @ 2020-05-20 18:06 Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability Sean V Kelley ` (2 more replies) 0 siblings, 3 replies; 11+ messages in thread From: Sean V Kelley @ 2020-05-20 18:06 UTC (permalink / raw) To: bhelgaas; +Cc: linux-pci, linux-kernel, Sean V Kelley Changes since v2 [1]: - Provide comment about what PCI_CXL_LOCK does. - Use "cxl" in place of "pos" where appropriate to make code more descriptive. - Remove unnecessary extra check for pci_is_pcie(dev). - Remove reshuffling of pci_read_config_word() and put them in the right place when first added. - Make inline stubs consistent in format locally. (Bjorn Helgaas) - Add return to inline stubs to fix warning. - Refreshed David's patch (V2) [1] https://lore.kernel.org/linux-pci/20200518163523.1225643-1-sean.v.kelley@linux.intel.com/ This patch series implements basic Designated Vendor-Specific Extended Capabilities (DVSEC) decode for Compute eXpress Link devices, a new CPU interconnect building upon PCIe. As a basis for the CXL support it provides PCI init handling for detection, decode, and caching of CXL device capabilities. Moreover, it makes use of the DVSEC Vendor ID and DVSEC ID so as to identify a CXL capable device. (PCIe r5.0, sec 7.9.6.2) DocLink: https://www.computeexpresslink.org/ For your reference, a parallel series of patches have been submitted to enable lspci decode of CXL DVSEC and may be tracked. Link: https://lore.kernel.org/linux-pci/20200511174618.10589-1-sean.v.kelley@linux.intel.com/ This patch makes use of pending DVSEC related header additions and the first patch of that series is included here. It can be sorted out when the upstream merge is done. Link: https://lore.kernel.org/linux-pci/20200508021844.6911-2-david.e.box@linux.intel.com/ Sample dmesg output of a CXL Type 3 device (CXL.io, CXL.mem): [ 2.997177] pci 0000:6b:00.0: CXL: Cache- IO+ Mem+ Viral- HDMCount 1 [ 2.997188] pci 0000:6b:00.0: CXL: cap ctrl status ctrl2 status2 lock [ 2.997201] pci 0000:6b:00.0: CXL: 001e 0002 0000 0000 0000 0000 David E. Box (1): PCI: Add defines for Designated Vendor-Specific Capability Sean V Kelley (2): PCI: Add basic Compute eXpress Link DVSEC decode PCI: Add helpers to enable/disable CXL.mem and CXL.cache drivers/pci/Kconfig | 9 ++ drivers/pci/Makefile | 1 + drivers/pci/cxl.c | 176 ++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 15 +++ drivers/pci/probe.c | 1 + include/linux/pci.h | 3 + include/uapi/linux/pci_regs.h | 5 + 7 files changed, 210 insertions(+) create mode 100644 drivers/pci/cxl.c -- 2.26.2 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-05-20 18:06 [PATCH V3 0/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley @ 2020-05-20 18:06 ` Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 2/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 3/3] PCI: Add helpers to enable/disable CXL.mem and CXL.cache Sean V Kelley 2 siblings, 0 replies; 11+ messages in thread From: Sean V Kelley @ 2020-05-20 18:06 UTC (permalink / raw) To: bhelgaas; +Cc: linux-pci, linux-kernel, David E. Box From: "David E. Box" <david.e.box@linux.intel.com> Add PCIe DVSEC extended capability ID and defines for the header offsets. Defined in PCIe r5.0, sec 7.9.6. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> --- include/uapi/linux/pci_regs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f9701410d3b5..09daa9f07b6b 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -720,6 +720,7 @@ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT @@ -1062,6 +1063,10 @@ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ + /* Data Link Feature */ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ -- 2.26.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V3 2/3] PCI: Add basic Compute eXpress Link DVSEC decode 2020-05-20 18:06 [PATCH V3 0/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability Sean V Kelley @ 2020-05-20 18:06 ` Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 3/3] PCI: Add helpers to enable/disable CXL.mem and CXL.cache Sean V Kelley 2 siblings, 0 replies; 11+ messages in thread From: Sean V Kelley @ 2020-05-20 18:06 UTC (permalink / raw) To: bhelgaas; +Cc: linux-pci, linux-kernel, Sean V Kelley, Felipe Balbi Compute eXpress Link is a new CPU interconnect created with workload accelerators in mind. The interconnect relies on PCIe Electrical and Physical interconnect for communication. CXL devices enumerate to the OS as an ACPI-described PCIe Root Complex Integrated Endpoint. This patch introduces the bare minimum support by simply looking for and caching the DVSEC CXL Extended Capability. Currently, only CXL.io (which is mandatory to be configured by BIOS) is enabled. In future, we will also add support for CXL.cache and CXL.mem. DocLink: https://www.computeexpresslink.org/ Originally-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> --- drivers/pci/Kconfig | 9 +++++ drivers/pci/Makefile | 1 + drivers/pci/cxl.c | 92 ++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 7 ++++ drivers/pci/probe.c | 1 + include/linux/pci.h | 3 ++ 6 files changed, 113 insertions(+) create mode 100644 drivers/pci/cxl.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 4bef5c2bae9f..eafb200b320b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -115,6 +115,15 @@ config XEN_PCIDEV_FRONTEND The PCI device frontend driver allows the kernel to import arbitrary PCI devices from a PCI backend to support PCI driver domains. +config PCI_CXL + bool "Enable PCI Compute eXpress Link" + depends on PCI + help + Say Y here if you want the PCI core to detect CXL devices, decode, and + cache the DVSEC CXL Extended Capability as configured by BIOS. + + When in doubt, say N. + config PCI_ATS bool diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 522d2b974e91..465eee31e999 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PCI_PF_STUB) += pci-pf-stub.o obj-$(CONFIG_PCI_ECAM) += ecam.o obj-$(CONFIG_PCI_P2PDMA) += p2pdma.o obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o +obj-$(CONFIG_PCI_CXL) += cxl.o # Endpoint library must be initialized before its users obj-$(CONFIG_PCI_ENDPOINT) += endpoint/ diff --git a/drivers/pci/cxl.c b/drivers/pci/cxl.c new file mode 100644 index 000000000000..4497c597347f --- /dev/null +++ b/drivers/pci/cxl.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Compute eXpress Link Support + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/pci_regs.h> + +#define PCI_DVSEC_VENDOR_ID_CXL 0x1e98 +#define PCI_DVSEC_ID_CXL_DEV 0x0 + +#define PCI_CXL_CAP 0x0a +#define PCI_CXL_CTRL 0x0c +#define PCI_CXL_STS 0x0e +#define PCI_CXL_CTRL2 0x10 +#define PCI_CXL_STS2 0x12 +#define PCI_CXL_LOCK 0x14 + +#define PCI_CXL_CACHE BIT(0) +#define PCI_CXL_IO BIT(1) +#define PCI_CXL_MEM BIT(2) +#define PCI_CXL_HDM_COUNT(reg) (((reg) & (3 << 4)) >> 4) +#define PCI_CXL_VIRAL BIT(14) + +/* + * pci_find_cxl_capability - Identify and return offset to Vendor-Specific + * capabilities. + * + * CXL makes use of Designated Vendor-Specific Extended Capability (DVSEC) + * to uniquely identify both DVSEC Vendor ID and DVSEC ID aligning with + * PCIe r5.0, sec 7.9.6.2 + */ +static int pci_find_cxl_capability(struct pci_dev *dev) +{ + u16 vendor, id; + int pos = 0; + + while ((pos = pci_find_next_ext_capability(dev, pos, + PCI_EXT_CAP_ID_DVSEC))) { + pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, + &vendor); + pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id); + if (vendor == PCI_DVSEC_VENDOR_ID_CXL && + id == PCI_DVSEC_ID_CXL_DEV) + return pos; + } + + return 0; +} + + +#define FLAG(x, y) (((x) & (y)) ? '+' : '-') + +void pci_cxl_init(struct pci_dev *dev) +{ + u16 cap, ctrl, status, ctrl2, status2, lock; + int cxl; + + /* Only for PCIe */ + if (!pci_is_pcie(dev)) + return; + + /* Only for Device 0 Function 0, Root Complex Integrated Endpoints */ + if (dev->devfn != 0 || (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)) + return; + + cxl = pci_find_cxl_capability(dev); + if (!cxl) + return; + + dev->cxl_cap = cxl; + pci_read_config_word(dev, cxl + PCI_CXL_CAP, &cap); + + pci_info(dev, "CXL: Cache%c IO%c Mem%c Viral%c HDMCount %d\n", + FLAG(cap, PCI_CXL_CACHE), + FLAG(cap, PCI_CXL_IO), + FLAG(cap, PCI_CXL_MEM), + FLAG(cap, PCI_CXL_VIRAL), + PCI_CXL_HDM_COUNT(cap)); + + pci_read_config_word(dev, cxl + PCI_CXL_CTRL, &ctrl); + pci_read_config_word(dev, cxl + PCI_CXL_STS, &status); + pci_read_config_word(dev, cxl + PCI_CXL_CTRL2, &ctrl2); + pci_read_config_word(dev, cxl + PCI_CXL_STS2, &status2); + pci_read_config_word(dev, cxl + PCI_CXL_LOCK, &lock); + + pci_info(dev, "CXL: cap ctrl status ctrl2 status2 lock\n"); + pci_info(dev, "CXL: %04x %04x %04x %04x %04x %04x\n", + cap, ctrl, status, ctrl2, status2, lock); +} diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 6d3f75867106..d9905e2dee95 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -469,6 +469,13 @@ static inline void pci_ats_init(struct pci_dev *d) { } static inline void pci_restore_ats_state(struct pci_dev *dev) { } #endif /* CONFIG_PCI_ATS */ +#ifdef CONFIG_PCI_CXL +/* Compute eXpress Link */ +void pci_cxl_init(struct pci_dev *dev); +#else +static inline void pci_cxl_init(struct pci_dev *dev) { } +#endif + #ifdef CONFIG_PCI_PRI void pci_pri_init(struct pci_dev *dev); void pci_restore_pri_state(struct pci_dev *pdev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 77b8a145c39b..c55df0ae8f06 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2371,6 +2371,7 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_ptm_init(dev); /* Precision Time Measurement */ pci_aer_init(dev); /* Advanced Error Reporting */ pci_dpc_init(dev); /* Downstream Port Containment */ + pci_cxl_init(dev); /* Compute eXpress Link */ pcie_report_downtraining(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 83ce1cdf5676..9fd544f76447 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -314,6 +314,9 @@ struct pci_dev { #ifdef CONFIG_PCIEAER u16 aer_cap; /* AER capability offset */ struct aer_stats *aer_stats; /* AER stats for this device */ +#endif +#ifdef CONFIG_PCI_CXL + u16 cxl_cap; /* CXL capability offset */ #endif u8 pcie_cap; /* PCIe capability offset */ u8 msi_cap; /* MSI capability offset */ -- 2.26.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V3 3/3] PCI: Add helpers to enable/disable CXL.mem and CXL.cache 2020-05-20 18:06 [PATCH V3 0/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 2/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley @ 2020-05-20 18:06 ` Sean V Kelley 2 siblings, 0 replies; 11+ messages in thread From: Sean V Kelley @ 2020-05-20 18:06 UTC (permalink / raw) To: bhelgaas; +Cc: linux-pci, linux-kernel, Sean V Kelley With these helpers, a device driver can enable/disable access to CXL.mem and CXL.cache. Note that the device driver is responsible for managing the memory area. Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com> --- drivers/pci/cxl.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 8 +++++ 2 files changed, 92 insertions(+) diff --git a/drivers/pci/cxl.c b/drivers/pci/cxl.c index 4497c597347f..e58e5262b59a 100644 --- a/drivers/pci/cxl.c +++ b/drivers/pci/cxl.c @@ -24,6 +24,90 @@ #define PCI_CXL_HDM_COUNT(reg) (((reg) & (3 << 4)) >> 4) #define PCI_CXL_VIRAL BIT(14) +#define PCI_CXL_CONFIG_LOCK BIT(0) + +static void pci_cxl_unlock(struct pci_dev *dev) +{ + int cxl = dev->cxl_cap; + u16 lock; + + pci_read_config_word(dev, cxl + PCI_CXL_LOCK, &lock); + lock &= ~PCI_CXL_CONFIG_LOCK; + pci_write_config_word(dev, cxl + PCI_CXL_LOCK, lock); +} + +static void pci_cxl_lock(struct pci_dev *dev) +{ + int cxl = dev->cxl_cap; + u16 lock; + + pci_read_config_word(dev, cxl + PCI_CXL_LOCK, &lock); + lock |= PCI_CXL_CONFIG_LOCK; + pci_write_config_word(dev, cxl + PCI_CXL_LOCK, lock); +} + +/* + * CXL DVSEC CTRL registers have Read-Write-Lockable attributes. + * PCI_CXL_CONFIG_LOCK locks these CTRL registers by making them RO. + * This lock prevents future changes to configuration and is not intended + * for enforcing mutual exclusion. See CXL 1.1, sec 7.1.1.6 + */ +static int pci_cxl_enable_disable_feature(struct pci_dev *dev, int enable, + u16 feature) +{ + int cxl = dev->cxl_cap; + int ret; + u16 reg; + + if (!dev->cxl_cap) + return -EINVAL; + + /* Only for Device 0 Function 0, Root Complex Integrated Endpoints */ + if (dev->devfn != 0 || (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)) + return -EINVAL; + + pci_cxl_unlock(dev); + ret = pci_read_config_word(dev, cxl + PCI_CXL_CTRL, ®); + if (ret) + goto lock; + + if (enable) + reg |= feature; + else + reg &= ~feature; + + ret = pci_write_config_word(dev, cxl + PCI_CXL_CTRL, reg); + +lock: + pci_cxl_lock(dev); + + return ret; +} + +int pci_cxl_mem_enable(struct pci_dev *dev) +{ + return pci_cxl_enable_disable_feature(dev, true, PCI_CXL_MEM); +} +EXPORT_SYMBOL_GPL(pci_cxl_mem_enable); + +void pci_cxl_mem_disable(struct pci_dev *dev) +{ + pci_cxl_enable_disable_feature(dev, false, PCI_CXL_MEM); +} +EXPORT_SYMBOL_GPL(pci_cxl_mem_disable); + +int pci_cxl_cache_enable(struct pci_dev *dev) +{ + return pci_cxl_enable_disable_feature(dev, true, PCI_CXL_CACHE); +} +EXPORT_SYMBOL_GPL(pci_cxl_cache_enable); + +void pci_cxl_cache_disable(struct pci_dev *dev) +{ + pci_cxl_enable_disable_feature(dev, false, PCI_CXL_CACHE); +} +EXPORT_SYMBOL_GPL(pci_cxl_cache_disable); + /* * pci_find_cxl_capability - Identify and return offset to Vendor-Specific * capabilities. diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index d9905e2dee95..5ec7fa0eb709 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -472,8 +472,16 @@ static inline void pci_restore_ats_state(struct pci_dev *dev) { } #ifdef CONFIG_PCI_CXL /* Compute eXpress Link */ void pci_cxl_init(struct pci_dev *dev); +int pci_cxl_mem_enable(struct pci_dev *dev); +void pci_cxl_mem_disable(struct pci_dev *dev); +int pci_cxl_cache_enable(struct pci_dev *dev); +void pci_cxl_cache_disable(struct pci_dev *dev); #else static inline void pci_cxl_init(struct pci_dev *dev) { } +static inline int pci_cxl_mem_enable(struct pci_dev *dev) { return 0; } +static inline void pci_cxl_mem_disable(struct pci_dev *dev) { } +static inline int pci_cxl_cache_enable(struct pci_dev *dev) { return 0; } +static inline void pci_cxl_cache_disable(struct pci_dev *dev) { } #endif #ifdef CONFIG_PCI_PRI -- 2.26.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 0/3] Intel Platform Monitoring Technology @ 2020-05-08 2:18 David E. Box 2020-07-14 6:23 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability David E. Box 0 siblings, 1 reply; 11+ messages in thread From: David E. Box @ 2020-05-08 2:18 UTC (permalink / raw) To: bhelgaas, andy, lee.jones, alexander.h.duyck Cc: David E. Box, linux-kernel, linux-pci Intel Platform Monitoring Technology (PMT) is an architecture for enumerating and accessing hardware monitoring capabilities on a device. With customers increasingly asking for hardware telemetry, engineers not only have to figure out how to measure and collect data, but also how to deliver it and make it discoverable. The latter may be through some device specific method requiring device specific tools to collect the data. This in turn requires customers to manage a suite of different tools in order to collect the differing assortment of monitoring data on their systems. Even when such information can be provided in kernel drivers, they may require constant maintenance to update register mappings as they change with firmware updates and new versions of hardware. PMT provides a solution for discovering and reading telemetry from a device through a hardware agnostic framework that allows for updates to systems without requiring patches to the kernel or software tools. PMT defines several capabilities to support collecting monitoring data from hardware. All are discoverable as separate instances of the PCIE Designated Vendor extended capability (DVSEC) with the Intel vendor code. The DVSEC ID field uniquely identifies the capability. Each DVSEC also provides a BAR offset to a header that defines capability-specific attributes, including GUID, feature type, offset and length, as well as configuration settings where applicable. The GUID uniquely identifies the register space of any monitor data exposed by the capability. The GUID is associated with an XML file from the vendor that describes the mapping of the register space along with properties of the monitor data. This allows vendors to perform firmware updates that can change the mapping (e.g. add new metrics) without requiring any changes to drivers or software tools. The new mapping is confirmed by an updated GUID, read from the hardware, which software uses with a new XML. The current capabilities defined by PMT are Telemetry, Watcher, and Crashlog. The Telemetry capability provides access to a continuous block of read only data. The Watcher capability provides access to hardware sampling and tracing features. Crashlog provides access to device crash dumps. While there is some relationship between capabilities (Watcher can be configured to sample from the Telemetry data set) each exists as stand alone features with no dependency on any other. The design therefore splits them into individual, capability specific drivers. MFD is used to create platform devices for each capability so that they may be managed by their own driver. The PMT architecture is (for the most part) agnostic to the type of device it can collect from. Devices nodes are consequently generic in naming, e.g. /dev/telem<n> and /dev/smplr<n>. Each capability driver creates a class to manage the list of devices supporting it. Software can determine which devices support a PMT feature by searching through each device node entry in the sysfs class folder. It can additionally determine if a particular device supports a PMT feature by checking for a PMT class folder in the device folder. This patch set provides support for the PMT framework, along with support for Telemetry on Tiger Lake. Changes from V1: - In the telemetry driver, set the device in device_create() to the parent pci device (the monitoring device) for clear association in sysfs. Was set before to the platform device created by the pci parent. - Move telem struct into driver and delete unneeded header file. - Start telem device numbering from 0 instead of 1. 1 was used due to anticipated changes, no longer needed. - Use helper macros suggested by Andy S. - Rename class to pmt_telemetry, spelling out full name - Move monitor device name defines to common header - Coding style, spelling, and Makefile/MAINTAINERS ordering fixes David E. Box (3): PCI: Add #defines for Designated Vendor-Specific Capability mfd: Intel Platform Monitoring Technology support platform/x86: Intel PMT Telemetry capability driver MAINTAINERS | 6 + drivers/mfd/Kconfig | 10 + drivers/mfd/Makefile | 1 + drivers/mfd/intel_pmt.c | 170 ++++++++++++ drivers/platform/x86/Kconfig | 10 + drivers/platform/x86/Makefile | 1 + drivers/platform/x86/intel_pmt_telem.c | 362 +++++++++++++++++++++++++ include/linux/intel-dvsec.h | 48 ++++ include/uapi/linux/pci_regs.h | 5 + 9 files changed, 613 insertions(+) create mode 100644 drivers/mfd/intel_pmt.c create mode 100644 drivers/platform/x86/intel_pmt_telem.c create mode 100644 include/linux/intel-dvsec.h -- 2.20.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-05-08 2:18 [PATCH v2 0/3] Intel Platform Monitoring Technology David E. Box @ 2020-07-14 6:23 ` David E. Box 2020-07-14 8:40 ` Andy Shevchenko 2020-07-16 2:55 ` Randy Dunlap 0 siblings, 2 replies; 11+ messages in thread From: David E. Box @ 2020-07-14 6:23 UTC (permalink / raw) To: lee.jones, david.e.box, dvhart, andy, bhelgaas, alexander.h.duyck Cc: linux-kernel, platform-driver-x86, linux-pci Add PCIe DVSEC extended capability ID and defines for the header offsets. Defined in PCIe r5.0, sec 7.9.6. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> --- include/uapi/linux/pci_regs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f9701410d3b5..09daa9f07b6b 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -720,6 +720,7 @@ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT @@ -1062,6 +1063,10 @@ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ + /* Data Link Feature */ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-07-14 6:23 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability David E. Box @ 2020-07-14 8:40 ` Andy Shevchenko 2020-07-16 2:55 ` Randy Dunlap 1 sibling, 0 replies; 11+ messages in thread From: Andy Shevchenko @ 2020-07-14 8:40 UTC (permalink / raw) To: David E. Box Cc: Lee Jones, Darren Hart, Andy Shevchenko, Bjorn Helgaas, Alexander Duyck, Linux Kernel Mailing List, Platform Driver, linux-pci On Tue, Jul 14, 2020 at 9:22 AM David E. Box <david.e.box@linux.intel.com> wrote: > > Add PCIe DVSEC extended capability ID and defines for the header offsets. > Defined in PCIe r5.0, sec 7.9.6. > Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> > Signed-off-by: David E. Box <david.e.box@linux.intel.com> > Acked-by: Bjorn Helgaas <bhelgaas@google.com> > --- > include/uapi/linux/pci_regs.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index f9701410d3b5..09daa9f07b6b 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -720,6 +720,7 @@ > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT > @@ -1062,6 +1063,10 @@ > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ > > +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ > +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ > + > /* Data Link Feature */ > #define PCI_DLF_CAP 0x04 /* Capabilities Register */ > #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ > -- > 2.20.1 > -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-07-14 6:23 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability David E. Box 2020-07-14 8:40 ` Andy Shevchenko @ 2020-07-16 2:55 ` Randy Dunlap 2020-07-16 15:07 ` Bjorn Helgaas 2020-07-16 17:18 ` Alexander Duyck 1 sibling, 2 replies; 11+ messages in thread From: Randy Dunlap @ 2020-07-16 2:55 UTC (permalink / raw) To: David E. Box, lee.jones, dvhart, andy, bhelgaas, alexander.h.duyck Cc: linux-kernel, platform-driver-x86, linux-pci On 7/13/20 11:23 PM, David E. Box wrote: > Add PCIe DVSEC extended capability ID and defines for the header offsets. > Defined in PCIe r5.0, sec 7.9.6. > > Signed-off-by: David E. Box <david.e.box@linux.intel.com> > Acked-by: Bjorn Helgaas <bhelgaas@google.com> > --- > include/uapi/linux/pci_regs.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index f9701410d3b5..09daa9f07b6b 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -720,6 +720,7 @@ > +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > @@ -1062,6 +1063,10 @@ > +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ > +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ Just a little comment: It would make more sense to me to s/DVSEC/DVSPEC/g. But then I don't have the PCIe documentation. -- ~Randy ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-07-16 2:55 ` Randy Dunlap @ 2020-07-16 15:07 ` Bjorn Helgaas 2020-07-16 15:07 ` Randy Dunlap 2020-07-16 17:18 ` Alexander Duyck 1 sibling, 1 reply; 11+ messages in thread From: Bjorn Helgaas @ 2020-07-16 15:07 UTC (permalink / raw) To: Randy Dunlap Cc: David E. Box, lee.jones, dvhart, andy, bhelgaas, alexander.h.duyck, linux-kernel, platform-driver-x86, linux-pci On Wed, Jul 15, 2020 at 07:55:11PM -0700, Randy Dunlap wrote: > On 7/13/20 11:23 PM, David E. Box wrote: > > Add PCIe DVSEC extended capability ID and defines for the header offsets. > > Defined in PCIe r5.0, sec 7.9.6. > > > > Signed-off-by: David E. Box <david.e.box@linux.intel.com> > > Acked-by: Bjorn Helgaas <bhelgaas@google.com> > > --- > > include/uapi/linux/pci_regs.h | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > index f9701410d3b5..09daa9f07b6b 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -720,6 +720,7 @@ > > +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > > @@ -1062,6 +1063,10 @@ > > +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > > +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ > > +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ > > Just a little comment: It would make more sense to me to > s/DVSEC/DVSPEC/g. Yeah, that is confusing, but "DVSEC" is the term used in the spec. I think it stands for "Designated Vendor-Specific Extended Capability". ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-07-16 15:07 ` Bjorn Helgaas @ 2020-07-16 15:07 ` Randy Dunlap 0 siblings, 0 replies; 11+ messages in thread From: Randy Dunlap @ 2020-07-16 15:07 UTC (permalink / raw) To: Bjorn Helgaas Cc: David E. Box, lee.jones, dvhart, andy, bhelgaas, alexander.h.duyck, linux-kernel, platform-driver-x86, linux-pci On 7/16/20 8:07 AM, Bjorn Helgaas wrote: > On Wed, Jul 15, 2020 at 07:55:11PM -0700, Randy Dunlap wrote: >> On 7/13/20 11:23 PM, David E. Box wrote: >>> Add PCIe DVSEC extended capability ID and defines for the header offsets. >>> Defined in PCIe r5.0, sec 7.9.6. >>> >>> Signed-off-by: David E. Box <david.e.box@linux.intel.com> >>> Acked-by: Bjorn Helgaas <bhelgaas@google.com> >>> --- >>> include/uapi/linux/pci_regs.h | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h >>> index f9701410d3b5..09daa9f07b6b 100644 >>> --- a/include/uapi/linux/pci_regs.h >>> +++ b/include/uapi/linux/pci_regs.h >>> @@ -720,6 +720,7 @@ >>> +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ >>> @@ -1062,6 +1063,10 @@ >>> +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ >>> +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ >>> +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ >> >> Just a little comment: It would make more sense to me to >> s/DVSEC/DVSPEC/g. > > Yeah, that is confusing, but "DVSEC" is the term used in the spec. I > think it stands for "Designated Vendor-Specific Extended Capability". Right. I noticed that after I sent the email. thanks. -- ~Randy ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-07-16 2:55 ` Randy Dunlap 2020-07-16 15:07 ` Bjorn Helgaas @ 2020-07-16 17:18 ` Alexander Duyck 2020-07-16 18:31 ` David E. Box 1 sibling, 1 reply; 11+ messages in thread From: Alexander Duyck @ 2020-07-16 17:18 UTC (permalink / raw) To: Randy Dunlap, David E. Box, lee.jones, dvhart, andy, bhelgaas Cc: linux-kernel, platform-driver-x86, linux-pci On 7/15/2020 7:55 PM, Randy Dunlap wrote: > On 7/13/20 11:23 PM, David E. Box wrote: >> Add PCIe DVSEC extended capability ID and defines for the header offsets. >> Defined in PCIe r5.0, sec 7.9.6. >> >> Signed-off-by: David E. Box <david.e.box@linux.intel.com> >> Acked-by: Bjorn Helgaas <bhelgaas@google.com> >> --- >> include/uapi/linux/pci_regs.h | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h >> index f9701410d3b5..09daa9f07b6b 100644 >> --- a/include/uapi/linux/pci_regs.h >> +++ b/include/uapi/linux/pci_regs.h >> @@ -720,6 +720,7 @@ >> +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ >> @@ -1062,6 +1063,10 @@ >> +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ >> +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ >> +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ > > Just a little comment: It would make more sense to me to > s/DVSEC/DVSPEC/g. > > But then I don't have the PCIe documentation. Arguably some of the confusion might be from the patch title. DVSEC is acronym for Designated Vendor-Specific Extended Capability if I recall correctly. It would probably be best to call that out since the extended implies it lives in the config space accessible via the memory mapped config. ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability 2020-07-16 17:18 ` Alexander Duyck @ 2020-07-16 18:31 ` David E. Box 0 siblings, 0 replies; 11+ messages in thread From: David E. Box @ 2020-07-16 18:31 UTC (permalink / raw) To: Alexander Duyck, Randy Dunlap, lee.jones, dvhart, andy, bhelgaas Cc: linux-kernel, platform-driver-x86, linux-pci On Thu, 2020-07-16 at 10:18 -0700, Alexander Duyck wrote: > > On 7/15/2020 7:55 PM, Randy Dunlap wrote: > > On 7/13/20 11:23 PM, David E. Box wrote: > > > Add PCIe DVSEC extended capability ID and defines for the header > > > offsets. > > > Defined in PCIe r5.0, sec 7.9.6. > > > > > > Signed-off-by: David E. Box <david.e.box@linux.intel.com> > > > Acked-by: Bjorn Helgaas <bhelgaas@google.com> > > > --- > > > include/uapi/linux/pci_regs.h | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/include/uapi/linux/pci_regs.h > > > b/include/uapi/linux/pci_regs.h > > > index f9701410d3b5..09daa9f07b6b 100644 > > > --- a/include/uapi/linux/pci_regs.h > > > +++ b/include/uapi/linux/pci_regs.h > > > @@ -720,6 +720,7 @@ > > > +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor- > > > Specific */ > > > @@ -1062,6 +1063,10 @@ > > > +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > > > +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific > > > Header1 */ > > > +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific > > > Header2 */ These comments I'll fix to say "Designated Vendor-Specific" > > > > Just a little comment: It would make more sense to me to > > s/DVSEC/DVSPEC/g. > > > > But then I don't have the PCIe documentation. > > Arguably some of the confusion might be from the patch title. DVSEC > is > acronym for Designated Vendor-Specific Extended Capability if I > recall > correctly. It would probably be best to call that out since the > extended > implies it lives in the config space accessible via the memory > mapped > config. I'll change the patch title as well, but agree DVSEC is better as it's consistent with the spec. Thanks David ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-07-16 18:31 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-20 18:06 [PATCH V3 0/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 2/3] PCI: Add basic Compute eXpress Link DVSEC decode Sean V Kelley 2020-05-20 18:06 ` [PATCH V3 3/3] PCI: Add helpers to enable/disable CXL.mem and CXL.cache Sean V Kelley -- strict thread matches above, loose matches on Subject: below -- 2020-05-08 2:18 [PATCH v2 0/3] Intel Platform Monitoring Technology David E. Box 2020-07-14 6:23 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability David E. Box 2020-07-14 8:40 ` Andy Shevchenko 2020-07-16 2:55 ` Randy Dunlap 2020-07-16 15:07 ` Bjorn Helgaas 2020-07-16 15:07 ` Randy Dunlap 2020-07-16 17:18 ` Alexander Duyck 2020-07-16 18:31 ` David E. Box
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