* [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables
@ 2020-07-02 20:46 Sibi Sankar
2020-07-09 2:22 ` Steev Klimaszewski
2020-07-09 14:45 ` Bjorn Andersson
0 siblings, 2 replies; 5+ messages in thread
From: Sibi Sankar @ 2020-07-02 20:46 UTC (permalink / raw)
To: bjorn.andersson
Cc: viresh.kumar, sboyd, georgi.djakov, agross, robh+dt,
linux-arm-msm, devicetree, linux-kernel, saravanak, dianders,
vincent.guittot, amit.kucheria, robdclark, Sibi Sankar
Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v2:
* Drop interconnect tags
* Add all possible cpu opps from supported frequency list
v1: https://patchwork.kernel.org/patch/11527589/
arch/arm64/boot/dts/qcom/sdm845.dtsi | 285 +++++++++++++++++++++++++++
1 file changed, 285 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8eb5a31346d28..9a7e27ede7186 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
@@ -198,6 +199,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
@@ -220,6 +224,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
@@ -239,6 +246,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
@@ -258,6 +268,9 @@ &LITTLE_CPU_SLEEP_1
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
@@ -277,6 +290,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
@@ -296,6 +312,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
@@ -315,6 +334,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_600>;
L2_600: l2-cache {
@@ -334,6 +356,9 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
@@ -433,6 +458,266 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
};
+ cpu0_opp_table: cpu0_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu0_opp2: opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu0_opp3: opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <800000 6451200>;
+ };
+
+ cpu0_opp4: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <800000 6451200>;
+ };
+
+ cpu0_opp5: opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-peak-kBps = <800000 7680000>;
+ };
+
+ cpu0_opp6: opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-peak-kBps = <1804000 9216000>;
+ };
+
+ cpu0_opp7: opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <1804000 9216000>;
+ };
+
+ cpu0_opp8: opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <1804000 10444800>;
+ };
+
+ cpu0_opp9: opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-peak-kBps = <1804000 11980800>;
+ };
+
+ cpu0_opp10: opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <1804000 11980800>;
+ };
+
+ cpu0_opp11: opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <2188000 13516800>;
+ };
+
+ cpu0_opp12: opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <2188000 15052800>;
+ };
+
+ cpu0_opp13: opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <2188000 16588800>;
+ };
+
+ cpu0_opp14: opp-1420800000 {
+ opp-hz = /bits/ 64 <1420800000>;
+ opp-peak-kBps = <3072000 18124800>;
+ };
+
+ cpu0_opp15: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <3072000 19353600>;
+ };
+
+ cpu0_opp16: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <4068000 19353600>;
+ };
+
+ cpu0_opp17: opp-1689600000 {
+ opp-hz = /bits/ 64 <1689600000>;
+ opp-peak-kBps = <4068000 20889600>;
+ };
+
+ cpu0_opp18: opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <4068000 22425600>;
+ };
+ };
+
+ cpu4_opp_table: cpu4_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu4_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu4_opp2: opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-peak-kBps = <800000 4800000>;
+ };
+
+ cpu4_opp3: opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp4: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp5: opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp6: opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-peak-kBps = <1804000 4800000>;
+ };
+
+ cpu4_opp7: opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <2188000 9216000>;
+ };
+
+ cpu4_opp8: opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <2188000 9216000>;
+ };
+
+ cpu4_opp9: opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-peak-kBps = <2188000 9216000>;
+ };
+
+ cpu4_opp10: opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <3072000 9216000>;
+ };
+
+ cpu4_opp11: opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <3072000 11980800>;
+ };
+
+ cpu4_opp12: opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-peak-kBps = <4068000 11980800>;
+ };
+
+ cpu4_opp13: opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-peak-kBps = <4068000 11980800>;
+ };
+
+ cpu4_opp14: opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <4068000 15052800>;
+ };
+
+ cpu4_opp15: opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <4068000 15052800>;
+ };
+
+ cpu4_opp16: opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <5412000 15052800>;
+ };
+
+ cpu4_opp17: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <5412000 15052800>;
+ };
+
+ cpu4_opp18: opp-1689600000 {
+ opp-hz = /bits/ 64 <1689600000>;
+ opp-peak-kBps = <5412000 19353600>;
+ };
+
+ cpu4_opp19: opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <6220000 19353600>;
+ };
+
+ cpu4_opp20: opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <6220000 19353600>;
+ };
+
+ cpu4_opp21: opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-peak-kBps = <7216000 19353600>;
+ };
+
+ cpu4_opp22: opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp23: opp-2092800000 {
+ opp-hz = /bits/ 64 <2092800000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp24: opp-2169600000 {
+ opp-hz = /bits/ 64 <2169600000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp25: opp-2246400000 {
+ opp-hz = /bits/ 64 <2246400000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp26: opp-2323200000 {
+ opp-hz = /bits/ 64 <2323200000>;
+ opp-peak-kBps = <7216000 20889600>;
+ };
+
+ cpu4_opp27: opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp28: opp-2476800000 {
+ opp-hz = /bits/ 64 <2476800000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp29: opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp30: opp-2649600000 {
+ opp-hz = /bits/ 64 <2649600000>;
+ opp-peak-kBps = <7216000 22425600>;
+ };
+
+ cpu4_opp31: opp-2745600000 {
+ opp-hz = /bits/ 64 <2745600000>;
+ opp-peak-kBps = <7216000 25497600>;
+ };
+
+ cpu4_opp32: opp-2803200000 {
+ opp-hz = /bits/ 64 <2803200000>;
+ opp-peak-kBps = <7216000 25497600>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables
2020-07-02 20:46 [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables Sibi Sankar
@ 2020-07-09 2:22 ` Steev Klimaszewski
2020-07-09 14:29 ` Bjorn Andersson
2020-07-09 14:45 ` Bjorn Andersson
1 sibling, 1 reply; 5+ messages in thread
From: Steev Klimaszewski @ 2020-07-09 2:22 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson
Cc: viresh.kumar, sboyd, georgi.djakov, agross, robh+dt,
linux-arm-msm, devicetree, linux-kernel, saravanak, dianders,
vincent.guittot, amit.kucheria, robdclark
On 7/2/20 3:46 PM, Sibi Sankar wrote:
> Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
Hi Sibi,
Bjorn asked me to give this patch a whirl, and I have to say, I like it
but I'm not sure if I'm missing a dependency somewhere...
In 5.8.0-rc4, I'm seeing a couple probe defers
[ 0.131341] cpu cpu0: _allocate_opp_table: Error finding interconnect
paths: -517
[ 0.132694] cpu cpu4: _allocate_opp_table: Error finding interconnect
paths: -517
And then a bit later on,
[ 0.625837] cpu cpu0: failed to get clock: -2
If these aren't anything to worry about, you can throw my Tested-by on
Tested-by: Steev Klimaszewski <steev@kali.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables
2020-07-09 2:22 ` Steev Klimaszewski
@ 2020-07-09 14:29 ` Bjorn Andersson
2020-07-09 14:43 ` Sibi Sankar
0 siblings, 1 reply; 5+ messages in thread
From: Bjorn Andersson @ 2020-07-09 14:29 UTC (permalink / raw)
To: Steev Klimaszewski
Cc: Sibi Sankar, viresh.kumar, sboyd, georgi.djakov, agross, robh+dt,
linux-arm-msm, devicetree, linux-kernel, saravanak, dianders,
vincent.guittot, amit.kucheria, robdclark
On Wed 08 Jul 19:22 PDT 2020, Steev Klimaszewski wrote:
>
> On 7/2/20 3:46 PM, Sibi Sankar wrote:
> > Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs.
> >
> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > ---
>
>
> Hi Sibi,
>
>
> Bjorn asked me to give this patch a whirl, and I have to say, I like it
> but I'm not sure if I'm missing a dependency somewhere...
>
>
> In 5.8.0-rc4, I'm seeing a couple probe defers
>
> [ 0.131341] cpu cpu0: _allocate_opp_table: Error finding interconnect
> paths: -517
>
> [ 0.132694] cpu cpu4: _allocate_opp_table: Error finding interconnect
> paths: -517
>
> And then a bit later on,
>
> [ 0.625837] cpu cpu0: failed to get clock: -2
>
>
> If these aren't anything to worry about, you can throw my Tested-by on
>
> Tested-by: Steev Klimaszewski <steev@kali.org>
>
You need to enable:
CONFIG_INTERCONNECT=y
CONFIG_INTERCONNECT_QCOM=y
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
CONFIG_INTERCONNECT_QCOM_SDM845=m
With this I can see the interconnect_summary in debugfs change with the
CPU frequency.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables
2020-07-09 14:29 ` Bjorn Andersson
@ 2020-07-09 14:43 ` Sibi Sankar
0 siblings, 0 replies; 5+ messages in thread
From: Sibi Sankar @ 2020-07-09 14:43 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Steev Klimaszewski, viresh.kumar, sboyd, georgi.djakov, agross,
robh+dt, linux-arm-msm, devicetree, linux-kernel, saravanak,
dianders, vincent.guittot, amit.kucheria, robdclark,
linux-kernel-owner
On 2020-07-09 19:59, Bjorn Andersson wrote:
> On Wed 08 Jul 19:22 PDT 2020, Steev Klimaszewski wrote:
>
>>
>> On 7/2/20 3:46 PM, Sibi Sankar wrote:
>> > Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs.
>> >
>> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> > ---
>>
>>
>> Hi Sibi,
>>
>>
>> Bjorn asked me to give this patch a whirl, and I have to say, I like
>> it
>> but I'm not sure if I'm missing a dependency somewhere...
>>
>>
>> In 5.8.0-rc4, I'm seeing a couple probe defers
>>
>> [ 0.131341] cpu cpu0: _allocate_opp_table: Error finding
>> interconnect
>> paths: -517
>>
>> [ 0.132694] cpu cpu4: _allocate_opp_table: Error finding
>> interconnect
>> paths: -517
>>
>> And then a bit later on,
>>
>> [ 0.625837] cpu cpu0: failed to get clock: -2
>>
>>
>> If these aren't anything to worry about, you can throw my Tested-by on
>>
>> Tested-by: Steev Klimaszewski <steev@kali.org>
>>
>
> You need to enable:
> CONFIG_INTERCONNECT=y
> CONFIG_INTERCONNECT_QCOM=y
> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
> CONFIG_INTERCONNECT_QCOM_SDM845=m
Steev had ^^ enabled but he was missing
the required cpufreq driver changes
available in linux-next.
>
> With this I can see the interconnect_summary in debugfs change with the
> CPU frequency.
>
> Regards,
> Bjorn
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables
2020-07-02 20:46 [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables Sibi Sankar
2020-07-09 2:22 ` Steev Klimaszewski
@ 2020-07-09 14:45 ` Bjorn Andersson
1 sibling, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2020-07-09 14:45 UTC (permalink / raw)
To: Sibi Sankar
Cc: viresh.kumar, sboyd, georgi.djakov, agross, robh+dt,
linux-arm-msm, devicetree, linux-kernel, saravanak, dianders,
vincent.guittot, amit.kucheria, robdclark
On Thu 02 Jul 13:46 PDT 2020, Sibi Sankar wrote:
> Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
and applied.
Thanks,
Bjorn
> ---
>
> v2:
> * Drop interconnect tags
> * Add all possible cpu opps from supported frequency list
>
> v1: https://patchwork.kernel.org/patch/11527589/
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 285 +++++++++++++++++++++++++++
> 1 file changed, 285 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 8eb5a31346d28..9a7e27ede7186 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -12,6 +12,7 @@
> #include <dt-bindings/clock/qcom,lpass-sdm845.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,videocc-sdm845.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/interconnect/qcom,sdm845.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/phy/phy-qcom-qusb2.h>
> @@ -198,6 +199,9 @@ &LITTLE_CPU_SLEEP_1
> capacity-dmips-mhz = <607>;
> dynamic-power-coefficient = <100>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> @@ -220,6 +224,9 @@ &LITTLE_CPU_SLEEP_1
> capacity-dmips-mhz = <607>;
> dynamic-power-coefficient = <100>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_100>;
> L2_100: l2-cache {
> @@ -239,6 +246,9 @@ &LITTLE_CPU_SLEEP_1
> capacity-dmips-mhz = <607>;
> dynamic-power-coefficient = <100>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_200>;
> L2_200: l2-cache {
> @@ -258,6 +268,9 @@ &LITTLE_CPU_SLEEP_1
> capacity-dmips-mhz = <607>;
> dynamic-power-coefficient = <100>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_300>;
> L2_300: l2-cache {
> @@ -277,6 +290,9 @@ &BIG_CPU_SLEEP_1
> &CLUSTER_SLEEP_0>;
> dynamic-power-coefficient = <396>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> + operating-points-v2 = <&cpu4_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_400>;
> L2_400: l2-cache {
> @@ -296,6 +312,9 @@ &BIG_CPU_SLEEP_1
> &CLUSTER_SLEEP_0>;
> dynamic-power-coefficient = <396>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> + operating-points-v2 = <&cpu4_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_500>;
> L2_500: l2-cache {
> @@ -315,6 +334,9 @@ &BIG_CPU_SLEEP_1
> &CLUSTER_SLEEP_0>;
> dynamic-power-coefficient = <396>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> + operating-points-v2 = <&cpu4_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_600>;
> L2_600: l2-cache {
> @@ -334,6 +356,9 @@ &BIG_CPU_SLEEP_1
> &CLUSTER_SLEEP_0>;
> dynamic-power-coefficient = <396>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> + operating-points-v2 = <&cpu4_opp_table>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> #cooling-cells = <2>;
> next-level-cache = <&L2_700>;
> L2_700: l2-cache {
> @@ -433,6 +458,266 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
> };
> };
>
> + cpu0_opp_table: cpu0_opp_table {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + cpu0_opp1: opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-peak-kBps = <800000 4800000>;
> + };
> +
> + cpu0_opp2: opp-403200000 {
> + opp-hz = /bits/ 64 <403200000>;
> + opp-peak-kBps = <800000 4800000>;
> + };
> +
> + cpu0_opp3: opp-480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-peak-kBps = <800000 6451200>;
> + };
> +
> + cpu0_opp4: opp-576000000 {
> + opp-hz = /bits/ 64 <576000000>;
> + opp-peak-kBps = <800000 6451200>;
> + };
> +
> + cpu0_opp5: opp-652800000 {
> + opp-hz = /bits/ 64 <652800000>;
> + opp-peak-kBps = <800000 7680000>;
> + };
> +
> + cpu0_opp6: opp-748800000 {
> + opp-hz = /bits/ 64 <748800000>;
> + opp-peak-kBps = <1804000 9216000>;
> + };
> +
> + cpu0_opp7: opp-825600000 {
> + opp-hz = /bits/ 64 <825600000>;
> + opp-peak-kBps = <1804000 9216000>;
> + };
> +
> + cpu0_opp8: opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-peak-kBps = <1804000 10444800>;
> + };
> +
> + cpu0_opp9: opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-peak-kBps = <1804000 11980800>;
> + };
> +
> + cpu0_opp10: opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-peak-kBps = <1804000 11980800>;
> + };
> +
> + cpu0_opp11: opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-peak-kBps = <2188000 13516800>;
> + };
> +
> + cpu0_opp12: opp-1228800000 {
> + opp-hz = /bits/ 64 <1228800000>;
> + opp-peak-kBps = <2188000 15052800>;
> + };
> +
> + cpu0_opp13: opp-1324800000 {
> + opp-hz = /bits/ 64 <1324800000>;
> + opp-peak-kBps = <2188000 16588800>;
> + };
> +
> + cpu0_opp14: opp-1420800000 {
> + opp-hz = /bits/ 64 <1420800000>;
> + opp-peak-kBps = <3072000 18124800>;
> + };
> +
> + cpu0_opp15: opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-peak-kBps = <3072000 19353600>;
> + };
> +
> + cpu0_opp16: opp-1612800000 {
> + opp-hz = /bits/ 64 <1612800000>;
> + opp-peak-kBps = <4068000 19353600>;
> + };
> +
> + cpu0_opp17: opp-1689600000 {
> + opp-hz = /bits/ 64 <1689600000>;
> + opp-peak-kBps = <4068000 20889600>;
> + };
> +
> + cpu0_opp18: opp-1766400000 {
> + opp-hz = /bits/ 64 <1766400000>;
> + opp-peak-kBps = <4068000 22425600>;
> + };
> + };
> +
> + cpu4_opp_table: cpu4_opp_table {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + cpu4_opp1: opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-peak-kBps = <800000 4800000>;
> + };
> +
> + cpu4_opp2: opp-403200000 {
> + opp-hz = /bits/ 64 <403200000>;
> + opp-peak-kBps = <800000 4800000>;
> + };
> +
> + cpu4_opp3: opp-480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-peak-kBps = <1804000 4800000>;
> + };
> +
> + cpu4_opp4: opp-576000000 {
> + opp-hz = /bits/ 64 <576000000>;
> + opp-peak-kBps = <1804000 4800000>;
> + };
> +
> + cpu4_opp5: opp-652800000 {
> + opp-hz = /bits/ 64 <652800000>;
> + opp-peak-kBps = <1804000 4800000>;
> + };
> +
> + cpu4_opp6: opp-748800000 {
> + opp-hz = /bits/ 64 <748800000>;
> + opp-peak-kBps = <1804000 4800000>;
> + };
> +
> + cpu4_opp7: opp-825600000 {
> + opp-hz = /bits/ 64 <825600000>;
> + opp-peak-kBps = <2188000 9216000>;
> + };
> +
> + cpu4_opp8: opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-peak-kBps = <2188000 9216000>;
> + };
> +
> + cpu4_opp9: opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-peak-kBps = <2188000 9216000>;
> + };
> +
> + cpu4_opp10: opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-peak-kBps = <3072000 9216000>;
> + };
> +
> + cpu4_opp11: opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-peak-kBps = <3072000 11980800>;
> + };
> +
> + cpu4_opp12: opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-peak-kBps = <4068000 11980800>;
> + };
> +
> + cpu4_opp13: opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-peak-kBps = <4068000 11980800>;
> + };
> +
> + cpu4_opp14: opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-peak-kBps = <4068000 15052800>;
> + };
> +
> + cpu4_opp15: opp-1459200000 {
> + opp-hz = /bits/ 64 <1459200000>;
> + opp-peak-kBps = <4068000 15052800>;
> + };
> +
> + cpu4_opp16: opp-1536000000 {
> + opp-hz = /bits/ 64 <1536000000>;
> + opp-peak-kBps = <5412000 15052800>;
> + };
> +
> + cpu4_opp17: opp-1612800000 {
> + opp-hz = /bits/ 64 <1612800000>;
> + opp-peak-kBps = <5412000 15052800>;
> + };
> +
> + cpu4_opp18: opp-1689600000 {
> + opp-hz = /bits/ 64 <1689600000>;
> + opp-peak-kBps = <5412000 19353600>;
> + };
> +
> + cpu4_opp19: opp-1766400000 {
> + opp-hz = /bits/ 64 <1766400000>;
> + opp-peak-kBps = <6220000 19353600>;
> + };
> +
> + cpu4_opp20: opp-1843200000 {
> + opp-hz = /bits/ 64 <1843200000>;
> + opp-peak-kBps = <6220000 19353600>;
> + };
> +
> + cpu4_opp21: opp-1920000000 {
> + opp-hz = /bits/ 64 <1920000000>;
> + opp-peak-kBps = <7216000 19353600>;
> + };
> +
> + cpu4_opp22: opp-1996800000 {
> + opp-hz = /bits/ 64 <1996800000>;
> + opp-peak-kBps = <7216000 20889600>;
> + };
> +
> + cpu4_opp23: opp-2092800000 {
> + opp-hz = /bits/ 64 <2092800000>;
> + opp-peak-kBps = <7216000 20889600>;
> + };
> +
> + cpu4_opp24: opp-2169600000 {
> + opp-hz = /bits/ 64 <2169600000>;
> + opp-peak-kBps = <7216000 20889600>;
> + };
> +
> + cpu4_opp25: opp-2246400000 {
> + opp-hz = /bits/ 64 <2246400000>;
> + opp-peak-kBps = <7216000 20889600>;
> + };
> +
> + cpu4_opp26: opp-2323200000 {
> + opp-hz = /bits/ 64 <2323200000>;
> + opp-peak-kBps = <7216000 20889600>;
> + };
> +
> + cpu4_opp27: opp-2400000000 {
> + opp-hz = /bits/ 64 <2400000000>;
> + opp-peak-kBps = <7216000 22425600>;
> + };
> +
> + cpu4_opp28: opp-2476800000 {
> + opp-hz = /bits/ 64 <2476800000>;
> + opp-peak-kBps = <7216000 22425600>;
> + };
> +
> + cpu4_opp29: opp-2553600000 {
> + opp-hz = /bits/ 64 <2553600000>;
> + opp-peak-kBps = <7216000 22425600>;
> + };
> +
> + cpu4_opp30: opp-2649600000 {
> + opp-hz = /bits/ 64 <2649600000>;
> + opp-peak-kBps = <7216000 22425600>;
> + };
> +
> + cpu4_opp31: opp-2745600000 {
> + opp-hz = /bits/ 64 <2745600000>;
> + opp-peak-kBps = <7216000 25497600>;
> + };
> +
> + cpu4_opp32: opp-2803200000 {
> + opp-hz = /bits/ 64 <2803200000>;
> + opp-peak-kBps = <7216000 25497600>;
> + };
> + };
> +
> pmu {
> compatible = "arm,armv8-pmuv3";
> interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-07-09 14:47 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-02 20:46 [PATCH v2] arm64: dts: qcom: sdm845: Add cpu OPP tables Sibi Sankar
2020-07-09 2:22 ` Steev Klimaszewski
2020-07-09 14:29 ` Bjorn Andersson
2020-07-09 14:43 ` Sibi Sankar
2020-07-09 14:45 ` Bjorn Andersson
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