[PATCH v2 0/4] Add initial support for RoseapplePi SBC

[PATCH v2 0/4] Add initial support for RoseapplePi SBC

[Cristian Ciocaltea]

This patchset enables basic support for RoseapplePi, relying exclusively
on the existing infrastructure for the Actions Semi Owl SoCs (thanks to
Andreas and Mani for making this possible).

The SBC is powered by the Actions Semi S500 SoC and comes with 2GB RAM,
uSD slot and optional eMMC storage. For more details, please check:
http://roseapplepi.org/index.php/spec/

The upcoming patches will improve this initial support by adding the
missing bits and pieces to the S500 clock management unit, which is a
prerequisite for providing an S500 pinctrl and gpio driver, in order to
eventually enable access to additional functionality like I2C and MMC.

Thanks and regards,
Cristian Ciocaltea

Changes in v2:
 - Added Reviewed-by and Acked-by tags from Rob
 - Added Reviewed-by tags from Peter
 - Rebased series onto v5.9-rc2

Cristian Ciocaltea (4):
  arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers
  dt-bindings: Add vendor prefix for RoseapplePi.org
  dt-bindings: arm: actions: Document RoseapplePi
  arm: dts: owl-s500: Add RoseapplePi

 .../devicetree/bindings/arm/actions.yaml      |  1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 arch/arm/boot/dts/Makefile                    |  1 +
 arch/arm/boot/dts/owl-s500-roseapplepi.dts    | 47 +++++++++++++++++++
 arch/arm/boot/dts/owl-s500.dtsi               |  6 +--
 5 files changed, 54 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts

-- 
2.28.0

[PATCH v2 1/4] arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers

[Cristian Ciocaltea]

The PPI interrupts for cortex-a9 were incorrectly specified, fix them.

Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 5ceb6cc4451d..1dbe4e8b38ac 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -84,21 +84,21 @@ scu: scu@b0020000 {
 		global_timer: timer@b0020200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0xb0020200 0x100>;
-			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+			interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 			status = "disabled";
 		};
 
 		twd_timer: timer@b0020600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xb0020600 0x20>;
-			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 			status = "disabled";
 		};
 
 		twd_wdt: wdt@b0020620 {
 			compatible = "arm,cortex-a9-twd-wdt";
 			reg = <0xb0020620 0xe0>;
-			interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 			status = "disabled";
 		};
 
-- 
2.28.0

[PATCH v2 2/4] dt-bindings: Add vendor prefix for RoseapplePi.org

[Cristian Ciocaltea]

Add devicetree vendor prefix for RoseapplePi.org Foundation.
Website: http://roseapplepi.org/

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 63996ab03521..0b5bd97b4211 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -894,6 +894,8 @@ patternProperties:
     description: Ronbo Electronics
   "^roofull,.*":
     description: Shenzhen Roofull Technology Co, Ltd
+  "^roseapplepi,.*":
+    description: RoseapplePi.org
   "^samsung,.*":
     description: Samsung Semiconductor
   "^samtec,.*":
-- 
2.28.0

[PATCH v2 3/4] dt-bindings: arm: actions: Document RoseapplePi

[Cristian Ciocaltea]

Define compatible strings for RoseapplePi, a SBC manufactured
in Taiwan, based on Actions Semi S500 reference design.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/actions.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/actions.yaml b/Documentation/devicetree/bindings/arm/actions.yaml
index ace3fdaa8396..787cd1b4f26c 100644
--- a/Documentation/devicetree/bindings/arm/actions.yaml
+++ b/Documentation/devicetree/bindings/arm/actions.yaml
@@ -18,6 +18,7 @@ properties:
           - enum:
               - allo,sparky # Allo.com Sparky
               - cubietech,cubieboard6 # Cubietech CubieBoard6
+              - roseapplepi,roseapplepi # RoseapplePi.org RoseapplePi
           - const: actions,s500
       - items:
           - enum:
-- 
2.28.0

[PATCH v2 4/4] arm: dts: owl-s500: Add RoseapplePi

[Cristian Ciocaltea]

Add a Device Tree for the RoseapplePi SBC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
---
 arch/arm/boot/dts/Makefile                 |  1 +
 arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 ++++++++++++++++++++++
 2 files changed, 48 insertions(+)
 create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4572db3fa5ae..bff9ef996fbb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 dtb-$(CONFIG_ARCH_ACTIONS) += \
 	owl-s500-cubieboard6.dtb \
 	owl-s500-guitar-bb-rev-b.dtb \
+	owl-s500-roseapplepi.dtb \
 	owl-s500-sparky.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
new file mode 100644
index 000000000000..a2087e617cb2
--- /dev/null
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Roseapple Pi
+ *
+ * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "owl-s500.dtsi"
+
+/ {
+	compatible = "roseapplepi,roseapplepi", "actions,s500";
+	model = "Roseapple Pi";
+
+	aliases {
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x80000000>; /* 2GB */
+	};
+
+	uart2_clk: uart2-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <921600>;
+		#clock-cells = <0>;
+	};
+};
+
+&twd_timer {
+	status = "okay";
+};
+
+&timer {
+	clocks = <&hosc>;
+};
+
+&uart2 {
+	status = "okay";
+	clocks = <&uart2_clk>;
+};
-- 
2.28.0

Re: [PATCH v2 1/4] arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers

[Manivannan Sadhasivam]

On 0828, Cristian Ciocaltea wrote:
> The PPI interrupts for cortex-a9 were incorrectly specified, fix them.
> 
> Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Reviewed-by: Peter Korsgaard <peter@korsgaard.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 5ceb6cc4451d..1dbe4e8b38ac 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -84,21 +84,21 @@ scu: scu@b0020000 {
>  		global_timer: timer@b0020200 {
>  			compatible = "arm,cortex-a9-global-timer";
>  			reg = <0xb0020200 0x100>;
> -			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> +			interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
>  			status = "disabled";
>  		};
>  
>  		twd_timer: timer@b0020600 {
>  			compatible = "arm,cortex-a9-twd-timer";
>  			reg = <0xb0020600 0x20>;
> -			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
>  			status = "disabled";
>  		};
>  
>  		twd_wdt: wdt@b0020620 {
>  			compatible = "arm,cortex-a9-twd-wdt";
>  			reg = <0xb0020620 0xe0>;
> -			interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> +			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
>  			status = "disabled";
>  		};
>  
> -- 
> 2.28.0
> 

Re: [PATCH v2 4/4] arm: dts: owl-s500: Add RoseapplePi

[Manivannan Sadhasivam]

On 0828, Cristian Ciocaltea wrote:
> Add a Device Tree for the RoseapplePi SBC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Reviewed-by: Peter Korsgaard <peter@korsgaard.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/Makefile                 |  1 +
>  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 ++++++++++++++++++++++
>  2 files changed, 48 insertions(+)
>  create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 4572db3fa5ae..bff9ef996fbb 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>  dtb-$(CONFIG_ARCH_ACTIONS) += \
>  	owl-s500-cubieboard6.dtb \
>  	owl-s500-guitar-bb-rev-b.dtb \
> +	owl-s500-roseapplepi.dtb \
>  	owl-s500-sparky.dtb
>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>  	prima2-evb.dtb
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> new file mode 100644
> index 000000000000..a2087e617cb2
> --- /dev/null
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Roseapple Pi
> + *
> + * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "owl-s500.dtsi"
> +
> +/ {
> +	compatible = "roseapplepi,roseapplepi", "actions,s500";
> +	model = "Roseapple Pi";
> +
> +	aliases {
> +		serial2 = &uart2;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial2:115200n8";
> +	};
> +
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000>; /* 2GB */
> +	};
> +
> +	uart2_clk: uart2-clk {
> +		compatible = "fixed-clock";
> +		clock-frequency = <921600>;
> +		#clock-cells = <0>;
> +	};
> +};
> +
> +&twd_timer {
> +	status = "okay";
> +};
> +
> +&timer {
> +	clocks = <&hosc>;
> +};
> +
> +&uart2 {
> +	status = "okay";
> +	clocks = <&uart2_clk>;
> +};
> -- 
> 2.28.0
> 

Re: [PATCH v2 2/4] dt-bindings: Add vendor prefix for RoseapplePi.org

[Manivannan Sadhasivam]

On 0828, Cristian Ciocaltea wrote:
> Add devicetree vendor prefix for RoseapplePi.org Foundation.
> Website: http://roseapplepi.org/
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>

Rob, are you going to take this patch? Else I'll take this through arm-soc tree!

Thanks,
Mani

> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 63996ab03521..0b5bd97b4211 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -894,6 +894,8 @@ patternProperties:
>      description: Ronbo Electronics
>    "^roofull,.*":
>      description: Shenzhen Roofull Technology Co, Ltd
> +  "^roseapplepi,.*":
> +    description: RoseapplePi.org
>    "^samsung,.*":
>      description: Samsung Semiconductor
>    "^samtec,.*":
> -- 
> 2.28.0
> 

Re: [PATCH v2 1/4] arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers

[Cristian Ciocaltea]

On Mon, Aug 31, 2020 at 02:49:25PM +0530, Manivannan Sadhasivam wrote:
> On 0828, Cristian Ciocaltea wrote:
> > The PPI interrupts for cortex-a9 were incorrectly specified, fix them.
> > 
> > Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar")
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Cristi

> Thanks,
> Mani
> 
> > ---
> >  arch/arm/boot/dts/owl-s500.dtsi | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> > index 5ceb6cc4451d..1dbe4e8b38ac 100644
> > --- a/arch/arm/boot/dts/owl-s500.dtsi
> > +++ b/arch/arm/boot/dts/owl-s500.dtsi
> > @@ -84,21 +84,21 @@ scu: scu@b0020000 {
> >  		global_timer: timer@b0020200 {
> >  			compatible = "arm,cortex-a9-global-timer";
> >  			reg = <0xb0020200 0x100>;
> > -			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > +			interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> >  			status = "disabled";
> >  		};
> >  
> >  		twd_timer: timer@b0020600 {
> >  			compatible = "arm,cortex-a9-twd-timer";
> >  			reg = <0xb0020600 0x20>;
> > -			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > +			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> >  			status = "disabled";
> >  		};
> >  
> >  		twd_wdt: wdt@b0020620 {
> >  			compatible = "arm,cortex-a9-twd-wdt";
> >  			reg = <0xb0020620 0xe0>;
> > -			interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > +			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> >  			status = "disabled";
> >  		};
> >  
> > -- 
> > 2.28.0
> > 

Re: [PATCH v2 4/4] arm: dts: owl-s500: Add RoseapplePi

[Cristian Ciocaltea]

On Mon, Aug 31, 2020 at 02:56:48PM +0530, Manivannan Sadhasivam wrote:
> On 0828, Cristian Ciocaltea wrote:
> > Add a Device Tree for the RoseapplePi SBC.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Cristi

> Thanks,
> Mani
> 
> > ---
> >  arch/arm/boot/dts/Makefile                 |  1 +
> >  arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 ++++++++++++++++++++++
> >  2 files changed, 48 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 4572db3fa5ae..bff9ef996fbb 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
> >  dtb-$(CONFIG_ARCH_ACTIONS) += \
> >  	owl-s500-cubieboard6.dtb \
> >  	owl-s500-guitar-bb-rev-b.dtb \
> > +	owl-s500-roseapplepi.dtb \
> >  	owl-s500-sparky.dtb
> >  dtb-$(CONFIG_ARCH_PRIMA2) += \
> >  	prima2-evb.dtb
> > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > new file mode 100644
> > index 000000000000..a2087e617cb2
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > @@ -0,0 +1,47 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Roseapple Pi
> > + *
> > + * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "owl-s500.dtsi"
> > +
> > +/ {
> > +	compatible = "roseapplepi,roseapplepi", "actions,s500";
> > +	model = "Roseapple Pi";
> > +
> > +	aliases {
> > +		serial2 = &uart2;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial2:115200n8";
> > +	};
> > +
> > +	memory@0 {
> > +		device_type = "memory";
> > +		reg = <0x0 0x80000000>; /* 2GB */
> > +	};
> > +
> > +	uart2_clk: uart2-clk {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <921600>;
> > +		#clock-cells = <0>;
> > +	};
> > +};
> > +
> > +&twd_timer {
> > +	status = "okay";
> > +};
> > +
> > +&timer {
> > +	clocks = <&hosc>;
> > +};
> > +
> > +&uart2 {
> > +	status = "okay";
> > +	clocks = <&uart2_clk>;
> > +};
> > -- 
> > 2.28.0
> > 

Re: [PATCH v2 2/4] dt-bindings: Add vendor prefix for RoseapplePi.org

[Manivannan Sadhasivam]

On Fri, Aug 28, 2020 at 04:53:18PM +0300, Cristian Ciocaltea wrote:
> Add devicetree vendor prefix for RoseapplePi.org Foundation.
> Website: http://roseapplepi.org/
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>

Applied for v5.10!

Thanks,
Mani

> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 63996ab03521..0b5bd97b4211 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -894,6 +894,8 @@ patternProperties:
>      description: Ronbo Electronics
>    "^roofull,.*":
>      description: Shenzhen Roofull Technology Co, Ltd
> +  "^roseapplepi,.*":
> +    description: RoseapplePi.org
>    "^samsung,.*":
>      description: Samsung Semiconductor
>    "^samtec,.*":
> -- 
> 2.28.0
>