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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	leo.yan@linaro.org, jonathan.zhouwen@huawei.com,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 12/25] coresight: etm4x: Check for Software Lock
Date: Mon, 14 Dec 2020 17:37:18 +0000	[thread overview]
Message-ID: <20201214173731.302520-13-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201214173731.302520-1-suzuki.poulose@arm.com>

The Software lock is not implemented for system instructions
based accesses. So, skip the lock register access in such
cases.

Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 .../coresight/coresight-etm4x-core.c          | 40 ++++++++++++-------
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 923a6d730f7e..a1838b920062 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -130,6 +130,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 	isb();
 }
 
+static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
+			 struct csdev_access *csa)
+{
+	/* Software Lock is only accessible via memory mapped interface */
+	if (csa->io_mem)
+		CS_LOCK(csa->base);
+}
+
+static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
+			 struct csdev_access *csa)
+{
+	if (csa->io_mem)
+		CS_UNLOCK(csa->base);
+}
+
 static bool etm4_arch_supported(u8 arch)
 {
 	/* Mask out the minor version number */
@@ -169,8 +184,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 	struct device *etm_dev = &csdev->dev;
 	struct csdev_access *csa = &csdev->access;
 
-	CS_UNLOCK(drvdata->base);
-
+	etm4_cs_unlock(drvdata, csa);
 	etm4_os_unlock(drvdata);
 
 	rc = coresight_claim_device_unlocked(csdev);
@@ -271,7 +285,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 	isb();
 
 done:
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 
 	dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 		drvdata->cpu, rc);
@@ -528,7 +542,7 @@ static void etm4_disable_hw(void *info)
 	struct csdev_access *csa = &csdev->access;
 	int i;
 
-	CS_UNLOCK(drvdata->base);
+	etm4_cs_unlock(drvdata, csa);
 
 	if (!drvdata->skip_power_up) {
 		/* power can be removed from the trace unit now */
@@ -569,8 +583,7 @@ static void etm4_disable_hw(void *info)
 	}
 
 	coresight_disclaim_device_unlocked(csdev);
-
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 
 	dev_dbg(&drvdata->csdev->dev,
 		"cpu: %d disable smp call done\n", drvdata->cpu);
@@ -680,8 +693,7 @@ static void etm4_init_arch_data(void *info)
 
 	/* Make sure all registers are accessible */
 	etm4_os_unlock_csa(drvdata, csa);
-
-	CS_UNLOCK(drvdata->base);
+	etm4_cs_unlock(drvdata, csa);
 
 	/* find all capabilities of the tracing unit */
 	etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
@@ -846,7 +858,7 @@ static void etm4_init_arch_data(void *info)
 	drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 	/* NUMCNTR, bits[30:28] number of counters available for tracing */
 	drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 }
 
 /* Set ELx trace filter access in the TRCVICTLR register */
@@ -1227,8 +1239,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	dsb(sy);
 	isb();
 
-	CS_UNLOCK(drvdata->base);
-
+	etm4_cs_unlock(drvdata, csa);
 	/* Lock the OS lock to disable trace and external debugger access */
 	etm4_os_lock(drvdata);
 
@@ -1341,7 +1352,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 		etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
 				      TRCPDCR);
 out:
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 	return ret;
 }
 
@@ -1352,8 +1363,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
 	struct csdev_access *csa = &tmp_csa;
 
-	CS_UNLOCK(drvdata->base);
-
+	etm4_cs_unlock(drvdata, csa);
 	etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
 
 	etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
@@ -1438,7 +1448,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 
 	/* Unlock the OS lock to re-enable trace and external debug access */
 	etm4_os_unlock(drvdata);
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 }
 
 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
-- 
2.24.1


  parent reply	other threads:[~2020-12-14 18:14 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-14 17:37 [PATCH v5 00/25] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-12-14 17:37 ` Suzuki K Poulose [this message]
2020-12-14 17:37 ` [PATCH v5 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-12-16 18:01   ` Mike Leach
2020-12-14 17:37 ` [PATCH v5 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-05 21:44   ` Mathieu Poirier
2020-12-14 17:37 ` [PATCH v5 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2021-01-06 14:48 ` [PATCH v5 00/25] coresight: etm4x: Support for system instructions Mike Leach
2021-01-06 14:52   ` Suzuki K Poulose

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