linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	leo.yan@linaro.org, jonathan.zhouwen@huawei.com,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 04/25] coresight: tpiu: Prepare for using coresight device access abstraction
Date: Mon, 14 Dec 2020 17:37:10 +0000	[thread overview]
Message-ID: <20201214173731.302520-5-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201214173731.302520-1-suzuki.poulose@arm.com>

Prepare the TPIU driver to make use of the CoreSight device access
abstraction layer. The driver touches the device even before the
coresight device is registered. Thus we could be accessing the
devices without a csdev. As we are about to use the abstraction
layer for accessing the device, pass in the access directly
to avoid having to deal with the un-initialised csdev.

Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tpiu.c | 30 +++++++++-----------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
index 6ca396799883..a12b6ee0a576 100644
--- a/drivers/hwtracing/coresight/coresight-tpiu.c
+++ b/drivers/hwtracing/coresight/coresight-tpiu.c
@@ -60,49 +60,45 @@ struct tpiu_drvdata {
 	struct coresight_device	*csdev;
 };
 
-static void tpiu_enable_hw(struct tpiu_drvdata *drvdata)
+static void tpiu_enable_hw(struct csdev_access *csa)
 {
-	CS_UNLOCK(drvdata->base);
+	CS_UNLOCK(csa->base);
 
 	/* TODO: fill this up */
 
-	CS_LOCK(drvdata->base);
+	CS_LOCK(csa->base);
 }
 
 static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)
 {
-	struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
-
-	tpiu_enable_hw(drvdata);
+	tpiu_enable_hw(&csdev->access);
 	atomic_inc(csdev->refcnt);
 	dev_dbg(&csdev->dev, "TPIU enabled\n");
 	return 0;
 }
 
-static void tpiu_disable_hw(struct tpiu_drvdata *drvdata)
+static void tpiu_disable_hw(struct csdev_access *csa)
 {
-	CS_UNLOCK(drvdata->base);
+	CS_UNLOCK(csa->base);
 
 	/* Clear formatter and stop on flush */
-	writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR);
+	csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
 	/* Generate manual flush */
-	writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR);
+	csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
 	/* Wait for flush to complete */
-	coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
+	coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
 	/* Wait for formatter to stop */
-	coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
+	coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
 
-	CS_LOCK(drvdata->base);
+	CS_LOCK(csa->base);
 }
 
 static int tpiu_disable(struct coresight_device *csdev)
 {
-	struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
-
 	if (atomic_dec_return(csdev->refcnt))
 		return -EBUSY;
 
-	tpiu_disable_hw(drvdata);
+	tpiu_disable_hw(&csdev->access);
 
 	dev_dbg(&csdev->dev, "TPIU disabled\n");
 	return 0;
@@ -152,7 +148,7 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id)
 	desc.access = CSDEV_ACCESS_IOMEM(base);
 
 	/* Disable tpiu to support older devices */
-	tpiu_disable_hw(drvdata);
+	tpiu_disable_hw(&desc.access);
 
 	pdata = coresight_get_platform_data(dev);
 	if (IS_ERR(pdata))
-- 
2.24.1


  parent reply	other threads:[~2020-12-14 17:53 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-14 17:37 [PATCH v5 00/25] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-12-14 17:37 ` Suzuki K Poulose [this message]
2020-12-14 17:37 ` [PATCH v5 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-12-16 18:01   ` Mike Leach
2020-12-14 17:37 ` [PATCH v5 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-05 21:44   ` Mathieu Poirier
2020-12-14 17:37 ` [PATCH v5 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2021-01-06 14:48 ` [PATCH v5 00/25] coresight: etm4x: Support for system instructions Mike Leach
2021-01-06 14:52   ` Suzuki K Poulose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201214173731.302520-5-suzuki.poulose@arm.com \
    --to=suzuki.poulose@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=jonathan.zhouwen@huawei.com \
    --cc=leo.yan@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mathieu.poirier@linaro.org \
    --cc=mike.leach@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).