From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org, jonathan.zhouwen@huawei.com,
Will Deacon <will@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 25/25] coresight: Add support for v8.4 SelfHosted tracing
Date: Mon, 14 Dec 2020 17:37:31 +0000 [thread overview]
Message-ID: <20201214173731.302520-26-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201214173731.302520-1-suzuki.poulose@arm.com>
From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
v8.4 tracing extensions added support for trace filtering controlled
by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and
EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2
tracing if we are running the kernel at EL2.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[ Move the trace filtering setup etm_init_arch_data() and
clean ups]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
.../coresight/coresight-etm4x-core.c | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index fe38c81e0bed..3d62acb2307f 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -760,6 +760,30 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
return false;
}
+static void cpu_enable_tracing(void)
+{
+ u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
+ u64 trfcr;
+
+ if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
+ return;
+
+ /*
+ * If the CPU supports v8.4 SelfHosted Tracing, enable
+ * tracing at the kernel EL and EL0, forcing to use the
+ * virtual time as the timestamp.
+ */
+ trfcr = (TRFCR_ELx_TS_VIRTUAL |
+ TRFCR_ELx_ExTRE |
+ TRFCR_ELx_E0TRE);
+
+ /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
+ if (is_kernel_in_hyp_mode())
+ trfcr |= TRFCR_EL2_CX;
+
+ write_sysreg_s(trfcr, SYS_TRFCR_EL1);
+}
+
static void etm4_init_arch_data(void *info)
{
u32 etmidr0;
@@ -943,6 +967,7 @@ static void etm4_init_arch_data(void *info)
/* NUMCNTR, bits[30:28] number of counters available for tracing */
drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
etm4_cs_lock(drvdata, csa);
+ cpu_enable_tracing();
}
static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
--
2.24.1
next prev parent reply other threads:[~2020-12-14 17:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-14 17:37 [PATCH v5 00/25] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-12-16 18:01 ` Mike Leach
2020-12-14 17:37 ` [PATCH v5 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-05 21:44 ` Mathieu Poirier
2020-12-14 17:37 ` [PATCH v5 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-12-14 17:37 ` Suzuki K Poulose [this message]
2021-01-06 14:48 ` [PATCH v5 00/25] coresight: etm4x: Support for system instructions Mike Leach
2021-01-06 14:52 ` Suzuki K Poulose
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