From: lakshmi.sowjanya.d@intel.com
To: linus.walleij@linaro.org
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
andriy.shevchenko@linux.intel.com,
lakshmi.bai.raja.subramanian@intel.com, tamal.saha@intel.com,
lakshmi.sowjanya.d@intel.com
Subject: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver
Date: Fri, 16 Jul 2021 21:57:23 +0530 [thread overview]
Message-ID: <20210716162724.26047-2-lakshmi.sowjanya.d@intel.com> (raw)
In-Reply-To: <20210716162724.26047-1-lakshmi.sowjanya.d@intel.com>
From: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
Add Device Tree bindings documentation for Intel Keem Bay
SoC's pin controller.
Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file
Acked-by: Mark Gross <mgross@linux.intel.com>
Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
---
.../pinctrl/intel,pinctrl-keembay.yaml | 134 ++++++++++++++++++
MAINTAINERS | 5 +
2 files changed, 139 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
new file mode 100644
index 000000000000..6c6f45ac75a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay pin controller Device Tree Bindings
+
+maintainers:
+ - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
+
+description: |
+ Intel Keem Bay SoC integrates a pin controller which enables control
+ of pin directions, input/output values and configuration
+ for a total of 80 pins.
+
+properties:
+ compatible:
+ const: intel,keembay-pinctrl
+
+ reg:
+ maxItems: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ ngpios:
+ description: The number of GPIOs exposed.
+ const: 80
+
+ interrupts:
+ description:
+ Specifies the interrupt lines to be used by the controller.
+ maxItems: 8
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+patternProperties:
+ '^gpio@[0-9a-f]*$':
+ type: object
+
+ description:
+ Child nodes can be specified to contain pin configuration information,
+ which can then be utilized by pinctrl client devices.
+ The following properties are supported.
+
+ properties:
+ pins:
+ description: |
+ The name(s) of the pins to be configured in the child node.
+ Supported pin names are "GPIO0" up to "GPIO79".
+
+ bias-disable: true
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ drive-strength:
+ description: IO pads drive strength in milli Ampere.
+ enum: [2, 4, 8, 12]
+
+ bias-bus-hold:
+ type: boolean
+
+ input-schmitt-enable:
+ type: boolean
+
+ slew-rate:
+ description: GPIO slew rate control.
+ 0 - Fast(~100MHz)
+ 1 - Slow(~50MHz)
+ enum: [0, 1]
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - ngpios
+ - '#gpio-cells'
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ // Example 1
+ gpio@0 {
+ compatible = "intel,keembay-pinctrl";
+ reg = <0x600b0000 0x88>,
+ <0x600b0190 0x1ac>;
+ gpio-controller;
+ ngpios = <0x50>;
+ #gpio-cells = <0x2>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ // Example 2
+ gpio@1 {
+ compatible = "intel,keembay-pinctrl";
+ reg = <0x600c0000 0x88>,
+ <0x600c0190 0x1ac>;
+ gpio-controller;
+ ngpios = <0x50>;
+ #gpio-cells = <0x2>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 6c8be735cc91..f2f3fda0bf60 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14636,6 +14636,11 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
F: drivers/pinctrl/intel/
+PIN CONTROLLER - KEEMBAY
+M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
+S: Supported
+F: drivers/pinctrl/pinctrl-keembay*
+
PIN CONTROLLER - MEDIATEK
M: Sean Wang <sean.wang@kernel.org>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
--
2.17.1
next prev parent reply other threads:[~2021-07-16 16:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 16:27 [PATCH v3 0/2] Add pinctrl support for Intel Keem Bay SoC lakshmi.sowjanya.d
2021-07-16 16:27 ` lakshmi.sowjanya.d [this message]
2021-07-30 9:05 ` [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver Linus Walleij
2021-07-30 11:29 ` Andy Shevchenko
2021-07-30 11:58 ` Linus Walleij
2021-07-30 9:15 ` Linus Walleij
2021-07-30 11:06 ` D, Lakshmi Sowjanya
2021-07-16 16:27 ` [PATCH v3 2/2] pinctrl: Add Intel Keem Bay " lakshmi.sowjanya.d
2021-07-28 19:16 ` [kbuild] " Dan Carpenter
2021-07-30 11:05 ` D, Lakshmi Sowjanya
2021-07-30 9:13 ` Linus Walleij
2021-07-30 9:32 ` Andy Shevchenko
2021-07-30 11:06 ` D, Lakshmi Sowjanya
2021-07-30 11:30 ` Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210716162724.26047-2-lakshmi.sowjanya.d@intel.com \
--to=lakshmi.sowjanya.d@intel.com \
--cc=andriy.shevchenko@linux.intel.com \
--cc=lakshmi.bai.raja.subramanian@intel.com \
--cc=linus.walleij@linaro.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=tamal.saha@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).