* [PATCH 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
@ 2022-04-11 6:55 ` Rohit Agarwal
2022-04-11 7:30 ` Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 2/7] dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible Rohit Agarwal
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Rohit Agarwal @ 2022-04-11 6:55 UTC (permalink / raw)
To: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson
Cc: linux-arm-kernel, iommu, devicetree, linux-kernel, linux-mmc,
linux-arm-msm, Rohit Agarwal
Add reserved memory nodes to the SDX65 dtsi as defined by
the memory map.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 +++++++++++++++++
arch/arm/boot/dts/qcom-sdx65.dtsi | 45 ++++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index ad99f56..5d51cc4 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -23,6 +23,27 @@
stdout-path = "serial0:115200n8";
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mpss_dsm: mpss_dsm_region@8c400000 {
+ no-map;
+ reg = <0x8c400000 0x3200000>;
+ };
+
+ ipa_fw_mem: ipa_fw_region@8fced000 {
+ no-map;
+ reg = <0x8fced000 0x10000>;
+ };
+
+ mpss_adsp_mem: mpss_adsp_region@90800000 {
+ no-map;
+ reg = <0x90800000 0x10000000>;
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 7e2697f..365df74 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -66,6 +66,51 @@
reg = <0x8fee0000 0x20000>;
no-map;
};
+
+ secdata_mem: secdata_region@8fcfd000 {
+ no-map;
+ reg = <0x8fcfd000 0x1000>;
+ };
+
+ hyp_mem: hyp_region@8fd00000 {
+ no-map;
+ reg = <0x8fd00000 0x80000>;
+ };
+
+ aop_mem: aop_regions@8fe00000 {
+ no-map;
+ reg = <0x8fe00000 0x20000>;
+ };
+
+ access_control_mem: access_control_region@8fd80000 {
+ no-map;
+ reg = <0x8fd80000 0x80000>;
+ };
+
+ smem_mem: smem_region@8fe20000 {
+ no-map;
+ reg = <0x8fe20000 0xc0000>;
+ };
+
+ tz_mem: tz_mem_region@8ff00000 {
+ no-map;
+ reg = <0x8ff00000 0x100000>;
+ };
+
+ tz_apps_mem: tz_apps_mem_region@90000000 {
+ no-map;
+ reg = <0x90000000 0x500000>;
+ };
+
+ tz_heap_mem: tz_heap_region@8fcad000 {
+ no-map;
+ reg = <0x8fcad000 0x40000>;
+ };
+
+ llcc_tcm_mem: llcc_tcm_region@15800000 {
+ no-map;
+ reg = <0x15800000 0x800000>;
+ };
};
soc: soc {
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes
2022-04-11 6:55 ` [PATCH 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes Rohit Agarwal
@ 2022-04-11 7:30 ` Manivannan Sadhasivam
0 siblings, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-04-11 7:30 UTC (permalink / raw)
To: Rohit Agarwal
Cc: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson, linux-arm-kernel, iommu, devicetree,
linux-kernel, linux-mmc, linux-arm-msm
On Mon, Apr 11, 2022 at 12:25:37PM +0530, Rohit Agarwal wrote:
> Add reserved memory nodes to the SDX65 dtsi as defined by
> the memory map.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 +++++++++++++++++
> arch/arm/boot/dts/qcom-sdx65.dtsi | 45 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 66 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> index ad99f56..5d51cc4 100644
> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> @@ -23,6 +23,27 @@
> stdout-path = "serial0:115200n8";
> };
>
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mpss_dsm: mpss_dsm_region@8c400000 {
Node name should be generic. So please use "memory@" here and below.
Thanks,
Mani
> + no-map;
> + reg = <0x8c400000 0x3200000>;
> + };
> +
> + ipa_fw_mem: ipa_fw_region@8fced000 {
> + no-map;
> + reg = <0x8fced000 0x10000>;
> + };
> +
> + mpss_adsp_mem: mpss_adsp_region@90800000 {
> + no-map;
> + reg = <0x90800000 0x10000000>;
> + };
> + };
> +
> vph_pwr: vph-pwr-regulator {
> compatible = "regulator-fixed";
> regulator-name = "vph_pwr";
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 7e2697f..365df74 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -66,6 +66,51 @@
> reg = <0x8fee0000 0x20000>;
> no-map;
> };
> +
> + secdata_mem: secdata_region@8fcfd000 {
> + no-map;
> + reg = <0x8fcfd000 0x1000>;
> + };
> +
> + hyp_mem: hyp_region@8fd00000 {
> + no-map;
> + reg = <0x8fd00000 0x80000>;
> + };
> +
> + aop_mem: aop_regions@8fe00000 {
> + no-map;
> + reg = <0x8fe00000 0x20000>;
> + };
> +
> + access_control_mem: access_control_region@8fd80000 {
> + no-map;
> + reg = <0x8fd80000 0x80000>;
> + };
> +
> + smem_mem: smem_region@8fe20000 {
> + no-map;
> + reg = <0x8fe20000 0xc0000>;
> + };
> +
> + tz_mem: tz_mem_region@8ff00000 {
> + no-map;
> + reg = <0x8ff00000 0x100000>;
> + };
> +
> + tz_apps_mem: tz_apps_mem_region@90000000 {
> + no-map;
> + reg = <0x90000000 0x500000>;
> + };
> +
> + tz_heap_mem: tz_heap_region@8fcad000 {
> + no-map;
> + reg = <0x8fcad000 0x40000>;
> + };
> +
> + llcc_tcm_mem: llcc_tcm_region@15800000 {
> + no-map;
> + reg = <0x15800000 0x800000>;
> + };
> };
>
> soc: soc {
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/7] dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
2022-04-11 6:55 ` [PATCH 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes Rohit Agarwal
@ 2022-04-11 6:55 ` Rohit Agarwal
2022-04-11 6:55 ` [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller Rohit Agarwal
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Rohit Agarwal @ 2022-04-11 6:55 UTC (permalink / raw)
To: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson
Cc: linux-arm-kernel, iommu, devicetree, linux-kernel, linux-mmc,
linux-arm-msm, Rohit Agarwal
The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence,
document the compatible with "qcom,sdhci-msm-v5" as the fallback.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 6a8cc26..e1023e8 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -24,6 +24,7 @@ Required properties:
"qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
"qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
+ "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
"qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
NOTE that some old device tree files may be floating around that only
have the string "qcom,sdhci-msm-v4" without the SoC compatible string
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
2022-04-11 6:55 ` [PATCH 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes Rohit Agarwal
2022-04-11 6:55 ` [PATCH 2/7] dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible Rohit Agarwal
@ 2022-04-11 6:55 ` Rohit Agarwal
2022-04-11 7:31 ` Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 4/7] dt-bindings: arm-smmu: Add binding for SDX65 SMMU Rohit Agarwal
` (4 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Rohit Agarwal @ 2022-04-11 6:55 UTC (permalink / raw)
To: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson
Cc: linux-arm-kernel, iommu, devicetree, linux-kernel, linux-mmc,
linux-arm-msm, Rohit Agarwal
Add devicetree support for SDHCI controller found in Qualcomm SDX65
platform. The SDHCI controller is based on the MSM SDHCI v5 IP.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 365df74..632ac78 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -168,6 +168,19 @@
#interrupt-cells = <2>;
};
+ sdhc_1: sdhci@8804000 {
+ compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x08804000 0x1000>;
+ reg-names = "hc_mem";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx65-pdc", "qcom,pdc";
reg = <0xb210000 0x10000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller
2022-04-11 6:55 ` [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller Rohit Agarwal
@ 2022-04-11 7:31 ` Manivannan Sadhasivam
0 siblings, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-04-11 7:31 UTC (permalink / raw)
To: Rohit Agarwal
Cc: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson, linux-arm-kernel, iommu, devicetree,
linux-kernel, linux-mmc, linux-arm-msm
On Mon, Apr 11, 2022 at 12:25:39PM +0530, Rohit Agarwal wrote:
> Add devicetree support for SDHCI controller found in Qualcomm SDX65
> platform. The SDHCI controller is based on the MSM SDHCI v5 IP.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 365df74..632ac78 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -168,6 +168,19 @@
> #interrupt-cells = <2>;
> };
>
> + sdhc_1: sdhci@8804000 {
> + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x08804000 0x1000>;
> + reg-names = "hc_mem";
> + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> + clocks = <&gcc GCC_SDCC1_APPS_CLK>,
> + <&gcc GCC_SDCC1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> pdc: interrupt-controller@b210000 {
> compatible = "qcom,sdx65-pdc", "qcom,pdc";
> reg = <0xb210000 0x10000>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/7] dt-bindings: arm-smmu: Add binding for SDX65 SMMU
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
` (2 preceding siblings ...)
2022-04-11 6:55 ` [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller Rohit Agarwal
@ 2022-04-11 6:55 ` Rohit Agarwal
2022-04-11 6:55 ` [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Rohit Agarwal
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Rohit Agarwal @ 2022-04-11 6:55 UTC (permalink / raw)
To: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson
Cc: linux-arm-kernel, iommu, devicetree, linux-kernel, linux-mmc,
linux-arm-msm, Rohit Agarwal
Add devicetree binding for Qualcomm SDX65 SMMU.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index da5381c..1f99bff 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,sc8180x-smmu-500
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
+ - qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
` (3 preceding siblings ...)
2022-04-11 6:55 ` [PATCH 4/7] dt-bindings: arm-smmu: Add binding for SDX65 SMMU Rohit Agarwal
@ 2022-04-11 6:55 ` Rohit Agarwal
2022-04-11 7:32 ` Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Rohit Agarwal
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Rohit Agarwal @ 2022-04-11 6:55 UTC (permalink / raw)
To: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson
Cc: linux-arm-kernel, iommu, devicetree, linux-kernel, linux-mmc,
linux-arm-msm, Rohit Agarwal
Add a node for the ARM SMMU found in the SDX65.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 632ac78..2481769 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -181,6 +181,46 @@
status = "disabled";
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
+ reg = <0x15000000 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx65-pdc", "qcom,pdc";
reg = <0xb210000 0x10000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU
2022-04-11 6:55 ` [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Rohit Agarwal
@ 2022-04-11 7:32 ` Manivannan Sadhasivam
0 siblings, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-04-11 7:32 UTC (permalink / raw)
To: Rohit Agarwal
Cc: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson, linux-arm-kernel, iommu, devicetree,
linux-kernel, linux-mmc, linux-arm-msm
On Mon, Apr 11, 2022 at 12:25:41PM +0530, Rohit Agarwal wrote:
> Add a node for the ARM SMMU found in the SDX65.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 632ac78..2481769 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -181,6 +181,46 @@
> status = "disabled";
> };
>
> + apps_smmu: iommu@15000000 {
Please sort the nodes in ascending order.
Thanks,
Mani
> + compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
> + reg = <0x15000000 0x40000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> pdc: interrupt-controller@b210000 {
> compatible = "qcom,sdx65-pdc", "qcom,pdc";
> reg = <0xb210000 0x10000>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
` (4 preceding siblings ...)
2022-04-11 6:55 ` [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Rohit Agarwal
@ 2022-04-11 6:55 ` Rohit Agarwal
2022-04-11 7:33 ` Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 7/7] ARM: dts: qcom: sdx65: Add Shared memory manager support Rohit Agarwal
2022-04-11 7:27 ` [PATCH 0/7] SDX65 devicetree updates Manivannan Sadhasivam
7 siblings, 1 reply; 13+ messages in thread
From: Rohit Agarwal @ 2022-04-11 6:55 UTC (permalink / raw)
To: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson
Cc: linux-arm-kernel, iommu, devicetree, linux-kernel, linux-mmc,
linux-arm-msm, Rohit Agarwal
Add TCSR Mutex node to support Qualcomm Hardware Mutex block
on SDX65 platform.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 2481769..5c28c94 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -168,6 +168,12 @@
#interrupt-cells = <2>;
};
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01f40000 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
sdhc_1: sdhci@8804000 {
compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex
2022-04-11 6:55 ` [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Rohit Agarwal
@ 2022-04-11 7:33 ` Manivannan Sadhasivam
0 siblings, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-04-11 7:33 UTC (permalink / raw)
To: Rohit Agarwal
Cc: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson, linux-arm-kernel, iommu, devicetree,
linux-kernel, linux-mmc, linux-arm-msm
On Mon, Apr 11, 2022 at 12:25:42PM +0530, Rohit Agarwal wrote:
> Add TCSR Mutex node to support Qualcomm Hardware Mutex block
> on SDX65 platform.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 2481769..5c28c94 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -168,6 +168,12 @@
> #interrupt-cells = <2>;
> };
>
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x01f40000 0x40000>;
> + #hwlock-cells = <1>;
> + };
> +
> sdhc_1: sdhci@8804000 {
> compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
> reg = <0x08804000 0x1000>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 7/7] ARM: dts: qcom: sdx65: Add Shared memory manager support
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
` (5 preceding siblings ...)
2022-04-11 6:55 ` [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Rohit Agarwal
@ 2022-04-11 6:55 ` Rohit Agarwal
2022-04-11 7:27 ` [PATCH 0/7] SDX65 devicetree updates Manivannan Sadhasivam
7 siblings, 0 replies; 13+ messages in thread
From: Rohit Agarwal @ 2022-04-11 6:55 UTC (permalink / raw)
To: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson
Cc: linux-arm-kernel, iommu, devicetree, linux-kernel, linux-mmc,
linux-arm-msm, Rohit Agarwal
Add smem node to support shared memory manager on SDX65 platform.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 5c28c94..b0eec91 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -174,6 +174,12 @@
#hwlock-cells = <1>;
};
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
sdhc_1: sdhci@8804000 {
compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 0/7] SDX65 devicetree updates
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
` (6 preceding siblings ...)
2022-04-11 6:55 ` [PATCH 7/7] ARM: dts: qcom: sdx65: Add Shared memory manager support Rohit Agarwal
@ 2022-04-11 7:27 ` Manivannan Sadhasivam
7 siblings, 0 replies; 13+ messages in thread
From: Manivannan Sadhasivam @ 2022-04-11 7:27 UTC (permalink / raw)
To: Rohit Agarwal
Cc: will, robin.murphy, joro, robh+dt, krzk+dt, ulf.hansson, agross,
bjorn.andersson, linux-arm-kernel, iommu, devicetree,
linux-kernel, linux-mmc, linux-arm-msm
On Mon, Apr 11, 2022 at 12:25:36PM +0530, Rohit Agarwal wrote:
> Hello,
>
> This series adds devicetree nodes for SDX65. It adds
> reserved memory nodes, SDHCI, smmu and tcsr mutex support.
>
Please CC me to all SDX65 related patches as I'd like to review them.
Thanks,
Mani
> Thanks,
> Rohit.
>
> Rohit Agarwal (7):
> ARM: dts: qcom: sdx65: Add reserved memory nodes
> dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible
> ARM: dts: qcom: sdx65: Add support for SDHCI controller
> dt-bindings: arm-smmu: Add binding for SDX65 SMMU
> ARM: dts: qcom: sdx65: Enable ARM SMMU
> ARM: dts: qcom: sdx65: Add support for TCSR Mutex
> ARM: dts: qcom: sdx65: Add Shared memory manager support
>
> .../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
> .../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 ++++
> arch/arm/boot/dts/qcom-sdx65.dtsi | 110 +++++++++++++++++++++
> 4 files changed, 133 insertions(+)
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread