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From: Nick Forrington <nick.forrington@arm.com>
To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	acme@kernel.org
Cc: Nick Forrington <nick.forrington@arm.com>,
	John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Leo Yan <leo.yan@linaro.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
	Andi Kleen <ak@linux.intel.com>, Kajol Jain <kjain@linux.ibm.com>,
	James Clark <james.clark@arm.com>,
	Andrew Kilroy <andrew.kilroy@arm.com>
Subject: [PATCH 09/20] perf vendors events arm64: Arm Cortex-A35
Date: Tue, 10 May 2022 11:47:47 +0100	[thread overview]
Message-ID: <20220510104758.64677-10-nick.forrington@arm.com> (raw)
In-Reply-To: <20220510104758.64677-1-nick.forrington@arm.com>

Add PMU events for Arm Cortex-A35
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a35.json

which is based on PMU event descriptions from the Arm Cortex-A35 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json

which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Signed-off-by: Nick Forrington <nick.forrington@arm.com>
---
 .../arch/arm64/arm/cortex-a35/branch.json     | 11 +++++
 .../arch/arm64/arm/cortex-a35/bus.json        | 17 +++++++
 .../arch/arm64/arm/cortex-a35/cache.json      | 32 ++++++++++++++
 .../arch/arm64/arm/cortex-a35/exception.json  | 14 ++++++
 .../arm64/arm/cortex-a35/instruction.json     | 44 +++++++++++++++++++
 .../arch/arm64/arm/cortex-a35/memory.json     |  8 ++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv  |  1 +
 7 files changed, 127 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
new file mode 100644
index 000000000000..ece201718284
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json
@@ -0,0 +1,11 @@
+[
+    {
+        "ArchStdEvent": "BR_MIS_PRED"
+    },
+    {
+        "ArchStdEvent": "BR_PRED"
+    },
+    {
+        "ArchStdEvent": "BR_INDIRECT_SPEC"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
new file mode 100644
index 000000000000..75d850b781ac
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json
@@ -0,0 +1,17 @@
+[
+    {
+        "ArchStdEvent": "CPU_CYCLES"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS"
+    },
+    {
+        "ArchStdEvent": "BUS_CYCLES"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS_RD"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS_WR"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
new file mode 100644
index 000000000000..8a9a95e05c32
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json
@@ -0,0 +1,32 @@
+[
+    {
+        "ArchStdEvent": "L1I_CACHE_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1I_TLB_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE"
+    },
+    {
+        "ArchStdEvent": "L1D_TLB_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1I_CACHE"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_REFILL"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_WB"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
new file mode 100644
index 000000000000..27c3fe9c831a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json
@@ -0,0 +1,14 @@
+[
+    {
+        "ArchStdEvent": "EXC_TAKEN"
+    },
+    {
+        "ArchStdEvent": "MEMORY_ERROR"
+    },
+    {
+        "ArchStdEvent": "EXC_IRQ"
+    },
+    {
+        "ArchStdEvent": "EXC_FIQ"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
new file mode 100644
index 000000000000..df9f94cfc8d5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json
@@ -0,0 +1,44 @@
+[
+    {
+        "ArchStdEvent": "SW_INCR"
+    },
+    {
+        "ArchStdEvent": "LD_RETIRED"
+    },
+    {
+        "ArchStdEvent": "ST_RETIRED"
+    },
+    {
+        "ArchStdEvent": "INST_RETIRED"
+    },
+    {
+        "ArchStdEvent": "EXC_RETURN"
+    },
+    {
+        "ArchStdEvent": "CID_WRITE_RETIRED"
+    },
+    {
+        "ArchStdEvent": "PC_WRITE_RETIRED"
+    },
+    {
+        "ArchStdEvent": "BR_IMMED_RETIRED"
+    },
+    {
+        "ArchStdEvent": "BR_RETURN_RETIRED"
+    },
+    {
+        "ArchStdEvent": "INST_SPEC"
+    },
+    {
+        "ArchStdEvent": "DP_SPEC"
+    },
+    {
+        "ArchStdEvent": "ASE_SPEC"
+    },
+    {
+        "ArchStdEvent": "VFP_SPEC"
+    },
+    {
+        "ArchStdEvent": "CRYPTO_SPEC"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
new file mode 100644
index 000000000000..2c319f936957
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json
@@ -0,0 +1,8 @@
+[
+    {
+        "ArchStdEvent": "UNALIGNED_LDST_RETIRED"
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 286f98d5805a..2ce90180e3fa 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -22,6 +22,7 @@
 0x00000000410fd020,v1,arm/cortex-a34,core
 0x00000000410fd030,v1,arm/cortex-a53,core
 0x00000000420f1000,v1,arm/cortex-a53,core
+0x00000000410fd040,v1,arm/cortex-a35,core
 0x00000000410fd070,v1,arm/cortex-a57-a72,core
 0x00000000410fd080,v1,arm/cortex-a57-a72,core
 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
-- 
2.25.1


  parent reply	other threads:[~2022-05-10 10:51 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-10 10:47 [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs Nick Forrington
2022-05-10 10:47 ` [PATCH 01/20] perf vendors events arm64: Arm Cortex-A5 Nick Forrington
2022-05-12 15:32   ` John Garry
2022-05-10 10:47 ` [PATCH 02/20] perf vendors events arm64: Arm Cortex-A7 Nick Forrington
2022-05-10 10:47 ` [PATCH 03/20] perf vendors events arm64: Arm Cortex-A8 Nick Forrington
2022-05-10 10:47 ` [PATCH 04/20] perf vendors events arm64: Arm Cortex-A9 Nick Forrington
2022-05-10 10:47 ` [PATCH 05/20] perf vendors events arm64: Arm Cortex-A15 Nick Forrington
2022-05-10 10:47 ` [PATCH 06/20] perf vendors events arm64: Arm Cortex-A17 Nick Forrington
2022-05-18 12:58   ` Robin Murphy
2022-05-10 10:47 ` [PATCH 07/20] perf vendors events arm64: Arm Cortex-A32 Nick Forrington
2022-05-10 10:47 ` [PATCH 08/20] perf vendors events arm64: Arm Cortex-A34 Nick Forrington
2022-05-10 10:47 ` Nick Forrington [this message]
2022-05-10 10:47 ` [PATCH 10/20] perf vendors events arm64: Arm Cortex-A55 Nick Forrington
2022-05-10 10:47 ` [PATCH 11/20] perf vendors events arm64: Arm Cortex-A510 Nick Forrington
2022-05-10 10:47 ` [PATCH 12/20] perf vendors events arm64: Arm Cortex-A65 Nick Forrington
2022-05-10 10:47 ` [PATCH 13/20] perf vendors events arm64: Arm Cortex-A73 Nick Forrington
2022-05-10 10:47 ` [PATCH 14/20] perf vendors events arm64: Arm Cortex-A75 Nick Forrington
2022-05-10 10:47 ` [PATCH 15/20] perf vendors events arm64: Arm Cortex-A77 Nick Forrington
2022-05-10 10:47 ` [PATCH 16/20] perf vendors events arm64: Arm Cortex-A78 Nick Forrington
2022-05-10 10:47 ` [PATCH 17/20] perf vendors events arm64: Arm Cortex-A710 Nick Forrington
2022-05-10 10:47 ` [PATCH 18/20] perf vendors events arm64: Arm Cortex-X1 Nick Forrington
2022-05-10 10:47 ` [PATCH 19/20] perf vendors events arm64: Arm Cortex-X2 Nick Forrington
2022-05-10 10:47 ` [PATCH 20/20] perf vendors events arm64: Arm Neoverse E1 Nick Forrington
2022-05-10 15:50 ` [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs Arnaldo Carvalho de Melo
2022-05-10 15:55   ` John Garry
2022-05-12 13:01     ` Nick Forrington
2022-05-12 15:52       ` John Garry
2022-05-15 22:03         ` Ian Rogers
2022-05-16 11:10           ` John Garry
2022-05-16 20:29             ` Ian Rogers
2022-05-16 18:05           ` Nick Forrington
2022-05-16  9:25         ` Nick Forrington
2022-05-17 14:32 ` Robin Murphy
2022-05-18  8:15   ` John Garry
2022-05-18 12:32     ` Robin Murphy
2022-05-18 13:48       ` John Garry
2022-05-18 14:14         ` Robin Murphy
2022-05-19  7:59           ` John Garry
2022-05-19 13:50             ` Nick Forrington
2022-05-20 17:28               ` Ian Rogers
2022-05-19 13:42     ` Nick Forrington

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