From: Nick Forrington <nick.forrington@arm.com>
To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
acme@kernel.org
Cc: Nick Forrington <nick.forrington@arm.com>,
John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Leo Yan <leo.yan@linaro.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Andi Kleen <ak@linux.intel.com>, Kajol Jain <kjain@linux.ibm.com>,
James Clark <james.clark@arm.com>,
Andrew Kilroy <andrew.kilroy@arm.com>
Subject: [PATCH 15/20] perf vendors events arm64: Arm Cortex-A77
Date: Tue, 10 May 2022 11:47:53 +0100 [thread overview]
Message-ID: <20220510104758.64677-16-nick.forrington@arm.com> (raw)
In-Reply-To: <20220510104758.64677-1-nick.forrington@arm.com>
Add PMU events for Arm Cortex-A77
Update mapfile.csv
Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a77.json
which is based on PMU event descriptions from the Arm Cortex-A77 Technical
Reference Manual.
Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json
which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.
Signed-off-by: Nick Forrington <nick.forrington@arm.com>
---
.../arch/arm64/arm/cortex-a77/branch.json | 17 +++
.../arch/arm64/arm/cortex-a77/bus.json | 17 +++
.../arch/arm64/arm/cortex-a77/cache.json | 143 ++++++++++++++++++
.../arch/arm64/arm/cortex-a77/exception.json | 47 ++++++
.../arm64/arm/cortex-a77/instruction.json | 77 ++++++++++
.../arch/arm64/arm/cortex-a77/memory.json | 23 +++
.../arch/arm64/arm/cortex-a77/pipeline.json | 8 +
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
8 files changed, 333 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
new file mode 100644
index 000000000000..2f2d137f5f55
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "BR_MIS_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_PRED"
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC"
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
new file mode 100644
index 000000000000..75d850b781ac
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
@@ -0,0 +1,17 @@
+[
+ {
+ "ArchStdEvent": "CPU_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS"
+ },
+ {
+ "ArchStdEvent": "BUS_CYCLES"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
new file mode 100644
index 000000000000..cbb365f5091f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
@@ -0,0 +1,143 @@
+[
+ {
+ "ArchStdEvent": "L1I_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L1I_CACHE"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB"
+ },
+ {
+ "ArchStdEvent": "L1I_TLB"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_ALLOCATE"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_REFILL"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB"
+ },
+ {
+ "ArchStdEvent": "DTLB_WALK"
+ },
+ {
+ "ArchStdEvent": "ITLB_WALK"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "LL_CACHE_MISS_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_WR"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_RD"
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_WR"
+ },
+ {
+ "ArchStdEvent": "L3D_CACHE_RD"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
new file mode 100644
index 000000000000..344a2d552ad5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json
@@ -0,0 +1,47 @@
+[
+ {
+ "ArchStdEvent": "EXC_TAKEN"
+ },
+ {
+ "ArchStdEvent": "MEMORY_ERROR"
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF"
+ },
+ {
+ "ArchStdEvent": "EXC_SVC"
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ"
+ },
+ {
+ "ArchStdEvent": "EXC_SMC"
+ },
+ {
+ "ArchStdEvent": "EXC_HVC"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ"
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
new file mode 100644
index 000000000000..1a74786271d4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json
@@ -0,0 +1,77 @@
+[
+ {
+ "ArchStdEvent": "SW_INCR"
+ },
+ {
+ "ArchStdEvent": "INST_RETIRED"
+ },
+ {
+ "ArchStdEvent": "EXC_RETURN"
+ },
+ {
+ "ArchStdEvent": "CID_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "INST_SPEC"
+ },
+ {
+ "ArchStdEvent": "TTBR_WRITE_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_RETIRED"
+ },
+ {
+ "ArchStdEvent": "BR_MIS_PRED_RETIRED"
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC"
+ },
+ {
+ "ArchStdEvent": "STREX_SPEC"
+ },
+ {
+ "ArchStdEvent": "LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC"
+ },
+ {
+ "ArchStdEvent": "DP_SPEC"
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC"
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC"
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC"
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC"
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC"
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
new file mode 100644
index 000000000000..5aff6e93c1ad
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
@@ -0,0 +1,23 @@
+[
+ {
+ "ArchStdEvent": "MEM_ACCESS"
+ },
+ {
+ "ArchStdEvent": "REMOTE_ACCESS"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD"
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC"
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
new file mode 100644
index 000000000000..eeac798d403a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json
@@ -0,0 +1,8 @@
+[
+ {
+ "ArchStdEvent": "STALL_FRONTEND"
+ },
+ {
+ "ArchStdEvent": "STALL_BACKEND"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 43cdeae3f1b6..1fa58d247132 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -31,6 +31,7 @@
0x00000000410fd0a0,v1,arm/cortex-a75,core
0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
+0x00000000410fd0d0,v1,arm/cortex-a77,core
0x00000000410fd400,v1,arm/neoverse-v1,core
0x00000000410fd460,v1,arm/cortex-a510,core
0x00000000410fd490,v1,arm/neoverse-n2,core
--
2.25.1
next prev parent reply other threads:[~2022-05-10 10:54 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 10:47 [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs Nick Forrington
2022-05-10 10:47 ` [PATCH 01/20] perf vendors events arm64: Arm Cortex-A5 Nick Forrington
2022-05-12 15:32 ` John Garry
2022-05-10 10:47 ` [PATCH 02/20] perf vendors events arm64: Arm Cortex-A7 Nick Forrington
2022-05-10 10:47 ` [PATCH 03/20] perf vendors events arm64: Arm Cortex-A8 Nick Forrington
2022-05-10 10:47 ` [PATCH 04/20] perf vendors events arm64: Arm Cortex-A9 Nick Forrington
2022-05-10 10:47 ` [PATCH 05/20] perf vendors events arm64: Arm Cortex-A15 Nick Forrington
2022-05-10 10:47 ` [PATCH 06/20] perf vendors events arm64: Arm Cortex-A17 Nick Forrington
2022-05-18 12:58 ` Robin Murphy
2022-05-10 10:47 ` [PATCH 07/20] perf vendors events arm64: Arm Cortex-A32 Nick Forrington
2022-05-10 10:47 ` [PATCH 08/20] perf vendors events arm64: Arm Cortex-A34 Nick Forrington
2022-05-10 10:47 ` [PATCH 09/20] perf vendors events arm64: Arm Cortex-A35 Nick Forrington
2022-05-10 10:47 ` [PATCH 10/20] perf vendors events arm64: Arm Cortex-A55 Nick Forrington
2022-05-10 10:47 ` [PATCH 11/20] perf vendors events arm64: Arm Cortex-A510 Nick Forrington
2022-05-10 10:47 ` [PATCH 12/20] perf vendors events arm64: Arm Cortex-A65 Nick Forrington
2022-05-10 10:47 ` [PATCH 13/20] perf vendors events arm64: Arm Cortex-A73 Nick Forrington
2022-05-10 10:47 ` [PATCH 14/20] perf vendors events arm64: Arm Cortex-A75 Nick Forrington
2022-05-10 10:47 ` Nick Forrington [this message]
2022-05-10 10:47 ` [PATCH 16/20] perf vendors events arm64: Arm Cortex-A78 Nick Forrington
2022-05-10 10:47 ` [PATCH 17/20] perf vendors events arm64: Arm Cortex-A710 Nick Forrington
2022-05-10 10:47 ` [PATCH 18/20] perf vendors events arm64: Arm Cortex-X1 Nick Forrington
2022-05-10 10:47 ` [PATCH 19/20] perf vendors events arm64: Arm Cortex-X2 Nick Forrington
2022-05-10 10:47 ` [PATCH 20/20] perf vendors events arm64: Arm Neoverse E1 Nick Forrington
2022-05-10 15:50 ` [PATCH 00/20] perf vendors events arm64: Multiple Arm CPUs Arnaldo Carvalho de Melo
2022-05-10 15:55 ` John Garry
2022-05-12 13:01 ` Nick Forrington
2022-05-12 15:52 ` John Garry
2022-05-15 22:03 ` Ian Rogers
2022-05-16 11:10 ` John Garry
2022-05-16 20:29 ` Ian Rogers
2022-05-16 18:05 ` Nick Forrington
2022-05-16 9:25 ` Nick Forrington
2022-05-17 14:32 ` Robin Murphy
2022-05-18 8:15 ` John Garry
2022-05-18 12:32 ` Robin Murphy
2022-05-18 13:48 ` John Garry
2022-05-18 14:14 ` Robin Murphy
2022-05-19 7:59 ` John Garry
2022-05-19 13:50 ` Nick Forrington
2022-05-20 17:28 ` Ian Rogers
2022-05-19 13:42 ` Nick Forrington
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