Re: [PATCH 01/20] perf vendors events arm64: Arm Cortex-A5

[John Garry <john.garry@huawei.com>]

On 10/05/2022 11:47, Nick Forrington wrote:
> --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
> +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
> @@ -35,6 +35,18 @@
>           "EventName": "L1D_TLB_REFILL",
>           "BriefDescription": "Attributable Level 1 data TLB refill"
>       },

This is a comment on the general situation of pmu-events support for arm64:

> +    {
> +        "PublicDescription": "Instruction architecturally executed, condition code check pass, load",
> +        "EventCode": "0x06",
> +        "EventName": "LD_RETIRED",
> +        "BriefDescription": "Instruction architecturally executed, condition code check pass, load"
> +    },
> +    {
 > +[
 > +    {
 > +        "ArchStdEvent": "L1I_CACHE_REFILL"
 > +    },

The JSONs for some cores list these common arch events and some don't. 
The effect (if we do) is that the perf tool creates the alias for the 
event and we get all the event info in "perf list", which is useful.

It would be good to have consistency here, but so many arm 
implementations exist and it's tricky to have all cores supported in 
pmu-events. So I had a patch series which makes perf read the armv8 pmu 
sysfs event file to learn all the events which the core supports and 
create the aliases from that. So, in this, we don't require the JSONs to 
list these events explicitly. Maybe I'll revisit it soon.

Thanks,
John