From: Andre Przywara <andre.przywara@arm.com>
To: Samuel Holland <samuel@sholland.org>
Cc: Conor.Dooley@microchip.com, wens@csie.org,
jernej.skrabec@gmail.com, linux-sunxi@lists.linux.dev,
palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
robh+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org,
Geert Uytterhoeven <geert@linux-m68k.org>,
Icenowy Zheng <uwu@icenowy.me>
Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree
Date: Mon, 22 Aug 2022 11:50:02 +0100 [thread overview]
Message-ID: <20220822115002.74003b1c@donnerap.cambridge.arm.com> (raw)
In-Reply-To: <932aaefd-e2ca-ef26-bf30-e315fb271ec5@sholland.org>
On Sat, 20 Aug 2022 12:24:55 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> On 8/15/22 12:01 PM, Conor.Dooley@microchip.com wrote:
> > On 15/08/2022 14:11, Andre Przywara wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Mon, 15 Aug 2022 00:08:09 -0500
> >> Samuel Holland <samuel@sholland.org> wrote:
> >>
> >> Hi,
> >>
> >> thanks for all the efforts in getting those SoC peripherals supported!
> >>
> >>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
> >>> one HiFi 4 DSP. The SoC is based on a design that additionally contained
> >>> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
> >>
> >> So because of this, the Allwinner R528 and T113 SoCs would share almost
> >> everything in this file. Would it be useful to already split this DT up?
> >> To have a base .dtsi, basically this file without /cpus and /soc/plic,
> >> then have a RISC-V specific file with just those, including the base?
> >> There is precedence for this across-arch(-directories) sharing with the
> >> Raspberry Pi and Allwinner H3/H5 SoCs.
> >
> > For those playing along at home, one example is the arm64 bananapi m2
> > dts which looks like:
> >> /dts-v1/;
> >> #include "sun50i-h5.dtsi"
> >> #include "sun50i-h5-cpu-opp.dtsi"
> >> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
> >>
> >> / {
> >> model = "Banana Pi BPI-M2-Plus v1.2 H5";
> >> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
> >> };
> >
> > I think this is a pretty good idea, and putting in the modularity up
> > front seems logical to me, so when the arm one does eventually get
> > added it can be done by only touching a single arch.
>
> This is not feasible, due to the different #interrupt-cells. See
> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>
> Even if we share some file across architectures, you still have to update files
> in both places to get the interrupts properties correct.
There are interrupt-maps for that:
sun8i-r528.dtsi:
soc {
#interrupt-cells = <1>;
interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
....
sun20i-d1.dtsi:
soc {
#interrupt-cells = <1>;
interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>,
<0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>,
then, in the shared .dtsi:
uart0: serial@2500000 {
compatible = "snps,dw-apb-uart";
...
interrupts = <18>;
This is completely untested, but I have all the files spelt out there, and
dtc seems happy for both architectures (outside of the kernel tree for now).
> I get the desire to deduplicate things, but we already deal with updating the
> same/similar nodes across several SoCs, so that is nothing new. I think it would
> be more confusing/complicated to have all of the interrupts properties
> overridden in a separate file.
So is this the only thing that prevents sharing? The above paragraph
sounds a bit you are not very fond of the idea to begin with?
Cheers,
Andre
next prev parent reply other threads:[~2022-08-22 10:50 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 5:08 [PATCH 00/12] riscv: Allwinner D1 platform support Samuel Holland
2022-08-15 5:08 ` [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Samuel Holland
2022-08-15 17:06 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Samuel Holland
2022-08-15 17:07 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-11-04 2:57 ` Icenowy Zheng
2022-11-20 11:23 ` Conor Dooley
2022-11-20 11:25 ` Conor Dooley
2022-08-15 5:08 ` [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors Samuel Holland
2022-08-15 17:12 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-08-15 5:08 ` [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles Samuel Holland
2022-08-16 7:39 ` Krzysztof Kozlowski
2022-08-16 9:02 ` Heiko Stübner
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 17:35 ` Rob Herring
2022-08-15 5:08 ` [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option Samuel Holland
2022-08-15 16:56 ` Conor.Dooley
2022-08-16 9:17 ` Heiko Stübner
2022-08-16 9:23 ` Conor.Dooley
2022-08-15 17:13 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Samuel Holland
2022-08-15 13:11 ` Andre Przywara
2022-08-15 17:01 ` Conor.Dooley
2022-08-20 17:24 ` Samuel Holland
2022-08-20 17:29 ` Conor.Dooley
2022-08-21 6:45 ` Icenowy Zheng
2022-08-21 10:04 ` Conor.Dooley
2022-08-22 11:46 ` Geert Uytterhoeven
2022-08-22 12:13 ` Conor.Dooley
2022-08-22 12:29 ` Andre Przywara
2022-08-22 12:31 ` Geert Uytterhoeven
2022-08-22 13:56 ` Conor.Dooley
2022-08-22 15:29 ` Jessica Clarke
2022-09-09 3:42 ` Samuel Holland
2022-09-09 7:10 ` Geert Uytterhoeven
2022-09-21 7:49 ` Geert Uytterhoeven
2022-08-22 10:50 ` Andre Przywara [this message]
2022-08-16 7:41 ` Krzysztof Kozlowski
2022-08-16 7:49 ` Jernej Škrabec
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 9:25 ` Jernej Škrabec
2022-08-16 9:42 ` Krzysztof Kozlowski
2022-08-16 11:00 ` Andre Przywara
2022-08-16 11:11 ` Krzysztof Kozlowski
2022-08-16 11:12 ` Krzysztof Kozlowski
2022-08-16 11:34 ` Conor.Dooley
2022-08-22 11:40 ` Geert Uytterhoeven
2022-08-16 9:11 ` Heiko Stübner
2022-08-17 8:29 ` Krzysztof Kozlowski
2022-08-19 22:19 ` Conor.Dooley
2022-08-15 5:08 ` [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Samuel Holland
2022-08-15 17:37 ` Conor.Dooley
2022-08-15 18:34 ` Conor.Dooley
2022-08-16 8:55 ` Heiko Stübner
2022-08-19 22:10 ` Conor.Dooley
2022-08-21 7:06 ` Icenowy Zheng
2022-09-04 20:10 ` Peter Korsgaard
2022-09-09 4:37 ` Samuel Holland
2022-09-09 7:18 ` Conor.Dooley
2022-09-09 8:11 ` Heiko Stübner
2022-09-09 19:04 ` Jessica Clarke
2022-09-03 15:21 ` Peter Korsgaard
2022-08-15 5:08 ` [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Samuel Holland
2022-08-15 7:05 ` [PATCH 00/12] riscv: Allwinner D1 platform support Conor.Dooley
2022-08-15 17:12 ` Conor.Dooley
2022-08-16 2:42 ` Samuel Holland
2022-08-16 6:38 ` Conor.Dooley
2022-09-01 18:10 ` Palmer Dabbelt
2022-09-02 5:42 ` Conor.Dooley
2022-09-06 20:29 ` Jernej Škrabec
2022-09-07 20:43 ` Conor.Dooley
2022-09-08 7:00 ` Geert Uytterhoeven
2022-09-08 9:04 ` Arnd Bergmann
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