From: <Conor.Dooley@microchip.com>
To: <geert@linux-m68k.org>, <andre.przywara@arm.com>
Cc: <devicetree@vger.kernel.org>, <aou@eecs.berkeley.edu>,
<samuel@sholland.org>, <linux-kernel@vger.kernel.org>,
<jernej.skrabec@gmail.com>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>, <wens@csie.org>,
<robh+dt@kernel.org>, <palmer@dabbelt.com>,
<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>
Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree
Date: Mon, 22 Aug 2022 12:13:42 +0000 [thread overview]
Message-ID: <538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com> (raw)
In-Reply-To: <CAMuHMdUHVpj9ikE2NxpBSBtTG8K6v92vGdbw3GLmEYUoVzatvg@mail.gmail.com>
Hey Geert,
On 22/08/2022 12:46, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor, Andre,
>
> On Sun, Aug 21, 2022 at 12:07 PM <Conor.Dooley@microchip.com> wrote:
>> On 21/08/2022 07:45, Icenowy Zheng wrote:
>>> 在 2022-08-20星期六的 17:29 +0000,Conor.Dooley@microchip.com写道:
>>>> On 20/08/2022 18:24, Samuel Holland wrote:
>>>>> This is not feasible, due to the different #interrupt-cells. See
>>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>>>>>
>>>>> Even if we share some file across architectures, you still have to
>>>>> update files
>>>>> in both places to get the interrupts properties correct.
>>>>>
>>>>> I get the desire to deduplicate things, but we already deal with
>>>>> updating the
>>>>> same/similar nodes across several SoCs, so that is nothing new. I
>>>>> think it would
>>>>> be more confusing/complicated to have all of the interrupts
>>>>> properties
>>>>> overridden in a separate file.
>>>>
>>>> Yeah, should maybe have circled back after that conversation, would
>>>> have been
>>>> nice but if the DTC can't do it nicely then w/e.
>>>
>>> Well, maybe we can overuse the facility of C preprocessor?
>>>
>>> e.g.
>>>
>>> ```
>>> // For ARM
>>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n
>>> // For RISC-V
>>> #define SOC_PERIPHERAL_IRQ(n) n
>>> ```
>>>
>>
>> Geert pointed out that this is not possible (at least on the Renesas
>> stuff) because the GIC interrupt numbers are not the same as the
>> PLIC's & the DTC is not able to handle the addition:
>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>
> Without the ability to do additions in DTC, we could e.g. list both
> interrupts in the macro, like:
>
> // For ARM
> #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na
> // For RISC-V
> #define SOC_PERIPHERAL_IRQ(na, nr) nr
Do you think this is worth doing? Or are you just providing an
example of what could be done?
Where would you envisage putting these macros? I forget the order
of the CPP operations that are done, can they be put in the dts?
>
> On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <andre.przywara@arm.com> wrote:
>> There are interrupt-maps for that:
>> sun8i-r528.dtsi:
>> soc {
>> #interrupt-cells = <1>;
>> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> ....
>>
>> sun20i-d1.dtsi:
>> soc {
>> #interrupt-cells = <1>;
>> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>,
>> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>,
>>
>> then, in the shared .dtsi:
>> uart0: serial@2500000 {
>> compatible = "snps,dw-apb-uart";
>> ...
>> interrupts = <18>;
>
> Nice! But it's gonna be a very large interrupt-map.
I quite like the idea of not duplicating files across the archs
if it can be helped, but not at the expense of making them hard to
understand & I feel like unfortunately the large interrupt map is
in that territory.
Thanks,
Conor.
next prev parent reply other threads:[~2022-08-22 12:13 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 5:08 [PATCH 00/12] riscv: Allwinner D1 platform support Samuel Holland
2022-08-15 5:08 ` [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Samuel Holland
2022-08-15 17:06 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Samuel Holland
2022-08-15 17:07 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-11-04 2:57 ` Icenowy Zheng
2022-11-20 11:23 ` Conor Dooley
2022-11-20 11:25 ` Conor Dooley
2022-08-15 5:08 ` [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors Samuel Holland
2022-08-15 17:12 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-08-15 5:08 ` [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles Samuel Holland
2022-08-16 7:39 ` Krzysztof Kozlowski
2022-08-16 9:02 ` Heiko Stübner
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 17:35 ` Rob Herring
2022-08-15 5:08 ` [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option Samuel Holland
2022-08-15 16:56 ` Conor.Dooley
2022-08-16 9:17 ` Heiko Stübner
2022-08-16 9:23 ` Conor.Dooley
2022-08-15 17:13 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Samuel Holland
2022-08-15 13:11 ` Andre Przywara
2022-08-15 17:01 ` Conor.Dooley
2022-08-20 17:24 ` Samuel Holland
2022-08-20 17:29 ` Conor.Dooley
2022-08-21 6:45 ` Icenowy Zheng
2022-08-21 10:04 ` Conor.Dooley
2022-08-22 11:46 ` Geert Uytterhoeven
2022-08-22 12:13 ` Conor.Dooley [this message]
2022-08-22 12:29 ` Andre Przywara
2022-08-22 12:31 ` Geert Uytterhoeven
2022-08-22 13:56 ` Conor.Dooley
2022-08-22 15:29 ` Jessica Clarke
2022-09-09 3:42 ` Samuel Holland
2022-09-09 7:10 ` Geert Uytterhoeven
2022-09-21 7:49 ` Geert Uytterhoeven
2022-08-22 10:50 ` Andre Przywara
2022-08-16 7:41 ` Krzysztof Kozlowski
2022-08-16 7:49 ` Jernej Škrabec
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 9:25 ` Jernej Škrabec
2022-08-16 9:42 ` Krzysztof Kozlowski
2022-08-16 11:00 ` Andre Przywara
2022-08-16 11:11 ` Krzysztof Kozlowski
2022-08-16 11:12 ` Krzysztof Kozlowski
2022-08-16 11:34 ` Conor.Dooley
2022-08-22 11:40 ` Geert Uytterhoeven
2022-08-16 9:11 ` Heiko Stübner
2022-08-17 8:29 ` Krzysztof Kozlowski
2022-08-19 22:19 ` Conor.Dooley
2022-08-15 5:08 ` [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Samuel Holland
2022-08-15 17:37 ` Conor.Dooley
2022-08-15 18:34 ` Conor.Dooley
2022-08-16 8:55 ` Heiko Stübner
2022-08-19 22:10 ` Conor.Dooley
2022-08-21 7:06 ` Icenowy Zheng
2022-09-04 20:10 ` Peter Korsgaard
2022-09-09 4:37 ` Samuel Holland
2022-09-09 7:18 ` Conor.Dooley
2022-09-09 8:11 ` Heiko Stübner
2022-09-09 19:04 ` Jessica Clarke
2022-09-03 15:21 ` Peter Korsgaard
2022-08-15 5:08 ` [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Samuel Holland
2022-08-15 7:05 ` [PATCH 00/12] riscv: Allwinner D1 platform support Conor.Dooley
2022-08-15 17:12 ` Conor.Dooley
2022-08-16 2:42 ` Samuel Holland
2022-08-16 6:38 ` Conor.Dooley
2022-09-01 18:10 ` Palmer Dabbelt
2022-09-02 5:42 ` Conor.Dooley
2022-09-06 20:29 ` Jernej Škrabec
2022-09-07 20:43 ` Conor.Dooley
2022-09-08 7:00 ` Geert Uytterhoeven
2022-09-08 9:04 ` Arnd Bergmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=538ae41e-664f-2efb-f941-9a063b727b6a@microchip.com \
--to=conor.dooley@microchip.com \
--cc=andre.przywara@arm.com \
--cc=aou@eecs.berkeley.edu \
--cc=devicetree@vger.kernel.org \
--cc=geert@linux-m68k.org \
--cc=jernej.skrabec@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-sunxi@lists.linux.dev \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
--cc=samuel@sholland.org \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).