From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Samuel Holland <samuel@sholland.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Andre Przywara <andre.przywara@arm.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
devicetree <devicetree@vger.kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree
Date: Wed, 21 Sep 2022 09:49:59 +0200 [thread overview]
Message-ID: <CAMuHMdV1n00JNR7SuUXY5pVHcnG_1PHne95cUdsW+ZHgqvZW=A@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdUMM9H4jLJ8-zOz9SXoqmK-s4zRWzGCsU8jt_sDgY1h+Q@mail.gmail.com>
On Fri, Sep 9, 2022 at 9:10 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Fri, Sep 9, 2022 at 5:42 AM Samuel Holland <samuel@sholland.org> wrote:
> > On 8/22/22 10:29 AM, Jessica Clarke wrote:
> > > On 22 Aug 2022, at 14:56, conor.dooley@microchip.com wrote:
> > >> On 22/08/2022 13:31, Geert Uytterhoeven wrote:
> > >>>> Do you think this is worth doing? Or are you just providing an
> > >>>> example of what could be done?
> > >>>
> > >>> Just some brainstorming...
> > >>>
> > >>>> Where would you envisage putting these macros? I forget the order
> > >>>> of the CPP operations that are done, can they be put in the dts?
> > >>>
> > >>> The SOC_PERIPHERAL_IRQ() macro should be defined in the
> > >>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.
> > >>
> > >> Right, one level up but ~the same result.
> > >>
> > >>>>> Nice! But it's gonna be a very large interrupt-map.
> > >>>>
> > >>>> I quite like the idea of not duplicating files across the archs
> > >>>> if it can be helped, but not at the expense of making them hard to
> > >>>> understand & I feel like unfortunately the large interrupt map is
> > >>>> in that territory.
> > >>>
> > >>> I feel the same.
> > >>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
> > >>> is a risk for making mistakes.
> > >>>
> > >>> So personally, I'm in favor of teaching dtc arithmetic, so we can
> > >>> handle the offset in SOC_PERIPHERAL_IRQ().
> > >>
> > >> Yup, in the same boat here. mayb I'll get bored enough to bite..
> > >
> > > Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a
> > > BSD-licensed implementation[1] and so adding new features like this to
> > > GPL dtc that actually get used would require us to reimplement it too.
> > > I don’t know how much effort it would be but please keep this in mind.
> >
> > I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2. I like
> > that it only affects the DT source, and does not leak into the DTB. We still
> > have the freedom to switch to using arithmetic later when all of the tools
> > support it.
>
> May I suggest an alternative solution, which would be more generic,
> and can be extended to other/more CPU cores easily:
>
> Specify both interrupts in the .dtsi, but wrapped inside e.g. ARM()
> resp. RISCV() macros:
>
> ARM(interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;)
> RISCV(interrupts = <412 IRQ_TYPE_LEVEL_HIGH>;)
>
> The same construct can be used for e.g. interrupt-parent.
> The ARM .dts would define:
>
> #define ARM(x...) x
> #define RISCV(x....)
>
> before including the .dtsi.
> The RISC-V DTS would define instead:
>
> #define ARM(x...)
> #define RISCV(x...) x
>
> Cfr. the AR_CLASS(), M_CLASS(), ARM(), and THUMB() macros in
> arch/arm/include/asm/unified.h.
I brought it up with the DT people in a separate thread[1].
Please continue the discussion there.
Thanks!
[1] https://lore.kernel.org/r/CAMuHMdUPm36RsxHdVwspR3NCAR3C507AyB6R65W42N2gXWq0ag@mail.gmail.com
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2022-09-21 7:50 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 5:08 [PATCH 00/12] riscv: Allwinner D1 platform support Samuel Holland
2022-08-15 5:08 ` [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Samuel Holland
2022-08-15 17:06 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Samuel Holland
2022-08-15 17:07 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-11-04 2:57 ` Icenowy Zheng
2022-11-20 11:23 ` Conor Dooley
2022-11-20 11:25 ` Conor Dooley
2022-08-15 5:08 ` [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors Samuel Holland
2022-08-15 17:12 ` Heiko Stübner
2022-08-16 17:34 ` Rob Herring
2022-08-15 5:08 ` [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles Samuel Holland
2022-08-16 7:39 ` Krzysztof Kozlowski
2022-08-16 9:02 ` Heiko Stübner
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 17:35 ` Rob Herring
2022-08-15 5:08 ` [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option Samuel Holland
2022-08-15 16:56 ` Conor.Dooley
2022-08-16 9:17 ` Heiko Stübner
2022-08-16 9:23 ` Conor.Dooley
2022-08-15 17:13 ` Heiko Stübner
2022-08-15 5:08 ` [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Samuel Holland
2022-08-15 13:11 ` Andre Przywara
2022-08-15 17:01 ` Conor.Dooley
2022-08-20 17:24 ` Samuel Holland
2022-08-20 17:29 ` Conor.Dooley
2022-08-21 6:45 ` Icenowy Zheng
2022-08-21 10:04 ` Conor.Dooley
2022-08-22 11:46 ` Geert Uytterhoeven
2022-08-22 12:13 ` Conor.Dooley
2022-08-22 12:29 ` Andre Przywara
2022-08-22 12:31 ` Geert Uytterhoeven
2022-08-22 13:56 ` Conor.Dooley
2022-08-22 15:29 ` Jessica Clarke
2022-09-09 3:42 ` Samuel Holland
2022-09-09 7:10 ` Geert Uytterhoeven
2022-09-21 7:49 ` Geert Uytterhoeven [this message]
2022-08-22 10:50 ` Andre Przywara
2022-08-16 7:41 ` Krzysztof Kozlowski
2022-08-16 7:49 ` Jernej Škrabec
2022-08-16 9:12 ` Heiko Stübner
2022-08-16 9:25 ` Jernej Škrabec
2022-08-16 9:42 ` Krzysztof Kozlowski
2022-08-16 11:00 ` Andre Przywara
2022-08-16 11:11 ` Krzysztof Kozlowski
2022-08-16 11:12 ` Krzysztof Kozlowski
2022-08-16 11:34 ` Conor.Dooley
2022-08-22 11:40 ` Geert Uytterhoeven
2022-08-16 9:11 ` Heiko Stübner
2022-08-17 8:29 ` Krzysztof Kozlowski
2022-08-19 22:19 ` Conor.Dooley
2022-08-15 5:08 ` [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Samuel Holland
2022-08-15 17:37 ` Conor.Dooley
2022-08-15 18:34 ` Conor.Dooley
2022-08-16 8:55 ` Heiko Stübner
2022-08-19 22:10 ` Conor.Dooley
2022-08-21 7:06 ` Icenowy Zheng
2022-09-04 20:10 ` Peter Korsgaard
2022-09-09 4:37 ` Samuel Holland
2022-09-09 7:18 ` Conor.Dooley
2022-09-09 8:11 ` Heiko Stübner
2022-09-09 19:04 ` Jessica Clarke
2022-09-03 15:21 ` Peter Korsgaard
2022-08-15 5:08 ` [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Samuel Holland
2022-08-15 5:08 ` [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Samuel Holland
2022-08-15 5:08 ` [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Samuel Holland
2022-08-15 7:05 ` [PATCH 00/12] riscv: Allwinner D1 platform support Conor.Dooley
2022-08-15 17:12 ` Conor.Dooley
2022-08-16 2:42 ` Samuel Holland
2022-08-16 6:38 ` Conor.Dooley
2022-09-01 18:10 ` Palmer Dabbelt
2022-09-02 5:42 ` Conor.Dooley
2022-09-06 20:29 ` Jernej Škrabec
2022-09-07 20:43 ` Conor.Dooley
2022-09-08 7:00 ` Geert Uytterhoeven
2022-09-08 9:04 ` Arnd Bergmann
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