[PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support

[PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support

[Hal Feng]

This series adds basic support for the StarFive JH7110 RISC-V SoC to
boot up and get a serial console. This series includes basic clock, 
reset, pinctrl and uart drivers, which are necessary for booting.
It's should be noted that the reset and clock driver codes of JH7110
are partly common with those of JH7100, so the common codes are
factored out and can be reused by drivers of JH7110 and other more
SoCs from StarFive.

The JH7110 is the upgraded version of JH7100 and also the first official
released version of JH71XX series SoCs from StarFive Technology Ltd. 
The VisionFive 2 boards equipped with JH7110 SoCs are launched
recently [1]. More information and support can visit RVspace wiki [2].

This series is also available at 
https://github.com/hal-feng/linux/commits/visionfive2-minimal

[1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
[2] https://wiki.rvspace.org/

Emil Renner Berthing (17):
  dt-bindings: riscv: Add StarFive JH7110 bindings
  dt-bindings: timer: Add StarFive JH7110 clint
  dt-bindings: interrupt-controller: Add StarFive JH7110 plic
  dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
  soc: sifive: l2 cache: Convert to platform driver
  soc: sifive: l2 cache: Add StarFive JH71x0 support
  reset: starfive: jh7100: Use 32bit I/O on 32bit registers
  dt-bindings: reset: Add StarFive JH7110 reset definitions
  clk: starfive: Factor out common clock driver code
  dt-bindings: clock: Add StarFive JH7110 system clock definitions
  dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
  clk: starfive: Add StarFive JH7110 system clock driver
  dt-bindings: clock: Add StarFive JH7110 always-on definitions
  dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
  clk: starfive: Add StarFive JH7110 always-on clock driver
  RISC-V: Add initial StarFive JH7110 device tree
  RISC-V: Add StarFive JH7110 VisionFive2 board device tree

Hal Feng (8):
  reset: starfive: jh7100: Use regmap APIs to operate registers
  reset: starfive: jh7100: Move necessary properties to device tree
  reset: starfive: Rename 'reset-starfive-jh7100.c' to
    'reset-starfive.c'
  dt-bindings: reset: Add starfive,jh7110-reset bindings
  reset: starfive: Add StarFive JH7110 SoC support
  clk: starfive: Use regmap APIs to operate registers
  RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
  RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options

Jianlong Huang (5):
  pinctrl: Create subdirectory for StarFive drivers
  pinctrl: starfive: Rename "pinctrl-starfive" to
    "pinctrl-starfive-jh7100"
  dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
  dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings
  pinctrl: starfive: Add StarFive JH7110 driver

 .../clock/starfive,jh7110-clkgen-aon.yaml     |  62 ++
 .../clock/starfive,jh7110-clkgen-sys.yaml     |  69 ++
 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../pinctrl/starfive,jh7100-pinctrl.yaml      |   2 +-
 .../pinctrl/starfive,jh7110-pinctrl.yaml      | 202 ++++
 .../bindings/reset/starfive,jh7100-reset.yaml |  20 +
 .../bindings/reset/starfive,jh7110-reset.yaml |  54 +
 .../bindings/riscv/sifive-l2-cache.yaml       |   4 +
 .../devicetree/bindings/riscv/starfive.yaml   |   3 +
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |  27 +-
 arch/riscv/Kconfig.socs                       |  28 +-
 arch/riscv/boot/dts/starfive/Makefile         |   3 +-
 .../dts/starfive/jh7100-beaglev-starlight.dts |   2 +-
 arch/riscv/boot/dts/starfive/jh7100.dtsi      |   3 +
 .../jh7110-starfive-visionfive-v2.dts         |  91 ++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 449 +++++++++
 arch/riscv/configs/defconfig                  |   1 +
 drivers/clk/starfive/Kconfig                  |  29 +-
 drivers/clk/starfive/Makefile                 |   6 +-
 .../clk/starfive/clk-starfive-jh7100-audio.c  | 138 +--
 drivers/clk/starfive/clk-starfive-jh7100.c    | 836 +++++-----------
 drivers/clk/starfive/clk-starfive-jh7100.h    | 112 ---
 .../clk/starfive/clk-starfive-jh7110-aon.c    | 161 +++
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 648 ++++++++++++
 drivers/clk/starfive/clk-starfive.c           | 349 +++++++
 drivers/clk/starfive/clk-starfive.h           | 112 +++
 drivers/pinctrl/Kconfig                       |  18 +-
 drivers/pinctrl/Makefile                      |   2 +-
 drivers/pinctrl/starfive/Kconfig              |  37 +
 drivers/pinctrl/starfive/Makefile             |   8 +
 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 718 ++++++++++++++
 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 925 +++++++++++++++++
 .../pinctrl-starfive-jh7100.c}                |  10 +-
 drivers/pinctrl/starfive/pinctrl-starfive.c   | 539 ++++++++++
 drivers/pinctrl/starfive/pinctrl-starfive.h   | 131 +++
 drivers/reset/Kconfig                         |   7 +-
 drivers/reset/Makefile                        |   2 +-
 drivers/reset/reset-starfive-jh7100.c         | 173 ----
 drivers/reset/reset-starfive.c                | 218 ++++
 drivers/soc/Makefile                          |   2 +-
 drivers/soc/sifive/Kconfig                    |   2 +-
 drivers/soc/sifive/sifive_l2_cache.c          |  86 +-
 .../dt-bindings/clock/starfive-jh7110-aon.h   |  26 +
 .../dt-bindings/clock/starfive-jh7110-sys.h   | 215 ++++
 ...l-starfive.h => pinctrl-starfive-jh7100.h} |   6 +-
 .../pinctrl/pinctrl-starfive-jh7110.h         | 931 ++++++++++++++++++
 include/dt-bindings/reset/starfive-jh7110.h   | 154 +++
 48 files changed, 6604 insertions(+), 1019 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
 delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
 create mode 100644 drivers/clk/starfive/clk-starfive.c
 create mode 100644 drivers/clk/starfive/clk-starfive.h
 create mode 100644 drivers/pinctrl/starfive/Kconfig
 create mode 100644 drivers/pinctrl/starfive/Makefile
 create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
 rename drivers/pinctrl/{pinctrl-starfive.c => starfive/pinctrl-starfive-jh7100.c} (99%)
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
 delete mode 100644 drivers/reset/reset-starfive-jh7100.c
 create mode 100644 drivers/reset/reset-starfive.c
 create mode 100644 include/dt-bindings/clock/starfive-jh7110-aon.h
 create mode 100644 include/dt-bindings/clock/starfive-jh7110-sys.h
 rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
 create mode 100644 include/dt-bindings/reset/starfive-jh7110.h

-- 
2.17.1

[PATCH v1 01/30] dt-bindings: riscv: Add StarFive JH7110 bindings

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add device tree bindings for the StarFive JH7110 RISC-V SoC and the
VisionFive2 board for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 5b36243fd674..543be573921d 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -21,6 +21,9 @@ properties:
       - items:
           - const: beagle,beaglev-starlight-jh7100-r0
           - const: starfive,jh7100
+      - items:
+          - const: starfive,visionfive-v2
+          - const: starfive,jh7110
 
 additionalProperties: true
 
-- 
2.17.1

Re: [PATCH v1 01/30] dt-bindings: riscv: Add StarFive JH7110 bindings

[Krzysztof Kozlowski]

On 29/09/2022 16:31, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>

Drop last "bindings" from subject, it's redundant.

> 
> Add device tree bindings for the StarFive JH7110 RISC-V SoC and the
> VisionFive2 board for it.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  Documentation/devicetree/bindings/riscv/starfive.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 5b36243fd674..543be573921d 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -21,6 +21,9 @@ properties:
>        - items:
>            - const: beagle,beaglev-starlight-jh7100-r0
>            - const: starfive,jh7100

Blank line.

> +      - items:
> +          - const: starfive,visionfive-v2
> +          - const: starfive,jh7110
>  
>  additionalProperties: true
>  

Best regards,
Krzysztof

Re: [PATCH v1 01/30] dt-bindings: riscv: Add StarFive JH7110 bindings

[Hal Feng]

On Thu, 29 Sep 2022 16:34:22 +0200, Krzysztof Kozlowski wrote:
> On 29/09/2022 16:31, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Drop last "bindings" from subject, it's redundant.

Will fix. Thanks.

> 
> > 
> > Add device tree bindings for the StarFive JH7110 RISC-V SoC and the
> > VisionFive2 board for it.
> > 
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/starfive.yaml | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > index 5b36243fd674..543be573921d 100644
> > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > @@ -21,6 +21,9 @@ properties:
> >        - items:
> >            - const: beagle,beaglev-starlight-jh7100-r0
> >            - const: starfive,jh7100
> 
> Blank line.

Will fix. Thanks.

Best Regards,
Hal

[PATCH v1 02/30] dt-bindings: timer: Add StarFive JH7110 clint

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add compatible string for the StarFive JH7110 clint.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index e64f46339079..f85e4982ad05 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -26,6 +26,7 @@ properties:
       - enum:
           - sifive,fu540-c000-clint
           - starfive,jh7100-clint
+          - starfive,jh7110-clint
           - canaan,k210-clint
       - const: sifive,clint0
 
-- 
2.17.1

Re: [PATCH v1 02/30] dt-bindings: timer: Add StarFive JH7110 clint

[Krzysztof Kozlowski]

On 29/09/2022 16:31, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add compatible string for the StarFive JH7110 clint.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v1 03/30] dt-bindings: interrupt-controller: Add StarFive JH7110 plic

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add compatible string for StarFive JH7110 plic.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 92e0f8c3eff2..cef0451c3a47 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -60,6 +60,7 @@ properties:
           - enum:
               - sifive,fu540-c000-plic
               - starfive,jh7100-plic
+              - starfive,jh7110-plic
               - canaan,k210-plic
           - const: sifive,plic-1.0.0
       - items:
-- 
2.17.1

Re: [PATCH v1 03/30] dt-bindings: interrupt-controller: Add StarFive JH7110 plic

[Krzysztof Kozlowski]

On 29/09/2022 16:31, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add compatible string for StarFive JH7110 plic.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

This cache controller is also used on the StarFive JH7100 and JH7110
SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index ca3b9be58058..ba29ecfd3a92 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -24,6 +24,8 @@ select:
         enum:
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - starfive,jh7100-ccache
+          - starfive,jh7110-ccache
 
   required:
     - compatible
@@ -35,6 +37,8 @@ properties:
           - enum:
               - sifive,fu540-c000-ccache
               - sifive,fu740-c000-ccache
+              - starfive,jh7100-ccache
+              - starfive,jh7110-ccache
           - const: cache
       - items:
           - const: microchip,mpfs-ccache
-- 
2.17.1

Re: [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs

[Krzysztof Kozlowski]

On 29/09/2022 16:31, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> This cache controller is also used on the StarFive JH7100 and JH7110
> SoCs.


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs

[Conor Dooley]

On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> This cache controller is also used on the StarFive JH7100 and JH7110
> SoCs.

Ditto this patch, hopefully [0] will have landed as 6.1 material
before you get around to an actual v2.

Thanks,
Conor

0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/

> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index ca3b9be58058..ba29ecfd3a92 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -24,6 +24,8 @@ select:
>          enum:
>            - sifive,fu540-c000-ccache
>            - sifive,fu740-c000-ccache
> +          - starfive,jh7100-ccache
> +          - starfive,jh7110-ccache
>  
>    required:
>      - compatible
> @@ -35,6 +37,8 @@ properties:
>            - enum:
>                - sifive,fu540-c000-ccache
>                - sifive,fu740-c000-ccache
> +              - starfive,jh7100-ccache
> +              - starfive,jh7110-ccache
>            - const: cache
>        - items:
>            - const: microchip,mpfs-ccache
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs

[Ben Dooks]

On 29/09/2022 16:33, Conor Dooley wrote:
> On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> This cache controller is also used on the StarFive JH7100 and JH7110
>> SoCs.
> 
> Ditto this patch, hopefully [0] will have landed as 6.1 material
> before you get around to an actual v2.
> 
> Thanks,
> Conor
> 
> 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/

Also, the l2 cache is being proprely named the ccache (composable cache)
as it is not necessarily an L2 cache.

-- 
Ben

Re: [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs

[Hal Feng]

On Mon, 3 Oct 2022 10:26:44 +0100, Ben Dooks wrote:
> On 29/09/2022 16:33, Conor Dooley wrote:
> > On Thu, Sep 29, 2022 at 10:31:59PM +0800, Hal Feng wrote:
> >> From: Emil Renner Berthing <kernel@esmil.dk>
> >>
> >> This cache controller is also used on the StarFive JH7100 and JH7110
> >> SoCs.
> >
> > Ditto this patch, hopefully [0] will have landed as 6.1 material
> > before you get around to an actual v2.
> >
> > Thanks,
> > Conor
> >
> > 0 - https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/
> 
> Also, the l2 cache is being proprely named the ccache (composable cache)
> as it is not necessarily an L2 cache.
> 

Thanks for reminding. I will modify the code, based on the patches from Zong Li.
I hope his patch series will be merged as soon as possible.

Best regards,
Hal

[PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

This converts the driver to use the builtin_platform_driver_probe macro
to initialize the driver. This macro ends up calling device_initcall as
was used previously, but also allocates a platform device which gives us
access to much nicer APIs such as platform_ioremap_resource,
platform_get_irq and dev_err_probe.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
 1 file changed, 40 insertions(+), 39 deletions(-)

diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 59640a1d0b28..010d612f7420 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -7,9 +7,9 @@
  */
 #include <linux/debugfs.h>
 #include <linux/interrupt.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
 #include <asm/cacheinfo.h>
 #include <soc/sifive/sifive_l2_cache.h>
 
@@ -96,12 +96,6 @@ static void l2_config_read(void)
 	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
 }
 
-static const struct of_device_id sifive_l2_ids[] = {
-	{ .compatible = "sifive,fu540-c000-ccache" },
-	{ .compatible = "sifive,fu740-c000-ccache" },
-	{ /* end of table */ },
-};
-
 static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
 
 int register_sifive_l2_error_notifier(struct notifier_block *nb)
@@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
 	return IRQ_HANDLED;
 }
 
-static int __init sifive_l2_init(void)
+static int __init sifive_l2_probe(struct platform_device *pdev)
 {
-	struct device_node *np;
-	struct resource res;
-	int i, rc, intr_num;
-
-	np = of_find_matching_node(NULL, sifive_l2_ids);
-	if (!np)
-		return -ENODEV;
-
-	if (of_address_to_resource(np, 0, &res))
-		return -ENODEV;
-
-	l2_base = ioremap(res.start, resource_size(&res));
-	if (!l2_base)
-		return -ENOMEM;
-
-	intr_num = of_property_count_u32_elems(np, "interrupts");
-	if (!intr_num) {
-		pr_err("L2CACHE: no interrupts property\n");
-		return -ENODEV;
-	}
-
-	for (i = 0; i < intr_num; i++) {
-		g_irq[i] = irq_of_parse_and_map(np, i);
-		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
-		if (rc) {
-			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
-			return rc;
-		}
+	struct device *dev = &pdev->dev;
+	int nirqs;
+	int ret;
+	int i;
+
+	l2_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(l2_base))
+		return PTR_ERR(l2_base);
+
+	nirqs = platform_irq_count(pdev);
+	if (nirqs <= 0)
+		return dev_err_probe(dev, -ENODEV, "no interrupts\n");
+
+	for (i = 0; i < nirqs; i++) {
+		g_irq[i] = platform_get_irq(pdev, i);
+		if (g_irq[i] < 0)
+			return g_irq[i];
+
+		ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
+		if (ret)
+			return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
 	}
 
 	l2_config_read();
@@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
 #endif
 	return 0;
 }
-device_initcall(sifive_l2_init);
+
+static const struct of_device_id sifive_l2_match[] = {
+	{ .compatible = "sifive,fu540-c000-ccache" },
+	{ .compatible = "sifive,fu740-c000-ccache" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver sifive_l2_driver = {
+	.driver = {
+		.name = "sifive_l2_cache",
+		.of_match_table = sifive_l2_match,
+		.suppress_bind_attrs = true,
+	},
+};
+builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
-- 
2.17.1

Re: [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Conor Dooley]

On Thu, Sep 29, 2022 at 10:32:00PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> This converts the driver to use the builtin_platform_driver_probe macro
> to initialize the driver. This macro ends up calling device_initcall as
> was used previously, but also allocates a platform device which gives us
> access to much nicer APIs such as platform_ioremap_resource,
> platform_get_irq and dev_err_probe.

You should resend the series ignoring this comment, but for v2, I think
you should pay attention to following patchset:

https://lore.kernel.org/linux-riscv/20220913061817.22564-1-zong.li@sifive.com/

Hopefully by the time you get to a v2, that patchset will have been
applied as 6.1 material..

Thanks,
Conor.

> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
>  1 file changed, 40 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> index 59640a1d0b28..010d612f7420 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> @@ -7,9 +7,9 @@
>   */
>  #include <linux/debugfs.h>
>  #include <linux/interrupt.h>
> -#include <linux/of_irq.h>
> -#include <linux/of_address.h>
> -#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
>  #include <asm/cacheinfo.h>
>  #include <soc/sifive/sifive_l2_cache.h>
>  
> @@ -96,12 +96,6 @@ static void l2_config_read(void)
>  	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
>  }
>  
> -static const struct of_device_id sifive_l2_ids[] = {
> -	{ .compatible = "sifive,fu540-c000-ccache" },
> -	{ .compatible = "sifive,fu740-c000-ccache" },
> -	{ /* end of table */ },
> -};
> -
>  static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
>  
>  int register_sifive_l2_error_notifier(struct notifier_block *nb)
> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
>  	return IRQ_HANDLED;
>  }
>  
> -static int __init sifive_l2_init(void)
> +static int __init sifive_l2_probe(struct platform_device *pdev)
>  {
> -	struct device_node *np;
> -	struct resource res;
> -	int i, rc, intr_num;
> -
> -	np = of_find_matching_node(NULL, sifive_l2_ids);
> -	if (!np)
> -		return -ENODEV;
> -
> -	if (of_address_to_resource(np, 0, &res))
> -		return -ENODEV;
> -
> -	l2_base = ioremap(res.start, resource_size(&res));
> -	if (!l2_base)
> -		return -ENOMEM;
> -
> -	intr_num = of_property_count_u32_elems(np, "interrupts");
> -	if (!intr_num) {
> -		pr_err("L2CACHE: no interrupts property\n");
> -		return -ENODEV;
> -	}
> -
> -	for (i = 0; i < intr_num; i++) {
> -		g_irq[i] = irq_of_parse_and_map(np, i);
> -		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> -		if (rc) {
> -			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> -			return rc;
> -		}
> +	struct device *dev = &pdev->dev;
> +	int nirqs;
> +	int ret;
> +	int i;
> +
> +	l2_base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(l2_base))
> +		return PTR_ERR(l2_base);
> +
> +	nirqs = platform_irq_count(pdev);
> +	if (nirqs <= 0)
> +		return dev_err_probe(dev, -ENODEV, "no interrupts\n");
> +
> +	for (i = 0; i < nirqs; i++) {
> +		g_irq[i] = platform_get_irq(pdev, i);
> +		if (g_irq[i] < 0)
> +			return g_irq[i];
> +
> +		ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> +		if (ret)
> +			return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
>  	}
>  
>  	l2_config_read();
> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
>  #endif
>  	return 0;
>  }
> -device_initcall(sifive_l2_init);
> +
> +static const struct of_device_id sifive_l2_match[] = {
> +	{ .compatible = "sifive,fu540-c000-ccache" },
> +	{ .compatible = "sifive,fu740-c000-ccache" },
> +	{ /* sentinel */ }
> +};
> +
> +static struct platform_driver sifive_l2_driver = {
> +	.driver = {
> +		.name = "sifive_l2_cache",
> +		.of_match_table = sifive_l2_match,
> +		.suppress_bind_attrs = true,
> +	},
> +};
> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Ben Dooks]

On 29/09/2022 15:32, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> This converts the driver to use the builtin_platform_driver_probe macro
> to initialize the driver. This macro ends up calling device_initcall as
> was used previously, but also allocates a platform device which gives us
> access to much nicer APIs such as platform_ioremap_resource,
> platform_get_irq and dev_err_probe.

This is useful, but also there are other changes currently being sorted
out by Zong Li (cc'd into this message) which have already been reviewed
and are hopefully queued for the next kernel release.

> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>   drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
>   1 file changed, 40 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> index 59640a1d0b28..010d612f7420 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> @@ -7,9 +7,9 @@
>    */
>   #include <linux/debugfs.h>
>   #include <linux/interrupt.h>
> -#include <linux/of_irq.h>
> -#include <linux/of_address.h>
> -#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
>   #include <asm/cacheinfo.h>
>   #include <soc/sifive/sifive_l2_cache.h>
>   
> @@ -96,12 +96,6 @@ static void l2_config_read(void)
>   	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
>   }
>   
> -static const struct of_device_id sifive_l2_ids[] = {
> -	{ .compatible = "sifive,fu540-c000-ccache" },
> -	{ .compatible = "sifive,fu740-c000-ccache" },
> -	{ /* end of table */ },
> -};
> -
>   static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
>   
>   int register_sifive_l2_error_notifier(struct notifier_block *nb)
> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
>   	return IRQ_HANDLED;
>   }
>   
> -static int __init sifive_l2_init(void)
> +static int __init sifive_l2_probe(struct platform_device *pdev)
>   {
> -	struct device_node *np;
> -	struct resource res;
> -	int i, rc, intr_num;
> -
> -	np = of_find_matching_node(NULL, sifive_l2_ids);
> -	if (!np)
> -		return -ENODEV;
> -
> -	if (of_address_to_resource(np, 0, &res))
> -		return -ENODEV;
> -
> -	l2_base = ioremap(res.start, resource_size(&res));
> -	if (!l2_base)
> -		return -ENOMEM;
> -
> -	intr_num = of_property_count_u32_elems(np, "interrupts");
> -	if (!intr_num) {
> -		pr_err("L2CACHE: no interrupts property\n");
> -		return -ENODEV;
> -	}
> -
> -	for (i = 0; i < intr_num; i++) {
> -		g_irq[i] = irq_of_parse_and_map(np, i);
> -		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> -		if (rc) {
> -			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> -			return rc;
> -		}
> +	struct device *dev = &pdev->dev;
> +	int nirqs;
> +	int ret;
> +	int i;
> +
> +	l2_base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(l2_base))
> +		return PTR_ERR(l2_base);
> +
> +	nirqs = platform_irq_count(pdev);
> +	if (nirqs <= 0)
> +		return dev_err_probe(dev, -ENODEV, "no interrupts\n");

I wonder if zero irqs is an actual issue here?

> +	for (i = 0; i < nirqs; i++) {
> +		g_irq[i] = platform_get_irq(pdev, i);

I wonder if we need to keep g_irq[] around now? Is it going to be useful 
in the future?

> +		if (g_irq[i] < 0)
> +			return g_irq[i];
> +
> +		ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> +		if (ret)
> +			return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
>   	}
>   
>   	l2_config_read();
> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
>   #endif
>   	return 0;
>   }
> -device_initcall(sifive_l2_init);
> +
> +static const struct of_device_id sifive_l2_match[] = {
> +	{ .compatible = "sifive,fu540-c000-ccache" },
> +	{ .compatible = "sifive,fu740-c000-ccache" },
> +	{ /* sentinel */ }
> +};
> +
> +static struct platform_driver sifive_l2_driver = {
> +	.driver = {
> +		.name = "sifive_l2_cache",
> +		.of_match_table = sifive_l2_match,
> +		.suppress_bind_attrs = true,
> +	},
> +};
> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);

Re: [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Emil Renner Berthing]

On Thu, 29 Sept 2022 at 19:59, Ben Dooks <ben.dooks@sifive.com> wrote:
>
> On 29/09/2022 15:32, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > This converts the driver to use the builtin_platform_driver_probe macro
> > to initialize the driver. This macro ends up calling device_initcall as
> > was used previously, but also allocates a platform device which gives us
> > access to much nicer APIs such as platform_ioremap_resource,
> > platform_get_irq and dev_err_probe.
>
> This is useful, but also there are other changes currently being sorted
> out by Zong Li (cc'd into this message) which have already been reviewed
> and are hopefully queued for the next kernel release.
>
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>

I'm ok with something like this being merged, but please note that if
we ever want to support the JH7100 which uses registers in this
peripheral to flush the cache for its non-coherent DMAs then this
driver needs to be loaded before other peripherals or we will trigger
the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
can do that when it's a platform driver. See this patch for an
alternative to support the JH71x0s:
https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5

/Emil

> >   drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> >   1 file changed, 40 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> > index 59640a1d0b28..010d612f7420 100644
> > --- a/drivers/soc/sifive/sifive_l2_cache.c
> > +++ b/drivers/soc/sifive/sifive_l2_cache.c
> > @@ -7,9 +7,9 @@
> >    */
> >   #include <linux/debugfs.h>
> >   #include <linux/interrupt.h>
> > -#include <linux/of_irq.h>
> > -#include <linux/of_address.h>
> > -#include <linux/device.h>
> > +#include <linux/io.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/platform_device.h>
> >   #include <asm/cacheinfo.h>
> >   #include <soc/sifive/sifive_l2_cache.h>
> >
> > @@ -96,12 +96,6 @@ static void l2_config_read(void)
> >       pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> >   }
> >
> > -static const struct of_device_id sifive_l2_ids[] = {
> > -     { .compatible = "sifive,fu540-c000-ccache" },
> > -     { .compatible = "sifive,fu740-c000-ccache" },
> > -     { /* end of table */ },
> > -};
> > -
> >   static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> >
> >   int register_sifive_l2_error_notifier(struct notifier_block *nb)
> > @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> >       return IRQ_HANDLED;
> >   }
> >
> > -static int __init sifive_l2_init(void)
> > +static int __init sifive_l2_probe(struct platform_device *pdev)
> >   {
> > -     struct device_node *np;
> > -     struct resource res;
> > -     int i, rc, intr_num;
> > -
> > -     np = of_find_matching_node(NULL, sifive_l2_ids);
> > -     if (!np)
> > -             return -ENODEV;
> > -
> > -     if (of_address_to_resource(np, 0, &res))
> > -             return -ENODEV;
> > -
> > -     l2_base = ioremap(res.start, resource_size(&res));
> > -     if (!l2_base)
> > -             return -ENOMEM;
> > -
> > -     intr_num = of_property_count_u32_elems(np, "interrupts");
> > -     if (!intr_num) {
> > -             pr_err("L2CACHE: no interrupts property\n");
> > -             return -ENODEV;
> > -     }
> > -
> > -     for (i = 0; i < intr_num; i++) {
> > -             g_irq[i] = irq_of_parse_and_map(np, i);
> > -             rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> > -             if (rc) {
> > -                     pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> > -                     return rc;
> > -             }
> > +     struct device *dev = &pdev->dev;
> > +     int nirqs;
> > +     int ret;
> > +     int i;
> > +
> > +     l2_base = devm_platform_ioremap_resource(pdev, 0);
> > +     if (IS_ERR(l2_base))
> > +             return PTR_ERR(l2_base);
> > +
> > +     nirqs = platform_irq_count(pdev);
> > +     if (nirqs <= 0)
> > +             return dev_err_probe(dev, -ENODEV, "no interrupts\n");
>
> I wonder if zero irqs is an actual issue here?
>
> > +     for (i = 0; i < nirqs; i++) {
> > +             g_irq[i] = platform_get_irq(pdev, i);
>
> I wonder if we need to keep g_irq[] around now? Is it going to be useful
> in the future?
>
> > +             if (g_irq[i] < 0)
> > +                     return g_irq[i];
> > +
> > +             ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> > +             if (ret)
> > +                     return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> >       }
> >
> >       l2_config_read();
> > @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> >   #endif
> >       return 0;
> >   }
> > -device_initcall(sifive_l2_init);
> > +
> > +static const struct of_device_id sifive_l2_match[] = {
> > +     { .compatible = "sifive,fu540-c000-ccache" },
> > +     { .compatible = "sifive,fu740-c000-ccache" },
> > +     { /* sentinel */ }
> > +};
> > +
> > +static struct platform_driver sifive_l2_driver = {
> > +     .driver = {
> > +             .name = "sifive_l2_cache",
> > +             .of_match_table = sifive_l2_match,
> > +             .suppress_bind_attrs = true,
> > +     },
> > +};
> > +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Ben Dooks]

On 05/10/2022 14:44, Emil Renner Berthing wrote:
> On Thu, 29 Sept 2022 at 19:59, Ben Dooks <ben.dooks@sifive.com> wrote:
>>
>> On 29/09/2022 15:32, Hal Feng wrote:
>>> From: Emil Renner Berthing <kernel@esmil.dk>
>>>
>>> This converts the driver to use the builtin_platform_driver_probe macro
>>> to initialize the driver. This macro ends up calling device_initcall as
>>> was used previously, but also allocates a platform device which gives us
>>> access to much nicer APIs such as platform_ioremap_resource,
>>> platform_get_irq and dev_err_probe.
>>
>> This is useful, but also there are other changes currently being sorted
>> out by Zong Li (cc'd into this message) which have already been reviewed
>> and are hopefully queued for the next kernel release.
>>
>>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>>> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> 
> I'm ok with something like this being merged, but please note that if
> we ever want to support the JH7100 which uses registers in this
> peripheral to flush the cache for its non-coherent DMAs then this
> driver needs to be loaded before other peripherals or we will trigger
> the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> can do that when it's a platform driver. See this patch for an
> alternative to support the JH71x0s:
> https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
> 
> /Emil

Are you replying to your own patch that does the conversion to
platform driver and then saying that it could actually cause
issues?

I'm all for dropping this for the moment and keeping the old
early init for the ccache.


>>>    drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
>>>    1 file changed, 40 insertions(+), 39 deletions(-)
>>>
>>> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
>>> index 59640a1d0b28..010d612f7420 100644
>>> --- a/drivers/soc/sifive/sifive_l2_cache.c
>>> +++ b/drivers/soc/sifive/sifive_l2_cache.c
>>> @@ -7,9 +7,9 @@
>>>     */
>>>    #include <linux/debugfs.h>
>>>    #include <linux/interrupt.h>
>>> -#include <linux/of_irq.h>
>>> -#include <linux/of_address.h>
>>> -#include <linux/device.h>
>>> +#include <linux/io.h>
>>> +#include <linux/mod_devicetable.h>
>>> +#include <linux/platform_device.h>
>>>    #include <asm/cacheinfo.h>
>>>    #include <soc/sifive/sifive_l2_cache.h>
>>>
>>> @@ -96,12 +96,6 @@ static void l2_config_read(void)
>>>        pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
>>>    }
>>>
>>> -static const struct of_device_id sifive_l2_ids[] = {
>>> -     { .compatible = "sifive,fu540-c000-ccache" },
>>> -     { .compatible = "sifive,fu740-c000-ccache" },
>>> -     { /* end of table */ },
>>> -};
>>> -
>>>    static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
>>>
>>>    int register_sifive_l2_error_notifier(struct notifier_block *nb)
>>> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
>>>        return IRQ_HANDLED;
>>>    }
>>>
>>> -static int __init sifive_l2_init(void)
>>> +static int __init sifive_l2_probe(struct platform_device *pdev)
>>>    {
>>> -     struct device_node *np;
>>> -     struct resource res;
>>> -     int i, rc, intr_num;
>>> -
>>> -     np = of_find_matching_node(NULL, sifive_l2_ids);
>>> -     if (!np)
>>> -             return -ENODEV;
>>> -
>>> -     if (of_address_to_resource(np, 0, &res))
>>> -             return -ENODEV;
>>> -
>>> -     l2_base = ioremap(res.start, resource_size(&res));
>>> -     if (!l2_base)
>>> -             return -ENOMEM;
>>> -
>>> -     intr_num = of_property_count_u32_elems(np, "interrupts");
>>> -     if (!intr_num) {
>>> -             pr_err("L2CACHE: no interrupts property\n");
>>> -             return -ENODEV;
>>> -     }
>>> -
>>> -     for (i = 0; i < intr_num; i++) {
>>> -             g_irq[i] = irq_of_parse_and_map(np, i);
>>> -             rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
>>> -             if (rc) {
>>> -                     pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
>>> -                     return rc;
>>> -             }
>>> +     struct device *dev = &pdev->dev;
>>> +     int nirqs;
>>> +     int ret;
>>> +     int i;
>>> +
>>> +     l2_base = devm_platform_ioremap_resource(pdev, 0);
>>> +     if (IS_ERR(l2_base))
>>> +             return PTR_ERR(l2_base);
>>> +
>>> +     nirqs = platform_irq_count(pdev);
>>> +     if (nirqs <= 0)
>>> +             return dev_err_probe(dev, -ENODEV, "no interrupts\n");
>>
>> I wonder if zero irqs is an actual issue here?
>>
>>> +     for (i = 0; i < nirqs; i++) {
>>> +             g_irq[i] = platform_get_irq(pdev, i);
>>
>> I wonder if we need to keep g_irq[] around now? Is it going to be useful
>> in the future?
>>
>>> +             if (g_irq[i] < 0)
>>> +                     return g_irq[i];
>>> +
>>> +             ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
>>> +             if (ret)
>>> +                     return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
>>>        }
>>>
>>>        l2_config_read();
>>> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
>>>    #endif
>>>        return 0;
>>>    }
>>> -device_initcall(sifive_l2_init);
>>> +
>>> +static const struct of_device_id sifive_l2_match[] = {
>>> +     { .compatible = "sifive,fu540-c000-ccache" },
>>> +     { .compatible = "sifive,fu740-c000-ccache" },
>>> +     { /* sentinel */ }
>>> +};
>>> +
>>> +static struct platform_driver sifive_l2_driver = {
>>> +     .driver = {
>>> +             .name = "sifive_l2_cache",
>>> +             .of_match_table = sifive_l2_match,
>>> +             .suppress_bind_attrs = true,
>>> +     },
>>> +};
>>> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Emil Renner Berthing]

On Wed, 5 Oct 2022 at 15:48, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> On 05/10/2022 14:44, Emil Renner Berthing wrote:
> > On Thu, 29 Sept 2022 at 19:59, Ben Dooks <ben.dooks@sifive.com> wrote:
> >>
> >> On 29/09/2022 15:32, Hal Feng wrote:
> >>> From: Emil Renner Berthing <kernel@esmil.dk>
> >>>
> >>> This converts the driver to use the builtin_platform_driver_probe macro
> >>> to initialize the driver. This macro ends up calling device_initcall as
> >>> was used previously, but also allocates a platform device which gives us
> >>> access to much nicer APIs such as platform_ioremap_resource,
> >>> platform_get_irq and dev_err_probe.
> >>
> >> This is useful, but also there are other changes currently being sorted
> >> out by Zong Li (cc'd into this message) which have already been reviewed
> >> and are hopefully queued for the next kernel release.
> >>
> >>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> >>> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> >
> > I'm ok with something like this being merged, but please note that if
> > we ever want to support the JH7100 which uses registers in this
> > peripheral to flush the cache for its non-coherent DMAs then this
> > driver needs to be loaded before other peripherals or we will trigger
> > the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> > can do that when it's a platform driver. See this patch for an
> > alternative to support the JH71x0s:
> > https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
> >
> > /Emil
>
> Are you replying to your own patch that does the conversion to
> platform driver and then saying that it could actually cause
> issues?

Yes, I can see it seems odd, but this patch lived for a while in the
kernel repo for the JH7100 until I rebased on 6.0-rc1 and realized the
above.
Hal Feng must have based his patches on a version of the code before
that when preparing this series.

> I'm all for dropping this for the moment and keeping the old
> early init for the ccache.

Cool.

/Emil

> >>>    drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> >>>    1 file changed, 40 insertions(+), 39 deletions(-)
> >>>
> >>> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> >>> index 59640a1d0b28..010d612f7420 100644
> >>> --- a/drivers/soc/sifive/sifive_l2_cache.c
> >>> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> >>> @@ -7,9 +7,9 @@
> >>>     */
> >>>    #include <linux/debugfs.h>
> >>>    #include <linux/interrupt.h>
> >>> -#include <linux/of_irq.h>
> >>> -#include <linux/of_address.h>
> >>> -#include <linux/device.h>
> >>> +#include <linux/io.h>
> >>> +#include <linux/mod_devicetable.h>
> >>> +#include <linux/platform_device.h>
> >>>    #include <asm/cacheinfo.h>
> >>>    #include <soc/sifive/sifive_l2_cache.h>
> >>>
> >>> @@ -96,12 +96,6 @@ static void l2_config_read(void)
> >>>        pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> >>>    }
> >>>
> >>> -static const struct of_device_id sifive_l2_ids[] = {
> >>> -     { .compatible = "sifive,fu540-c000-ccache" },
> >>> -     { .compatible = "sifive,fu740-c000-ccache" },
> >>> -     { /* end of table */ },
> >>> -};
> >>> -
> >>>    static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> >>>
> >>>    int register_sifive_l2_error_notifier(struct notifier_block *nb)
> >>> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> >>>        return IRQ_HANDLED;
> >>>    }
> >>>
> >>> -static int __init sifive_l2_init(void)
> >>> +static int __init sifive_l2_probe(struct platform_device *pdev)
> >>>    {
> >>> -     struct device_node *np;
> >>> -     struct resource res;
> >>> -     int i, rc, intr_num;
> >>> -
> >>> -     np = of_find_matching_node(NULL, sifive_l2_ids);
> >>> -     if (!np)
> >>> -             return -ENODEV;
> >>> -
> >>> -     if (of_address_to_resource(np, 0, &res))
> >>> -             return -ENODEV;
> >>> -
> >>> -     l2_base = ioremap(res.start, resource_size(&res));
> >>> -     if (!l2_base)
> >>> -             return -ENOMEM;
> >>> -
> >>> -     intr_num = of_property_count_u32_elems(np, "interrupts");
> >>> -     if (!intr_num) {
> >>> -             pr_err("L2CACHE: no interrupts property\n");
> >>> -             return -ENODEV;
> >>> -     }
> >>> -
> >>> -     for (i = 0; i < intr_num; i++) {
> >>> -             g_irq[i] = irq_of_parse_and_map(np, i);
> >>> -             rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> >>> -             if (rc) {
> >>> -                     pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> >>> -                     return rc;
> >>> -             }
> >>> +     struct device *dev = &pdev->dev;
> >>> +     int nirqs;
> >>> +     int ret;
> >>> +     int i;
> >>> +
> >>> +     l2_base = devm_platform_ioremap_resource(pdev, 0);
> >>> +     if (IS_ERR(l2_base))
> >>> +             return PTR_ERR(l2_base);
> >>> +
> >>> +     nirqs = platform_irq_count(pdev);
> >>> +     if (nirqs <= 0)
> >>> +             return dev_err_probe(dev, -ENODEV, "no interrupts\n");
> >>
> >> I wonder if zero irqs is an actual issue here?
> >>
> >>> +     for (i = 0; i < nirqs; i++) {
> >>> +             g_irq[i] = platform_get_irq(pdev, i);
> >>
> >> I wonder if we need to keep g_irq[] around now? Is it going to be useful
> >> in the future?
> >>
> >>> +             if (g_irq[i] < 0)
> >>> +                     return g_irq[i];
> >>> +
> >>> +             ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> >>> +             if (ret)
> >>> +                     return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> >>>        }
> >>>
> >>>        l2_config_read();
> >>> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> >>>    #endif
> >>>        return 0;
> >>>    }
> >>> -device_initcall(sifive_l2_init);
> >>> +
> >>> +static const struct of_device_id sifive_l2_match[] = {
> >>> +     { .compatible = "sifive,fu540-c000-ccache" },
> >>> +     { .compatible = "sifive,fu740-c000-ccache" },
> >>> +     { /* sentinel */ }
> >>> +};
> >>> +
> >>> +static struct platform_driver sifive_l2_driver = {
> >>> +     .driver = {
> >>> +             .name = "sifive_l2_cache",
> >>> +             .of_match_table = sifive_l2_match,
> >>> +             .suppress_bind_attrs = true,
> >>> +     },
> >>> +};
> >>> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
>
> --
> Ben Dooks                               http://www.codethink.co.uk/
> Senior Engineer                         Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>

Re: [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Conor Dooley]

On Wed, Oct 05, 2022 at 03:55:17PM +0200, Emil Renner Berthing wrote:
> On Wed, 5 Oct 2022 at 15:48, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> >
> > On 05/10/2022 14:44, Emil Renner Berthing wrote:
> > > On Thu, 29 Sept 2022 at 19:59, Ben Dooks <ben.dooks@sifive.com> wrote:
> > >>
> > >> On 29/09/2022 15:32, Hal Feng wrote:
> > >>> From: Emil Renner Berthing <kernel@esmil.dk>
> > >>>
> > >>> This converts the driver to use the builtin_platform_driver_probe macro
> > >>> to initialize the driver. This macro ends up calling device_initcall as
> > >>> was used previously, but also allocates a platform device which gives us
> > >>> access to much nicer APIs such as platform_ioremap_resource,
> > >>> platform_get_irq and dev_err_probe.
> > >>
> > >> This is useful, but also there are other changes currently being sorted
> > >> out by Zong Li (cc'd into this message) which have already been reviewed
> > >> and are hopefully queued for the next kernel release.
> > >>
> > >>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > >>> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > >
> > > I'm ok with something like this being merged, but please note that if
> > > we ever want to support the JH7100 which uses registers in this
> > > peripheral to flush the cache for its non-coherent DMAs then this
> > > driver needs to be loaded before other peripherals or we will trigger
> > > the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> > > can do that when it's a platform driver. See this patch for an
> > > alternative to support the JH71x0s:
> > > https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
> > >
> > > /Emil
> >
> > Are you replying to your own patch that does the conversion to
> > platform driver and then saying that it could actually cause
> > issues?
> 
> Yes, I can see it seems odd, but this patch lived for a while in the
> kernel repo for the JH7100 until I rebased on 6.0-rc1 and realized the
> above.
> Hal Feng must have based his patches on a version of the code before
> that when preparing this series.
> 
> > I'm all for dropping this for the moment and keeping the old
> > early init for the ccache.
> 
> Cool.

FWIW, if converting to a platform driver will inhibit using the driver
for doing non-coherent stuff I would like to NAK the patch :)

> 
> /Emil
> 
> > >>>    drivers/soc/sifive/sifive_l2_cache.c | 79 ++++++++++++++--------------
> > >>>    1 file changed, 40 insertions(+), 39 deletions(-)
> > >>>
> > >>> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> > >>> index 59640a1d0b28..010d612f7420 100644
> > >>> --- a/drivers/soc/sifive/sifive_l2_cache.c
> > >>> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> > >>> @@ -7,9 +7,9 @@
> > >>>     */
> > >>>    #include <linux/debugfs.h>
> > >>>    #include <linux/interrupt.h>
> > >>> -#include <linux/of_irq.h>
> > >>> -#include <linux/of_address.h>
> > >>> -#include <linux/device.h>
> > >>> +#include <linux/io.h>
> > >>> +#include <linux/mod_devicetable.h>
> > >>> +#include <linux/platform_device.h>
> > >>>    #include <asm/cacheinfo.h>
> > >>>    #include <soc/sifive/sifive_l2_cache.h>
> > >>>
> > >>> @@ -96,12 +96,6 @@ static void l2_config_read(void)
> > >>>        pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> > >>>    }
> > >>>
> > >>> -static const struct of_device_id sifive_l2_ids[] = {
> > >>> -     { .compatible = "sifive,fu540-c000-ccache" },
> > >>> -     { .compatible = "sifive,fu740-c000-ccache" },
> > >>> -     { /* end of table */ },
> > >>> -};
> > >>> -
> > >>>    static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> > >>>
> > >>>    int register_sifive_l2_error_notifier(struct notifier_block *nb)
> > >>> @@ -192,36 +186,29 @@ static irqreturn_t l2_int_handler(int irq, void *device)
> > >>>        return IRQ_HANDLED;
> > >>>    }
> > >>>
> > >>> -static int __init sifive_l2_init(void)
> > >>> +static int __init sifive_l2_probe(struct platform_device *pdev)
> > >>>    {
> > >>> -     struct device_node *np;
> > >>> -     struct resource res;
> > >>> -     int i, rc, intr_num;
> > >>> -
> > >>> -     np = of_find_matching_node(NULL, sifive_l2_ids);
> > >>> -     if (!np)
> > >>> -             return -ENODEV;
> > >>> -
> > >>> -     if (of_address_to_resource(np, 0, &res))
> > >>> -             return -ENODEV;
> > >>> -
> > >>> -     l2_base = ioremap(res.start, resource_size(&res));
> > >>> -     if (!l2_base)
> > >>> -             return -ENOMEM;
> > >>> -
> > >>> -     intr_num = of_property_count_u32_elems(np, "interrupts");
> > >>> -     if (!intr_num) {
> > >>> -             pr_err("L2CACHE: no interrupts property\n");
> > >>> -             return -ENODEV;
> > >>> -     }
> > >>> -
> > >>> -     for (i = 0; i < intr_num; i++) {
> > >>> -             g_irq[i] = irq_of_parse_and_map(np, i);
> > >>> -             rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> > >>> -             if (rc) {
> > >>> -                     pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> > >>> -                     return rc;
> > >>> -             }
> > >>> +     struct device *dev = &pdev->dev;
> > >>> +     int nirqs;
> > >>> +     int ret;
> > >>> +     int i;
> > >>> +
> > >>> +     l2_base = devm_platform_ioremap_resource(pdev, 0);
> > >>> +     if (IS_ERR(l2_base))
> > >>> +             return PTR_ERR(l2_base);
> > >>> +
> > >>> +     nirqs = platform_irq_count(pdev);
> > >>> +     if (nirqs <= 0)
> > >>> +             return dev_err_probe(dev, -ENODEV, "no interrupts\n");
> > >>
> > >> I wonder if zero irqs is an actual issue here?
> > >>
> > >>> +     for (i = 0; i < nirqs; i++) {
> > >>> +             g_irq[i] = platform_get_irq(pdev, i);
> > >>
> > >> I wonder if we need to keep g_irq[] around now? Is it going to be useful
> > >> in the future?
> > >>
> > >>> +             if (g_irq[i] < 0)
> > >>> +                     return g_irq[i];
> > >>> +
> > >>> +             ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
> > >>> +             if (ret)
> > >>> +                     return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
> > >>>        }
> > >>>
> > >>>        l2_config_read();
> > >>> @@ -234,4 +221,18 @@ static int __init sifive_l2_init(void)
> > >>>    #endif
> > >>>        return 0;
> > >>>    }
> > >>> -device_initcall(sifive_l2_init);
> > >>> +
> > >>> +static const struct of_device_id sifive_l2_match[] = {
> > >>> +     { .compatible = "sifive,fu540-c000-ccache" },
> > >>> +     { .compatible = "sifive,fu740-c000-ccache" },
> > >>> +     { /* sentinel */ }
> > >>> +};
> > >>> +
> > >>> +static struct platform_driver sifive_l2_driver = {
> > >>> +     .driver = {
> > >>> +             .name = "sifive_l2_cache",
> > >>> +             .of_match_table = sifive_l2_match,
> > >>> +             .suppress_bind_attrs = true,
> > >>> +     },
> > >>> +};
> > >>> +builtin_platform_driver_probe(sifive_l2_driver, sifive_l2_probe);
> > >>
> > >>
> > >> _______________________________________________
> > >> linux-riscv mailing list
> > >> linux-riscv@lists.infradead.org
> > >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> > >
> >
> > --
> > Ben Dooks                               http://www.codethink.co.uk/
> > Senior Engineer                         Codethink - Providing Genius
> >
> > https://www.codethink.co.uk/privacy.html
> >

Re: [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver

[Hal Feng]

On Wed, 5 Oct 2022 15:05:03 +0100, Conor Dooley wrote:
> On Wed, Oct 05, 2022 at 03:55:17PM +0200, Emil Renner Berthing wrote:
> > On Wed, 5 Oct 2022 at 15:48, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> > >
> > > On 05/10/2022 14:44, Emil Renner Berthing wrote:
> > > > On Thu, 29 Sept 2022 at 19:59, Ben Dooks <ben.dooks@sifive.com> wrote:
> > > >>
> > > >> On 29/09/2022 15:32, Hal Feng wrote:
> > > >>> From: Emil Renner Berthing <kernel@esmil.dk>
> > > >>>
> > > >>> This converts the driver to use the builtin_platform_driver_probe macro
> > > >>> to initialize the driver. This macro ends up calling device_initcall as
> > > >>> was used previously, but also allocates a platform device which gives us
> > > >>> access to much nicer APIs such as platform_ioremap_resource,
> > > >>> platform_get_irq and dev_err_probe.
> > > >>
> > > >> This is useful, but also there are other changes currently being sorted
> > > >> out by Zong Li (cc'd into this message) which have already been reviewed
> > > >> and are hopefully queued for the next kernel release.
> > > >>
> > > >>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > > >>> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > > >
> > > > I'm ok with something like this being merged, but please note that if
> > > > we ever want to support the JH7100 which uses registers in this
> > > > peripheral to flush the cache for its non-coherent DMAs then this
> > > > driver needs to be loaded before other peripherals or we will trigger
> > > > the 2nd warning in arch/riscv/mm/dma-noncoherent.c. I'm not sure we
> > > > can do that when it's a platform driver. See this patch for an
> > > > alternative to support the JH71x0s:
> > > > https://github.com/esmil/linux/commit/9c5b29da56ae29159c9572c5bb195fe3a1b535c5
> > > >
> > > > /Emil
> > >
> > > Are you replying to your own patch that does the conversion to
> > > platform driver and then saying that it could actually cause
> > > issues?
> > 
> > Yes, I can see it seems odd, but this patch lived for a while in the
> > kernel repo for the JH7100 until I rebased on 6.0-rc1 and realized the
> > above.
> > Hal Feng must have based his patches on a version of the code before
> > that when preparing this series.
> > 
> > > I'm all for dropping this for the moment and keeping the old
> > > early init for the ccache.
> > 
> > Cool.
> 
> FWIW, if converting to a platform driver will inhibit using the driver
> for doing non-coherent stuff I would like to NAK the patch :)
> 

Yeah, I agree, and this patch will be dropped on the next version.

[PATCH v1 06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

This adds support for the StarFive JH7100 and JH7110 SoCs which also
feature this SiFive cache controller.

Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 arch/riscv/Kconfig.socs              | 1 +
 drivers/soc/Makefile                 | 2 +-
 drivers/soc/sifive/Kconfig           | 2 +-
 drivers/soc/sifive/sifive_l2_cache.c | 7 +++++++
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..10f68a4359f9 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,7 @@ config SOC_STARFIVE
 	bool "StarFive SoCs"
 	select PINCTRL
 	select RESET_CONTROLLER
+	select SIFIVE_L2
 	select SIFIVE_PLIC
 	help
 	  This enables support for StarFive SoC platform hardware.
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 69ba6508cf2c..534669840858 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -26,7 +26,7 @@ obj-y				+= qcom/
 obj-y				+= renesas/
 obj-y				+= rockchip/
 obj-$(CONFIG_SOC_SAMSUNG)	+= samsung/
-obj-$(CONFIG_SOC_SIFIVE)	+= sifive/
+obj-y				+= sifive/
 obj-y				+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-y				+= ti/
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c40d08d..776b30723c04 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE
 
 config SIFIVE_L2
 	bool "Sifive L2 Cache controller"
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 010d612f7420..d6637254977f 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -10,6 +10,7 @@
 #include <linux/io.h>
 #include <linux/mod_devicetable.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <asm/cacheinfo.h>
 #include <soc/sifive/sifive_l2_cache.h>
 
@@ -189,6 +190,7 @@ static irqreturn_t l2_int_handler(int irq, void *device)
 static int __init sifive_l2_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	unsigned long quirks = (uintptr_t)device_get_match_data(dev);
 	int nirqs;
 	int ret;
 	int i;
@@ -206,6 +208,9 @@ static int __init sifive_l2_probe(struct platform_device *pdev)
 		if (g_irq[i] < 0)
 			return g_irq[i];
 
+		if (quirks & BIT(i))
+			continue;
+
 		ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
 		if (ret)
 			return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
@@ -225,6 +230,8 @@ static int __init sifive_l2_probe(struct platform_device *pdev)
 static const struct of_device_id sifive_l2_match[] = {
 	{ .compatible = "sifive,fu540-c000-ccache" },
 	{ .compatible = "sifive,fu740-c000-ccache" },
+	{ .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
+	{ .compatible = "starfive,jh7110-ccache" },
 	{ /* sentinel */ }
 };
 
-- 
2.17.1

[PATCH v1 07/30] reset: starfive: jh7100: Use 32bit I/O on 32bit registers

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

We currently use 64bit I/O on the 32bit registers. This works because
there are an even number of assert and status registers, so they're only
ever accessed in pairs on 64bit boundaries.

There are however other reset controllers for audio and video on the
JH7100 SoC with only one status register that isn't 64bit aligned so
64bit I/O results in an unaligned access exception.

Switch to 32bit I/O in preparation for supporting these resets too.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 drivers/reset/reset-starfive-jh7100.c | 41 +++++++++++++--------------
 1 file changed, 20 insertions(+), 21 deletions(-)

diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
index fc44b2fb3e03..a6e0945071e9 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive-jh7100.c
@@ -7,7 +7,6 @@
 
 #include <linux/bitmap.h>
 #include <linux/io.h>
-#include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/iopoll.h>
 #include <linux/mod_devicetable.h>
 #include <linux/platform_device.h>
@@ -34,16 +33,16 @@
  * lines don't though, so store the expected value of the status registers when
  * all lines are asserted.
  */
-static const u64 jh7100_reset_asserted[2] = {
+static const u32 jh7100_reset_asserted[4] = {
 	/* STATUS0 */
-	BIT_ULL_MASK(JH7100_RST_U74) |
-	BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
-	BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
+	BIT(JH7100_RST_U74 % 32) |
+	BIT(JH7100_RST_VP6_DRESET % 32) |
+	BIT(JH7100_RST_VP6_BRESET % 32),
 	/* STATUS1 */
-	BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
-	BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
+	BIT(JH7100_RST_HIFI4_DRESET % 32) |
+	BIT(JH7100_RST_HIFI4_BRESET % 32),
 	/* STATUS2 */
-	BIT_ULL_MASK(JH7100_RST_E24) |
+	BIT(JH7100_RST_E24 % 32),
 	/* STATUS3 */
 	0,
 };
@@ -65,12 +64,12 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 			       unsigned long id, bool assert)
 {
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
-	unsigned long offset = BIT_ULL_WORD(id);
-	u64 mask = BIT_ULL_MASK(id);
-	void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
-	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
-	u64 done = jh7100_reset_asserted[offset] & mask;
-	u64 value;
+	unsigned long offset = id / 32;
+	u32 mask = BIT(id % 32);
+	void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u32);
+	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
+	u32 done = jh7100_reset_asserted[offset] & mask;
+	u32 value;
 	unsigned long flags;
 	int ret;
 
@@ -79,15 +78,15 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	value = readq(reg_assert);
+	value = readl(reg_assert);
 	if (assert)
 		value |= mask;
 	else
 		value &= ~mask;
-	writeq(value, reg_assert);
+	writel(value, reg_assert);
 
 	/* if the associated clock is gated, deasserting might otherwise hang forever */
-	ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+	ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
 
 	spin_unlock_irqrestore(&data->lock, flags);
 	return ret;
@@ -121,10 +120,10 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
-	unsigned long offset = BIT_ULL_WORD(id);
-	u64 mask = BIT_ULL_MASK(id);
-	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
-	u64 value = readq(reg_status);
+	unsigned long offset = id / 32;
+	u32 mask = BIT(id % 32);
+	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
+	u32 value = readl(reg_status);
 
 	return !((value ^ jh7100_reset_asserted[offset]) & mask);
 }
-- 
2.17.1

[PATCH v1 08/30] reset: starfive: jh7100: Use regmap APIs to operate registers

[Hal Feng]

Reset registers address region is shared with clock controller
on the new StarFive JH7110 SoC. Change to use regmap framework
to allow base address sharing and preparation for JH7110 reset
support.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 drivers/reset/reset-starfive-jh7100.c | 61 +++++++++++++++------------
 1 file changed, 34 insertions(+), 27 deletions(-)

diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
index a6e0945071e9..8cba62348a16 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive-jh7100.c
@@ -3,15 +3,14 @@
  * Reset driver for the StarFive JH7100 SoC
  *
  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2021-2022 StarFive Technology Co., Ltd.
  */
 
-#include <linux/bitmap.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/mod_devicetable.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <linux/spinlock.h>
 
 #include <dt-bindings/reset/starfive-jh7100.h>
 
@@ -49,9 +48,7 @@ static const u32 jh7100_reset_asserted[4] = {
 
 struct jh7100_reset {
 	struct reset_controller_dev rcdev;
-	/* protect registers against concurrent read-modify-write */
-	spinlock_t lock;
-	void __iomem *base;
+	struct regmap *regmap;
 };
 
 static inline struct jh7100_reset *
@@ -64,31 +61,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 			       unsigned long id, bool assert)
 {
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
-	unsigned long offset = id / 32;
+	u32 offset = id / 32;
 	u32 mask = BIT(id % 32);
-	void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u32);
-	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
+	u32 reg_assert = JH7100_RESET_ASSERT0 + offset * sizeof(u32);
+	u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
 	u32 done = jh7100_reset_asserted[offset] & mask;
 	u32 value;
-	unsigned long flags;
 	int ret;
 
 	if (!assert)
 		done ^= mask;
 
-	spin_lock_irqsave(&data->lock, flags);
-
-	value = readl(reg_assert);
 	if (assert)
-		value |= mask;
+		ret = regmap_update_bits(data->regmap, reg_assert, mask, mask);
 	else
-		value &= ~mask;
-	writel(value, reg_assert);
+		ret = regmap_update_bits(data->regmap, reg_assert, mask, 0);
+
+	if (ret)
+		return ret;
 
 	/* if the associated clock is gated, deasserting might otherwise hang forever */
-	ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+	ret = regmap_read_poll_timeout_atomic(data->regmap,
+					      reg_status,
+					      value, (value & mask) == done,
+					      0, 1000);
+	if (ret)
+		dev_warn(rcdev->dev, "id:%ld bank:%d, mask:%#x assert:%#x status:%#x ret:%d\n",
+			 id, offset, mask, reg_assert, reg_status, ret);
 
-	spin_unlock_irqrestore(&data->lock, flags);
 	return ret;
 }
 
@@ -120,10 +120,15 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
-	unsigned long offset = id / 32;
+	u32 offset = id / 32;
 	u32 mask = BIT(id % 32);
-	void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u32);
-	u32 value = readl(reg_status);
+	u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
+	u32 value;
+	int ret;
+
+	ret = regmap_read(data->regmap, reg_status, &value);
+	if (ret)
+		return ret;
 
 	return !((value ^ jh7100_reset_asserted[offset]) & mask);
 }
@@ -143,16 +148,18 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
 	if (!data)
 		return -ENOMEM;
 
-	data->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(data->base))
-		return PTR_ERR(data->base);
+	data->regmap = device_node_to_regmap(pdev->dev.of_node);
+	if (IS_ERR(data->regmap)) {
+		dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
+			PTR_ERR(data->regmap));
+		return PTR_ERR(data->regmap);
+	}
 
 	data->rcdev.ops = &jh7100_reset_ops;
 	data->rcdev.owner = THIS_MODULE;
 	data->rcdev.nr_resets = JH7100_RSTN_END;
 	data->rcdev.dev = &pdev->dev;
 	data->rcdev.of_node = pdev->dev.of_node;
-	spin_lock_init(&data->lock);
 
 	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
 }
-- 
2.17.1

[PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree

[Hal Feng]

Store the necessary properties in device tree instead of .c file,
in order to apply this reset driver to other StarFive SoCs.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++
 arch/riscv/boot/dts/starfive/jh7100.dtsi      |  3 ++
 drivers/reset/reset-starfive-jh7100.c         | 50 +++++++++++++------
 3 files changed, 57 insertions(+), 16 deletions(-)

diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
index 300359a5e14b..3eff3f72a1ed 100644
--- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
@@ -20,19 +20,39 @@ properties:
   "#reset-cells":
     const: 1
 
+  starfive,assert-offset:
+    description: Offset of the first ASSERT register
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  starfive,status-offset:
+    description: Offset of the first STATUS register
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  starfive,nr-resets:
+    description: Number of reset signals
+    $ref: /schemas/types.yaml#/definitions/uint32
+
 required:
   - compatible
   - reg
   - "#reset-cells"
+  - starfive,assert-offset
+  - starfive,status-offset
+  - starfive,nr-resets
 
 additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/reset/starfive-jh7100.h>
+
     reset-controller@11840000 {
         compatible = "starfive,jh7100-reset";
         reg = <0x11840000 0x10000>;
         #reset-cells = <1>;
+        starfive,assert-offset = <0x0>;
+        starfive,status-offset= <0x10>;
+        starfive,nr-resets = <JH7100_RSTN_END>;
     };
 
 ...
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 000447482aca..904a93411add 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -145,6 +145,9 @@
 			compatible = "starfive,jh7100-reset";
 			reg = <0x0 0x11840000 0x0 0x10000>;
 			#reset-cells = <1>;
+			starfive,assert-offset = <0x0>;
+			starfive,status-offset= <0x10>;
+			starfive,nr-resets = <JH7100_RSTN_END>;
 		};
 
 		i2c0: i2c@118b0000 {
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
index 8cba62348a16..d3656e99ae0e 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive-jh7100.c
@@ -14,16 +14,6 @@
 
 #include <dt-bindings/reset/starfive-jh7100.h>
 
-/* register offsets */
-#define JH7100_RESET_ASSERT0	0x00
-#define JH7100_RESET_ASSERT1	0x04
-#define JH7100_RESET_ASSERT2	0x08
-#define JH7100_RESET_ASSERT3	0x0c
-#define JH7100_RESET_STATUS0	0x10
-#define JH7100_RESET_STATUS1	0x14
-#define JH7100_RESET_STATUS2	0x18
-#define JH7100_RESET_STATUS3	0x1c
-
 /*
  * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
  * line 32m + n, and writing a 0 deasserts the same line.
@@ -49,6 +39,10 @@ static const u32 jh7100_reset_asserted[4] = {
 struct jh7100_reset {
 	struct reset_controller_dev rcdev;
 	struct regmap *regmap;
+	u32 assert_offset;
+	u32 status_offset;
+	u32 nr_resets;
+	const u32 *asserted;
 };
 
 static inline struct jh7100_reset *
@@ -63,9 +57,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
 	u32 offset = id / 32;
 	u32 mask = BIT(id % 32);
-	u32 reg_assert = JH7100_RESET_ASSERT0 + offset * sizeof(u32);
-	u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
-	u32 done = jh7100_reset_asserted[offset] & mask;
+	u32 reg_assert = data->assert_offset + offset * sizeof(u32);
+	u32 reg_status = data->status_offset + offset * sizeof(u32);
+	u32 done = data->asserted ? data->asserted[offset] & mask : 0;
 	u32 value;
 	int ret;
 
@@ -122,7 +116,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 	struct jh7100_reset *data = jh7100_reset_from(rcdev);
 	u32 offset = id / 32;
 	u32 mask = BIT(id % 32);
-	u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32);
+	u32 reg_status = data->status_offset + offset * sizeof(u32);
 	u32 value;
 	int ret;
 
@@ -130,7 +124,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 	if (ret)
 		return ret;
 
-	return !((value ^ jh7100_reset_asserted[offset]) & mask);
+	return !((value ^ data->asserted[offset]) & mask);
 }
 
 static const struct reset_control_ops jh7100_reset_ops = {
@@ -143,6 +137,7 @@ static const struct reset_control_ops jh7100_reset_ops = {
 static int __init jh7100_reset_probe(struct platform_device *pdev)
 {
 	struct jh7100_reset *data;
+	int ret;
 
 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
@@ -155,12 +150,35 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
 		return PTR_ERR(data->regmap);
 	}
 
+	ret = of_property_read_u32(pdev->dev.of_node, "starfive,assert-offset",
+				   &data->assert_offset);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get starfive,assert-offset: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(pdev->dev.of_node, "starfive,status-offset",
+				   &data->status_offset);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get starfive,status-offset: %d\n", ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(pdev->dev.of_node, "starfive,nr-resets",
+				   &data->nr_resets);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get starfive,nr-resets: %d\n", ret);
+		return ret;
+	}
+
 	data->rcdev.ops = &jh7100_reset_ops;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = JH7100_RSTN_END;
+	data->rcdev.nr_resets = data->nr_resets;
 	data->rcdev.dev = &pdev->dev;
 	data->rcdev.of_node = pdev->dev.of_node;
 
+	data->asserted = jh7100_reset_asserted;
+
 	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
 }
 
-- 
2.17.1

Re: [PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree

[Rob Herring]

On Thu, Sep 29, 2022 at 10:32:04PM +0800, Hal Feng wrote:
> Store the necessary properties in device tree instead of .c file,
> in order to apply this reset driver to other StarFive SoCs.
> 
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++
>  arch/riscv/boot/dts/starfive/jh7100.dtsi      |  3 ++
>  drivers/reset/reset-starfive-jh7100.c         | 50 +++++++++++++------
>  3 files changed, 57 insertions(+), 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> index 300359a5e14b..3eff3f72a1ed 100644
> --- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> @@ -20,19 +20,39 @@ properties:
>    "#reset-cells":
>      const: 1
>  
> +  starfive,assert-offset:
> +    description: Offset of the first ASSERT register
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +
> +  starfive,status-offset:
> +    description: Offset of the first STATUS register
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +
> +  starfive,nr-resets:
> +    description: Number of reset signals
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +
>  required:
>    - compatible
>    - reg
>    - "#reset-cells"
> +  - starfive,assert-offset
> +  - starfive,status-offset
> +  - starfive,nr-resets

Adding required properties is a red flag. You can't add required 
properties to an existing binding. That breaks the ABI unless the OS 
deals with the properties being absent. If the OS has to do that, then 
why add them in the first place? All this should be implied by the 
compatible string.

Rob

Re: [PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree

[Emil Renner Berthing]

On Fri, 30 Sept 2022 at 22:51, Rob Herring <robh@kernel.org> wrote:
>
> On Thu, Sep 29, 2022 at 10:32:04PM +0800, Hal Feng wrote:
> > Store the necessary properties in device tree instead of .c file,
> > in order to apply this reset driver to other StarFive SoCs.
> >
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> >  .../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++
> >  arch/riscv/boot/dts/starfive/jh7100.dtsi      |  3 ++
> >  drivers/reset/reset-starfive-jh7100.c         | 50 +++++++++++++------
> >  3 files changed, 57 insertions(+), 16 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> > index 300359a5e14b..3eff3f72a1ed 100644
> > --- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> > +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
> > @@ -20,19 +20,39 @@ properties:
> >    "#reset-cells":
> >      const: 1
> >
> > +  starfive,assert-offset:
> > +    description: Offset of the first ASSERT register
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > +  starfive,status-offset:
> > +    description: Offset of the first STATUS register
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > +  starfive,nr-resets:
> > +    description: Number of reset signals
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +
> >  required:
> >    - compatible
> >    - reg
> >    - "#reset-cells"
> > +  - starfive,assert-offset
> > +  - starfive,status-offset
> > +  - starfive,nr-resets
>
> Adding required properties is a red flag. You can't add required
> properties to an existing binding. That breaks the ABI unless the OS
> deals with the properties being absent. If the OS has to do that, then
> why add them in the first place? All this should be implied by the
> compatible string.

Indeed. I really don't understand why this is even necessary. As
mentioned in my reply to the clock driver my original code just had a
combined driver for the whole CRG (clock and reset generator I
presume), and then you just need a simple node like this:

syscrg: clock-controller@13020000 {
    compatible = "starfive,jh7110-syscrg";
    reg = <0x0 0x13020000 0x0 0x10000>;
    clocks = <&osc>, <&gmac1_rmii_refin>,
             <&gmac1_rgmii_rxin>,
             <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
             <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
             <&tdm_ext>, <&mclk_ext>;
    clock-names = "osc", "gmac1_rmii_refin",
                  "gmac1_rgmii_rxin",
                  "i2stx_bclk_ext", "i2stx_lrck_ext",
                  "i2srx_bclk_ext", "i2srx_lrck_ext",
                  "tdm_ext", "mclk_ext";
    #clock-cells = <1>;
    #reset-cells = <1>;
};

/Emil

[PATCH v1 10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c'

[Hal Feng]

So this reset driver can be compatible with other StarFive SoCs.
No functional change.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 MAINTAINERS                                   |  9 +--
 drivers/reset/Kconfig                         |  6 +-
 drivers/reset/Makefile                        |  2 +-
 ...set-starfive-jh7100.c => reset-starfive.c} | 68 +++++++++----------
 4 files changed, 43 insertions(+), 42 deletions(-)
 rename drivers/reset/{reset-starfive-jh7100.c => reset-starfive.c} (70%)

diff --git a/MAINTAINERS b/MAINTAINERS
index f5ca4aefd184..f2319a3b708b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19411,12 +19411,13 @@ F:	Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
 F:	drivers/pinctrl/pinctrl-starfive.c
 F:	include/dt-bindings/pinctrl/pinctrl-starfive.h
 
-STARFIVE JH7100 RESET CONTROLLER DRIVER
+STARFIVE RESET CONTROLLER DRIVER
 M:	Emil Renner Berthing <kernel@esmil.dk>
+M:	Hal Feng <hal.feng@linux.starfivetech.com>
 S:	Maintained
-F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-F:	drivers/reset/reset-starfive-jh7100.c
-F:	include/dt-bindings/reset/starfive-jh7100.h
+F:	Documentation/devicetree/bindings/reset/starfive*
+F:	drivers/reset/reset-starfive.c
+F:	include/dt-bindings/reset/starfive*
 
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 806773e88832..8121de5ecc3c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -225,12 +225,12 @@ config RESET_SOCFPGA
 	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
 	  driver gets initialized early during platform init calls.
 
-config RESET_STARFIVE_JH7100
-	bool "StarFive JH7100 Reset Driver"
+config RESET_STARFIVE
+	bool "StarFive SoC Reset Driver"
 	depends on SOC_STARFIVE || COMPILE_TEST
 	default SOC_STARFIVE
 	help
-	  This enables the reset controller driver for the StarFive JH7100 SoC.
+	  This enables the reset controller driver for the StarFive SoCs.
 
 config RESET_SUNPLUS
 	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index cd5cf8e7c6a7..269268a48f56 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
-obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+obj-$(CONFIG_RESET_STARFIVE) += reset-starfive.o
 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive.c
similarity index 70%
rename from drivers/reset/reset-starfive-jh7100.c
rename to drivers/reset/reset-starfive.c
index d3656e99ae0e..56d07bafadd7 100644
--- a/drivers/reset/reset-starfive-jh7100.c
+++ b/drivers/reset/reset-starfive.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Reset driver for the StarFive JH7100 SoC
+ * Reset driver for the StarFive SoC
  *
  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
  * Copyright (C) 2021-2022 StarFive Technology Co., Ltd.
@@ -36,7 +36,7 @@ static const u32 jh7100_reset_asserted[4] = {
 	0,
 };
 
-struct jh7100_reset {
+struct starfive_reset {
 	struct reset_controller_dev rcdev;
 	struct regmap *regmap;
 	u32 assert_offset;
@@ -45,16 +45,16 @@ struct jh7100_reset {
 	const u32 *asserted;
 };
 
-static inline struct jh7100_reset *
-jh7100_reset_from(struct reset_controller_dev *rcdev)
+static inline struct starfive_reset *
+starfive_reset_from(struct reset_controller_dev *rcdev)
 {
-	return container_of(rcdev, struct jh7100_reset, rcdev);
+	return container_of(rcdev, struct starfive_reset, rcdev);
 }
 
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
-			       unsigned long id, bool assert)
+static int starfive_reset_update(struct reset_controller_dev *rcdev,
+				 unsigned long id, bool assert)
 {
-	struct jh7100_reset *data = jh7100_reset_from(rcdev);
+	struct starfive_reset *data = starfive_reset_from(rcdev);
 	u32 offset = id / 32;
 	u32 mask = BIT(id % 32);
 	u32 reg_assert = data->assert_offset + offset * sizeof(u32);
@@ -86,34 +86,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 	return ret;
 }
 
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
-			       unsigned long id)
+static int starfive_reset_assert(struct reset_controller_dev *rcdev,
+				 unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, true);
+	return starfive_reset_update(rcdev, id, true);
 }
 
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
-				 unsigned long id)
+static int starfive_reset_deassert(struct reset_controller_dev *rcdev,
+				   unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, false);
+	return starfive_reset_update(rcdev, id, false);
 }
 
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int starfive_reset_reset(struct reset_controller_dev *rcdev,
+				unsigned long id)
 {
 	int ret;
 
-	ret = jh7100_reset_assert(rcdev, id);
+	ret = starfive_reset_assert(rcdev, id);
 	if (ret)
 		return ret;
 
-	return jh7100_reset_deassert(rcdev, id);
+	return starfive_reset_deassert(rcdev, id);
 }
 
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
-			       unsigned long id)
+static int starfive_reset_status(struct reset_controller_dev *rcdev,
+				 unsigned long id)
 {
-	struct jh7100_reset *data = jh7100_reset_from(rcdev);
+	struct starfive_reset *data = starfive_reset_from(rcdev);
 	u32 offset = id / 32;
 	u32 mask = BIT(id % 32);
 	u32 reg_status = data->status_offset + offset * sizeof(u32);
@@ -127,16 +127,16 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 	return !((value ^ data->asserted[offset]) & mask);
 }
 
-static const struct reset_control_ops jh7100_reset_ops = {
-	.assert		= jh7100_reset_assert,
-	.deassert	= jh7100_reset_deassert,
-	.reset		= jh7100_reset_reset,
-	.status		= jh7100_reset_status,
+static const struct reset_control_ops starfive_reset_ops = {
+	.assert		= starfive_reset_assert,
+	.deassert	= starfive_reset_deassert,
+	.reset		= starfive_reset_reset,
+	.status		= starfive_reset_status,
 };
 
-static int __init jh7100_reset_probe(struct platform_device *pdev)
+static int __init starfive_reset_probe(struct platform_device *pdev)
 {
-	struct jh7100_reset *data;
+	struct starfive_reset *data;
 	int ret;
 
 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
@@ -171,7 +171,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	data->rcdev.ops = &jh7100_reset_ops;
+	data->rcdev.ops = &starfive_reset_ops;
 	data->rcdev.owner = THIS_MODULE;
 	data->rcdev.nr_resets = data->nr_resets;
 	data->rcdev.dev = &pdev->dev;
@@ -182,16 +182,16 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
 	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
 }
 
-static const struct of_device_id jh7100_reset_dt_ids[] = {
+static const struct of_device_id starfive_reset_dt_ids[] = {
 	{ .compatible = "starfive,jh7100-reset" },
 	{ /* sentinel */ }
 };
 
-static struct platform_driver jh7100_reset_driver = {
+static struct platform_driver starfive_reset_driver = {
 	.driver = {
-		.name = "jh7100-reset",
-		.of_match_table = jh7100_reset_dt_ids,
+		.name = "starfive-reset",
+		.of_match_table = starfive_reset_dt_ids,
 		.suppress_bind_attrs = true,
 	},
 };
-builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
+builtin_platform_driver_probe(starfive_reset_driver, starfive_reset_probe);
-- 
2.17.1

Re: [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support

[Krzysztof Kozlowski]

On 29/09/2022 16:31, Hal Feng wrote:

> This series is also available at 
> https://github.com/hal-feng/linux/commits/visionfive2-minimal
> 
> [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> [2] https://wiki.rvspace.org/
> 
> Emil Renner Berthing (17):
>   dt-bindings: riscv: Add StarFive JH7110 bindings
>   dt-bindings: timer: Add StarFive JH7110 clint
>   dt-bindings: interrupt-controller: Add StarFive JH7110 plic
>   dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
>   soc: sifive: l2 cache: Convert to platform driver
>   soc: sifive: l2 cache: Add StarFive JH71x0 support
>   reset: starfive: jh7100: Use 32bit I/O on 32bit registers
>   dt-bindings: reset: Add StarFive JH7110 reset definitions
>   clk: starfive: Factor out common clock driver code
>   dt-bindings: clock: Add StarFive JH7110 system clock definitions
>   dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
>   clk: starfive: Add StarFive JH7110 system clock driver
>   dt-bindings: clock: Add StarFive JH7110 always-on definitions
>   dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
>   clk: starfive: Add StarFive JH7110 always-on clock driver
>   RISC-V: Add initial StarFive JH7110 device tree
>   RISC-V: Add StarFive JH7110 VisionFive2 board device tree

Where is the rest of patches? Lists got only 5 of them. Anyway this is a
bit too big patchset. Split per subsystem.

Best regards,
Krzysztof

Re: [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support

[Conor Dooley]

On Thu, Sep 29, 2022 at 04:45:26PM +0200, Krzysztof Kozlowski wrote:
> On 29/09/2022 16:31, Hal Feng wrote:
> 
> > This series is also available at 
> > https://github.com/hal-feng/linux/commits/visionfive2-minimal
> > 
> > [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> > [2] https://wiki.rvspace.org/
> > 
> > Emil Renner Berthing (17):
> >   dt-bindings: riscv: Add StarFive JH7110 bindings
> >   dt-bindings: timer: Add StarFive JH7110 clint
> >   dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> >   dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
> >   soc: sifive: l2 cache: Convert to platform driver
> >   soc: sifive: l2 cache: Add StarFive JH71x0 support
> >   reset: starfive: jh7100: Use 32bit I/O on 32bit registers
> >   dt-bindings: reset: Add StarFive JH7110 reset definitions
> >   clk: starfive: Factor out common clock driver code
> >   dt-bindings: clock: Add StarFive JH7110 system clock definitions
> >   dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
> >   clk: starfive: Add StarFive JH7110 system clock driver
> >   dt-bindings: clock: Add StarFive JH7110 always-on definitions
> >   dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
> >   clk: starfive: Add StarFive JH7110 always-on clock driver
> >   RISC-V: Add initial StarFive JH7110 device tree
> >   RISC-V: Add StarFive JH7110 VisionFive2 board device tree
> 
> Where is the rest of patches? Lists got only 5 of them. Anyway this is a
> bit too big patchset. Split per subsystem.

They seem to be coming in over time in dribs and drabs. I assume it is
not a mailing list problem given how many lists are CCed on the mail and
the fact that they have different providers.

For v2 (or multiple v2s) please fix up your process so that this gets
sent normally and not a couple of patches every hour.

Thanks,
Conor.

Re: [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support

[hal.feng]

On Thu, Sep 29, 2022 at 18:59:24 +0100, Conor Dooley wrote:
> On Thu, Sep 29, 2022 at 04:45:26PM +0200, Krzysztof Kozlowski wrote:
> > On 29/09/2022 16:31, Hal Feng wrote:
> >
> > > This series is also available at
> > > https://github.com/hal-feng/linux/commits/visionfive2-minimal
> > >
> > > [1]
> > > https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-c
> > > ore-risc-v-sbc-linux/
> > > [2] https://wiki.rvspace.org/
> > >
> > > Emil Renner Berthing (17):
> > >   dt-bindings: riscv: Add StarFive JH7110 bindings
> > >   dt-bindings: timer: Add StarFive JH7110 clint
> > >   dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> > >   dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
> > >   soc: sifive: l2 cache: Convert to platform driver
> > >   soc: sifive: l2 cache: Add StarFive JH71x0 support
> > >   reset: starfive: jh7100: Use 32bit I/O on 32bit registers
> > >   dt-bindings: reset: Add StarFive JH7110 reset definitions
> > >   clk: starfive: Factor out common clock driver code
> > >   dt-bindings: clock: Add StarFive JH7110 system clock definitions
> > >   dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
> > >   clk: starfive: Add StarFive JH7110 system clock driver
> > >   dt-bindings: clock: Add StarFive JH7110 always-on definitions
> > >   dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
> > >   clk: starfive: Add StarFive JH7110 always-on clock driver
> > >   RISC-V: Add initial StarFive JH7110 device tree
> > >   RISC-V: Add StarFive JH7110 VisionFive2 board device tree
> >
> > Where is the rest of patches? Lists got only 5 of them. Anyway this is
> > a bit too big patchset. Split per subsystem.
> 
> They seem to be coming in over time in dribs and drabs. I assume it is not
a
> mailing list problem given how many lists are CCed on the mail and the
fact
> that they have different providers.
> 
> For v2 (or multiple v2s) please fix up your process so that this gets sent
> normally and not a couple of patches every hour.

Our email server has technical issue and we are aware of this.
Will fix in next revision. Sorry for the inconvenience caused.

Best Regards,
Hal

[PATCH v1 11/30] dt-bindings: reset: Add StarFive JH7110 reset definitions

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add resets for the StarFive JH7110 reset controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 include/dt-bindings/reset/starfive-jh7110.h | 154 ++++++++++++++++++++
 1 file changed, 154 insertions(+)
 create mode 100644 include/dt-bindings/reset/starfive-jh7110.h

diff --git a/include/dt-bindings/reset/starfive-jh7110.h b/include/dt-bindings/reset/starfive-jh7110.h
new file mode 100644
index 000000000000..512bd8834efb
--- /dev/null
+++ b/include/dt-bindings/reset/starfive-jh7110.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+
+/* syscrg_rst */
+#define JH7110_SYSRST_JTAG2APB			  0
+#define JH7110_SYSRST_SYSCON			  1
+#define JH7110_SYSRST_IOMUX			  2
+#define JH7110_SYSRST_BUS			  3
+#define JH7110_SYSRST_DEBUG			  4
+#define JH7110_SYSRST_CORE0			  5
+#define JH7110_SYSRST_CORE1			  6
+#define JH7110_SYSRST_CORE2			  7
+#define JH7110_SYSRST_CORE3			  8
+#define JH7110_SYSRST_CORE4			  9
+#define JH7110_SYSRST_CORE0_ST			 10
+#define JH7110_SYSRST_CORE1_ST			 11
+#define JH7110_SYSRST_CORE2_ST			 12
+#define JH7110_SYSRST_CORE3_ST			 13
+#define JH7110_SYSRST_CORE4_ST			 14
+#define JH7110_SYSRST_TRACE0			 15
+#define JH7110_SYSRST_TRACE1			 16
+#define JH7110_SYSRST_TRACE2			 17
+#define JH7110_SYSRST_TRACE3			 18
+#define JH7110_SYSRST_TRACE4			 19
+#define JH7110_SYSRST_TRACE_COM			 20
+#define JH7110_SYSRST_GPU_APB			 21
+#define JH7110_SYSRST_GPU_DOMA			 22
+#define JH7110_SYSRST_NOC_BUS_APB_BUS		 23
+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI	 24
+#define JH7110_SYSRST_NOC_BUS_CPU_AXI		 25
+#define JH7110_SYSRST_NOC_BUS_DISP_AXI		 26
+#define JH7110_SYSRST_NOC_BUS_GPU_AXI		 27
+#define JH7110_SYSRST_NOC_BUS_ISP_AXI		 28
+#define JH7110_SYSRST_NOC_BUS_DDRC		 29
+#define JH7110_SYSRST_NOC_BUS_STG_AXI		 30
+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI		 31
+
+#define JH7110_SYSRST_NOC_BUS_VENC_AXI		 32
+#define JH7110_SYSRST_AXI_CFG1_DEC_AHB		 33
+#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN		 34
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN		 35
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV	 36
+#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4	 37
+#define JH7110_SYSRST_DDR_AXI			 38
+#define JH7110_SYSRST_DDR_OSC			 39
+#define JH7110_SYSRST_DDR_APB			 40
+#define JH7110_SYSRST_DOM_ISP_TOP_N		 41
+#define JH7110_SYSRST_DOM_ISP_TOP_AXI		 42
+#define JH7110_SYSRST_DOM_VOUT_TOP_SRC		 43
+#define JH7110_SYSRST_CODAJ12_AXI		 44
+#define JH7110_SYSRST_CODAJ12_CORE		 45
+#define JH7110_SYSRST_CODAJ12_APB		 46
+#define JH7110_SYSRST_WAVE511_AXI		 47
+#define JH7110_SYSRST_WAVE511_BPU		 48
+#define JH7110_SYSRST_WAVE511_VCE		 49
+#define JH7110_SYSRST_WAVE511_APB		 50
+#define JH7110_SYSRST_VDEC_JPG_ARB_JPG		 51
+#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN		 52
+#define JH7110_SYSRST_AXIMEM0_AXI		 53
+#define JH7110_SYSRST_WAVE420L_AXI		 54
+#define JH7110_SYSRST_WAVE420L_BPU		 55
+#define JH7110_SYSRST_WAVE420L_VCE		 56
+#define JH7110_SYSRST_WAVE420L_APB		 57
+#define JH7110_SYSRST_AXIMEM1_AXI		 58
+#define JH7110_SYSRST_AXIMEM2_AXI		 59
+#define JH7110_SYSRST_INTMEM			 60
+#define JH7110_SYSRST_QSPI_AHB			 61
+#define JH7110_SYSRST_QSPI_APB			 62
+#define JH7110_SYSRST_QSPI_REF			 63
+
+#define JH7110_SYSRST_SDIO0_AHB			 64
+#define JH7110_SYSRST_SDIO1_AHB			 65
+#define JH7110_SYSRST_GMAC1_AXI			 66
+#define JH7110_SYSRST_GMAC1_AHB			 67
+#define JH7110_SYSRST_MAILBOX			 68
+#define JH7110_SYSRST_SPI0_APB			 69
+#define JH7110_SYSRST_SPI1_APB			 70
+#define JH7110_SYSRST_SPI2_APB			 71
+#define JH7110_SYSRST_SPI3_APB			 72
+#define JH7110_SYSRST_SPI4_APB			 73
+#define JH7110_SYSRST_SPI5_APB			 74
+#define JH7110_SYSRST_SPI6_APB			 75
+#define JH7110_SYSRST_I2C0_APB			 76
+#define JH7110_SYSRST_I2C1_APB			 77
+#define JH7110_SYSRST_I2C2_APB			 78
+#define JH7110_SYSRST_I2C3_APB			 79
+#define JH7110_SYSRST_I2C4_APB			 80
+#define JH7110_SYSRST_I2C5_APB			 81
+#define JH7110_SYSRST_I2C6_APB			 82
+#define JH7110_SYSRST_UART0_APB			 83
+#define JH7110_SYSRST_UART0_CORE		 84
+#define JH7110_SYSRST_UART1_APB			 85
+#define JH7110_SYSRST_UART1_CORE		 86
+#define JH7110_SYSRST_UART2_APB			 87
+#define JH7110_SYSRST_UART2_CORE		 88
+#define JH7110_SYSRST_UART3_APB			 89
+#define JH7110_SYSRST_UART3_CORE		 90
+#define JH7110_SYSRST_UART4_APB			 91
+#define JH7110_SYSRST_UART4_CORE		 92
+#define JH7110_SYSRST_UART5_APB			 93
+#define JH7110_SYSRST_UART5_CORE		 94
+#define JH7110_SYSRST_SPDIF_APB			 95
+
+#define JH7110_SYSRST_PWMDAC_APB		 96
+#define JH7110_SYSRST_PDM_DMIC			 97
+#define JH7110_SYSRST_PDM_APB			 98
+#define JH7110_SYSRST_I2SRX_APB			 99
+#define JH7110_SYSRST_I2SRX_BCLK		100
+#define JH7110_SYSRST_I2STX0_APB		101
+#define JH7110_SYSRST_I2STX0_BCLK		102
+#define JH7110_SYSRST_I2STX1_APB		103
+#define JH7110_SYSRST_I2STX1_BCLK		104
+#define JH7110_SYSRST_TDM_AHB			105
+#define JH7110_SYSRST_TDM_CORE			106
+#define JH7110_SYSRST_TDM_APB			107
+#define JH7110_SYSRST_PWM_APB			108
+#define JH7110_SYSRST_WDT_APB			109
+#define JH7110_SYSRST_WDT_CORE			110
+#define JH7110_SYSRST_CAN0_APB			111
+#define JH7110_SYSRST_CAN0_CORE			112
+#define JH7110_SYSRST_CAN0_TIMER		113
+#define JH7110_SYSRST_CAN1_APB			114
+#define JH7110_SYSRST_CAN1_CORE			115
+#define JH7110_SYSRST_CAN1_TIMER		116
+#define JH7110_SYSRST_TIMER_APB			117
+#define JH7110_SYSRST_TIMER0			118
+#define JH7110_SYSRST_TIMER1			119
+#define JH7110_SYSRST_TIMER2			120
+#define JH7110_SYSRST_TIMER3			121
+#define JH7110_SYSRST_INT_CTRL_APB		122
+#define JH7110_SYSRST_TEMP_APB			123
+#define JH7110_SYSRST_TEMP_CORE			124
+#define JH7110_SYSRST_JTAG_CERTIFICATION	125
+
+#define	JH7110_SYSRST_END			126
+
+/* aoncrg_rst */
+#define JH7110_AONRST_GMAC0_AXI		0
+#define JH7110_AONRST_GMAC0_AHB		1
+#define JH7110_AONRST_AON_IOMUX		2
+#define JH7110_AONRST_PMU_APB		3
+#define JH7110_AONRST_PMU_WKUP		4
+#define JH7110_AONRST_RTC_APB		5
+#define JH7110_AONRST_RTC_CAL		6
+#define JH7110_AONRST_RTC_32K		7
+
+#define	JH7110_AONRST_END		8
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
-- 
2.17.1

[PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Hal Feng]

Add bindings for the reset controller on the JH7110 RISC-V
SoC by StarFive Technology Ltd.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
new file mode 100644
index 000000000000..bb0010c200f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
+
+maintainers:
+  - Emil Renner Berthing <kernel@esmil.dk>
+  - Hal Feng <hal.feng@linux.starfivetech.com>
+
+properties:
+  compatible:
+    enum:
+      - starfive,jh7110-reset
+
+  "#reset-cells":
+    const: 1
+
+  starfive,assert-offset:
+    description: Offset of the first ASSERT register
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  starfive,status-offset:
+    description: Offset of the first STATUS register
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  starfive,nr-resets:
+    description: Number of reset signals
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+  - compatible
+  - "#reset-cells"
+  - starfive,assert-offset
+  - starfive,status-offset
+  - starfive,nr-resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/starfive-jh7110.h>
+
+    syscrg_rst: reset-controller@13020000 {
+        compatible = "starfive,jh7110-reset";
+        #reset-cells = <1>;
+        starfive,assert-offset = <0x2F8>;
+        starfive,status-offset= <0x308>;
+        starfive,nr-resets = <JH7110_SYSRST_END>;
+    };
+
+...
-- 
2.17.1

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Rob Herring]

On Fri, 30 Sep 2022 01:51:47 +0800, Hal Feng wrote:
> Add bindings for the reset controller on the JH7110 RISC-V
> SoC by StarFive Technology Ltd.
> 
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dts:18:18: fatal error: dt-bindings/reset/starfive-jh7110.h: No such file or directory
   18 |         #include <dt-bindings/reset/starfive-jh7110.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1420: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Rob Herring]

On Thu, Sep 29, 2022 at 01:21:56PM -0500, Rob Herring wrote:
> On Fri, 30 Sep 2022 01:51:47 +0800, Hal Feng wrote:
> > Add bindings for the reset controller on the JH7110 RISC-V
> > SoC by StarFive Technology Ltd.
> > 
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> >  .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > 
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dts:18:18: fatal error: dt-bindings/reset/starfive-jh7110.h: No such file or directory
>    18 |         #include <dt-bindings/reset/starfive-jh7110.h>
>       |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
> make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/reset/starfive,jh7110-reset.example.dtb] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1420: dt_binding_check] Error 2

Looks to be because this series got moderated and came in waves. In any 
case, patches 11 and 12 can be combined. Same for any other bindings and 
binding headers.

Rob

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Rob Herring]

On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
> Add bindings for the reset controller on the JH7110 RISC-V
> SoC by StarFive Technology Ltd.
> 
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> new file mode 100644
> index 000000000000..bb0010c200f9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
> +
> +maintainers:
> +  - Emil Renner Berthing <kernel@esmil.dk>
> +  - Hal Feng <hal.feng@linux.starfivetech.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - starfive,jh7110-reset

'reg' needed? Is this a sub-block of something else?

> +
> +  "#reset-cells":
> +    const: 1
> +
> +  starfive,assert-offset:
> +    description: Offset of the first ASSERT register
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +
> +  starfive,status-offset:
> +    description: Offset of the first STATUS register
> +    $ref: /schemas/types.yaml#/definitions/uint32

These can't be implied from the compatible string?

> +
> +  starfive,nr-resets:
> +    description: Number of reset signals
> +    $ref: /schemas/types.yaml#/definitions/uint32

Why do you need this? Most bindings don't. If just to validate 'resets' 
args, then don't.


> +
> +required:
> +  - compatible
> +  - "#reset-cells"
> +  - starfive,assert-offset
> +  - starfive,status-offset
> +  - starfive,nr-resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/starfive-jh7110.h>
> +
> +    syscrg_rst: reset-controller@13020000 {
> +        compatible = "starfive,jh7110-reset";
> +        #reset-cells = <1>;
> +        starfive,assert-offset = <0x2F8>;
> +        starfive,status-offset= <0x308>;
> +        starfive,nr-resets = <JH7110_SYSRST_END>;
> +    };
> +
> +...
> -- 
> 2.17.1
> 
> 

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Hal Feng]

On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
> On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
> > Add bindings for the reset controller on the JH7110 RISC-V
> > SoC by StarFive Technology Ltd.
> > 
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> >  .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > new file mode 100644
> > index 000000000000..bb0010c200f9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > @@ -0,0 +1,54 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
> > +
> > +maintainers:
> > +  - Emil Renner Berthing <kernel@esmil.dk>
> > +  - Hal Feng <hal.feng@linux.starfivetech.com>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - starfive,jh7110-reset
> 
> 'reg' needed? Is this a sub-block of something else?

Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
You might not see the complete patches at that time due to technical issue of
our smtp email server. Again, I feel so sorry about that.

	syscrg: syscrg@13020000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x13020000 0x0 0x10000>;

		syscrg_clk: clock-controller@13020000 {
			compatible = "starfive,jh7110-clkgen-sys";
			clocks = <&osc>, <&gmac1_rmii_refin>,
				 <&gmac1_rgmii_rxin>,
				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
				 <&tdm_ext>, <&mclk_ext>;
			clock-names = "osc", "gmac1_rmii_refin",
				"gmac1_rgmii_rxin",
				"i2stx_bclk_ext", "i2stx_lrck_ext",
				"i2srx_bclk_ext", "i2srx_lrck_ext",
				"tdm_ext", "mclk_ext";
			#clock-cells = <1>;
		};

		syscrg_rst: reset-controller@13020000 {
			compatible = "starfive,jh7110-reset";
			#reset-cells = <1>;
			starfive,assert-offset = <0x2F8>;
			starfive,status-offset= <0x308>;
			starfive,nr-resets = <JH7110_SYSRST_END>;
		};
	};

In this case, we get the memory mapped space through the parent node with syscon
APIs. You can see patch 13 for detail.

static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
{
	struct starfive_reset *data;
	int ret;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->regmap = device_node_to_regmap(pdev->dev.of_node);		  //for JH7100
	if (IS_ERR(data->regmap)) {
		data->regmap = syscon_node_to_regmap(pdev->dev.of_node->parent);  //for JH7110
		if (IS_ERR(data->regmap)) {
			dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
				PTR_ERR(data->regmap));
			return PTR_ERR(data->regmap);
		}
	}
	...
}

We use this method to avoid errors when remapping the same address in two
different drivers, because clock and reset of StarFive JH7110 share a common
register address region. For similar implementation, refer to file [1] and [2].

[1] arch/riscv/boot/dts/canaan/k210.dtsi

	sysctl: syscon@50440000 {
		compatible = "canaan,k210-sysctl",
			     "syscon", "simple-mfd";
		reg = <0x50440000 0x100>;
		clocks = <&sysclk K210_CLK_APB1>;
		clock-names = "pclk";

		sysclk: clock-controller {
			#clock-cells = <1>;
			compatible = "canaan,k210-clk";
			clocks = <&in0>;
		};

		sysrst: reset-controller {
			compatible = "canaan,k210-rst";
			#reset-cells = <1>;
		};

		reboot: syscon-reboot {
			compatible = "syscon-reboot";
			regmap = <&sysctl>;
			offset = <48>;
			mask = <1>;
			value = <1>;
		};
	};

[2] drivers/reset/reset-k210.c

> 
> > +
> > +  "#reset-cells":
> > +    const: 1
> > +
> > +  starfive,assert-offset:
> > +    description: Offset of the first ASSERT register
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > +  starfive,status-offset:
> > +    description: Offset of the first STATUS register
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> 
> These can't be implied from the compatible string?

These two properties are the key differences among different reset controllers.
There are five memory regions for clock and reset in StarFive JH7110 SoC. They
are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
has different reset ASSERT/STATUS register offset and different number of reset
signals. After storing them in dt, the reset driver can register all reset
controllers with the same compatible string. All we expect is that all reset
controllers in a single SoC use the same compatible string for matching and the
reset driver can be applied to all StarFive SoCs using different compatible strings.
Just like

arch/riscv/boot/dts/starfive/jh7100.dtsi:

	rstgen: reset-controller@11840000 {
		compatible = "starfive,jh7100-reset";
		reg = <0x0 0x11840000 0x0 0x10000>;
		#reset-cells = <1>;
		starfive,assert-offset = <0x0>;
		starfive,status-offset= <0x10>;
		starfive,nr-resets = <JH7100_RSTN_END>;
	};

arch/riscv/boot/dts/starfive/jh7110.dtsi:

	syscrg: syscrg@13020000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x13020000 0x0 0x10000>;

		syscrg_clk: clock-controller@13020000 {
			compatible = "starfive,jh7110-clkgen-sys";
			...
		};

		syscrg_rst: reset-controller@13020000 {
			compatible = "starfive,jh7110-reset";
			#reset-cells = <1>;
			starfive,assert-offset = <0x2F8>;
			starfive,status-offset= <0x308>;
			starfive,nr-resets = <JH7110_SYSRST_END>;
		};
	};

	aoncrg: aoncrg@17000000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x17000000 0x0 0x10000>;

		aoncrg_clk: clock-controller@17000000 {
			compatible = "starfive,jh7110-clkgen-aon";
			...
		};

		aoncrg_rst: reset-controller@17000000 {
			compatible = "starfive,jh7110-reset";
			#reset-cells = <1>;
			starfive,assert-offset = <0x38>;
			starfive,status-offset= <0x3C>;
			starfive,nr-resets = <JH7110_AONRST_END>;
		};
	};

	stgcrg: stgcrg@10230000 {	//Not submmited yet
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x10230000 0x0 0x10000>;

		stgcrg_clk: clock-controller@10230000 {
			compatible = "starfive,jh7110-clkgen-stg";
			...
		};

		stgcrg_rst: reset-controller@10230000 {
			compatible = "starfive,jh7110-reset";
			#reset-cells = <1>;
			starfive,assert-offset = <0x74>;
			starfive,status-offset= <0x78>;
			starfive,nr-resets = <JH7110_STGRST_END>;
		};
	};
	...

> 
> > +
> > +  starfive,nr-resets:
> > +    description: Number of reset signals
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> 
> Why do you need this? Most bindings don't. If just to validate 'resets' 
> args, then don't.

Can be removed. Instead, the reset driver should includes some related
binding headers or defines some macros for pointing out the number of
reset signals of each reset controller.

Best regards,
Hal

> 
> 
> > +
> > +required:
> > +  - compatible
> > +  - "#reset-cells"
> > +  - starfive,assert-offset
> > +  - starfive,status-offset
> > +  - starfive,nr-resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/reset/starfive-jh7110.h>
> > +
> > +    syscrg_rst: reset-controller@13020000 {
> > +        compatible = "starfive,jh7110-reset";
> > +        #reset-cells = <1>;
> > +        starfive,assert-offset = <0x2F8>;
> > +        starfive,status-offset= <0x308>;
> > +        starfive,nr-resets = <JH7110_SYSRST_END>;
> > +    };
> > +
> > +...
> > -- 
> > 2.17.1
> > 
> > 
>

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Krzysztof Kozlowski]

On 11/10/2022 11:30, Hal Feng wrote:
> On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
>> On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
>>> Add bindings for the reset controller on the JH7110 RISC-V
>>> SoC by StarFive Technology Ltd.
>>>
>>> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
>>> ---
>>>  .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
>>>  1 file changed, 54 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>> new file mode 100644
>>> index 000000000000..bb0010c200f9
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>> @@ -0,0 +1,54 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
>>> +
>>> +maintainers:
>>> +  - Emil Renner Berthing <kernel@esmil.dk>
>>> +  - Hal Feng <hal.feng@linux.starfivetech.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - starfive,jh7110-reset
>>
>> 'reg' needed? Is this a sub-block of something else?
> 
> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
> You might not see the complete patches at that time due to technical issue of
> our smtp email server. Again, I feel so sorry about that.
> 
> 	syscrg: syscrg@13020000 {
> 		compatible = "syscon", "simple-mfd";
> 		reg = <0x0 0x13020000 0x0 0x10000>;
> 
> 		syscrg_clk: clock-controller@13020000 {
> 			compatible = "starfive,jh7110-clkgen-sys";
> 			clocks = <&osc>, <&gmac1_rmii_refin>,
> 				 <&gmac1_rgmii_rxin>,
> 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> 				 <&tdm_ext>, <&mclk_ext>;
> 			clock-names = "osc", "gmac1_rmii_refin",
> 				"gmac1_rgmii_rxin",
> 				"i2stx_bclk_ext", "i2stx_lrck_ext",
> 				"i2srx_bclk_ext", "i2srx_lrck_ext",
> 				"tdm_ext", "mclk_ext";
> 			#clock-cells = <1>;
> 		};
> 
> 		syscrg_rst: reset-controller@13020000 {
> 			compatible = "starfive,jh7110-reset";
> 			#reset-cells = <1>;

So the answer to the "reg needed?" is what? You have unit address but no
reg, so this is not correct.

> 			starfive,assert-offset = <0x2F8>;
> 			starfive,status-offset= <0x308>;
> 			starfive,nr-resets = <JH7110_SYSRST_END>;
> 		};
> 	};
> 
> In this case, we get the memory mapped space through the parent node with syscon
> APIs. You can see patch 13 for detail.
> 
> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
> {


(...)

> 
>>
>>> +
>>> +  "#reset-cells":
>>> +    const: 1
>>> +
>>> +  starfive,assert-offset:
>>> +    description: Offset of the first ASSERT register
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +
>>> +  starfive,status-offset:
>>> +    description: Offset of the first STATUS register
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>
>> These can't be implied from the compatible string?
> 
> These two properties are the key differences among different reset controllers.

Different as in different compatibles? Please answer the questions...

> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> has different reset ASSERT/STATUS register offset and different number of reset
> signals. 

Then these are not exactly the same devices, so using one compatible for
them does not look correct.

> After storing them in dt, the reset driver can register all reset
> controllers with the same compatible string. 

Which is not how the compatible should be used...

> All we expect is that all reset
> controllers in a single SoC use the same compatible string for matching and the
> reset driver can be applied to all StarFive SoCs using different compatible strings.

Keep driver out of the talks.

> Just like

Existing bad pattern is not an argument to keep it going. Fix bad
patterns instead.

> 
> arch/riscv/boot/dts/starfive/jh7100.dtsi:
> 
> 	rstgen: reset-controller@11840000 {
> 		compatible = "starfive,jh7100-reset";
> 		reg = <0x0 0x11840000 0x0 0x10000>;
> 		#reset-cells = <1>;
> 		starfive,assert-offset = <0x0>;
> 		starfive,status-offset= <0x10>;
> 		starfive,nr-resets = <JH7100_RSTN_END>;
> 	};
> 
> arch/riscv/boot/dts/starfive/jh7110.dtsi:
> 
> 	syscrg: syscrg@13020000 {
> 		compatible = "syscon", "simple-mfd";
> 		reg = <0x0 0x13020000 0x0 0x10000>;
> 
> 		syscrg_clk: clock-controller@13020000 {
> 			compatible = "starfive,jh7110-clkgen-sys";
> 			...
> 		};
> 
> 		syscrg_rst: reset-controller@13020000 {
> 			compatible = "starfive,jh7110-reset";
> 			#reset-cells = <1>;
> 			starfive,assert-offset = <0x2F8>;
> 			starfive,status-offset= <0x308>;
> 			starfive,nr-resets = <JH7110_SYSRST_END>;
> 		};
> 	};
> 
> 	aoncrg: aoncrg@17000000 {
> 		compatible = "syscon", "simple-mfd";
> 		reg = <0x0 0x17000000 0x0 0x10000>;
> 
> 		aoncrg_clk: clock-controller@17000000 {
> 			compatible = "starfive,jh7110-clkgen-aon";
> 			...
> 		};
> 
> 		aoncrg_rst: reset-controller@17000000 {
> 			compatible = "starfive,jh7110-reset";
> 			#reset-cells = <1>;
> 			starfive,assert-offset = <0x38>;
> 			starfive,status-offset= <0x3C>;
> 			starfive,nr-resets = <JH7110_AONRST_END>;
> 		};
> 	};
> 
> 	stgcrg: stgcrg@10230000 {	//Not submmited yet
> 		compatible = "syscon", "simple-mfd";
> 		reg = <0x0 0x10230000 0x0 0x10000>;
> 
> 		stgcrg_clk: clock-controller@10230000 {
> 			compatible = "starfive,jh7110-clkgen-stg";
> 			...
> 		};
> 
> 		stgcrg_rst: reset-controller@10230000 {
> 			compatible = "starfive,jh7110-reset";
> 			#reset-cells = <1>;
> 			starfive,assert-offset = <0x74>;
> 			starfive,status-offset= <0x78>;
> 			starfive,nr-resets = <JH7110_STGRST_END>;
> 		};
> 	};
> 	...
> 
>>
>>> +
>>> +  starfive,nr-resets:
>>> +    description: Number of reset signals
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>
>> Why do you need this? Most bindings don't. If just to validate 'resets' 
>> args, then don't.
> 
> Can be removed. Instead, the reset driver should includes some related
> binding headers or defines some macros for pointing out the number of
> reset signals of each reset controller.
> 
> Best regards,
> Hal
> 
>>
>>
>>> +
>>> +required:
>>> +  - compatible
>>> +  - "#reset-cells"
>>> +  - starfive,assert-offset
>>> +  - starfive,status-offset
>>> +  - starfive,nr-resets
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/reset/starfive-jh7110.h>
>>> +
>>> +    syscrg_rst: reset-controller@13020000 {

Please test your patches.


Best regards,
Krzysztof

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Hal Feng]

On Tue, 11 Oct 2022 12:36:08 -0400, Krzysztof Kozlowski wrote:
> On 11/10/2022 11:30, Hal Feng wrote:
>> On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
>>> On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
>>>> Add bindings for the reset controller on the JH7110 RISC-V
>>>> SoC by StarFive Technology Ltd.
>>>>
>>>> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
>>>> ---
>>>>  .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
>>>>  1 file changed, 54 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>> new file mode 100644
>>>> index 000000000000..bb0010c200f9
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>>>> @@ -0,0 +1,54 @@
>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
>>>> +
>>>> +maintainers:
>>>> +  - Emil Renner Berthing <kernel@esmil.dk>
>>>> +  - Hal Feng <hal.feng@linux.starfivetech.com>
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    enum:
>>>> +      - starfive,jh7110-reset
>>>
>>> 'reg' needed? Is this a sub-block of something else?
>> 
>> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
>> You might not see the complete patches at that time due to technical issue of
>> our smtp email server. Again, I feel so sorry about that.
>> 
>> 	syscrg: syscrg@13020000 {
>> 		compatible = "syscon", "simple-mfd";
>> 		reg = <0x0 0x13020000 0x0 0x10000>;
>> 
>> 		syscrg_clk: clock-controller@13020000 {
>> 			compatible = "starfive,jh7110-clkgen-sys";
>> 			clocks = <&osc>, <&gmac1_rmii_refin>,
>> 				 <&gmac1_rgmii_rxin>,
>> 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>> 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>> 				 <&tdm_ext>, <&mclk_ext>;
>> 			clock-names = "osc", "gmac1_rmii_refin",
>> 				"gmac1_rgmii_rxin",
>> 				"i2stx_bclk_ext", "i2stx_lrck_ext",
>> 				"i2srx_bclk_ext", "i2srx_lrck_ext",
>> 				"tdm_ext", "mclk_ext";
>> 			#clock-cells = <1>;
>> 		};
>> 
>> 		syscrg_rst: reset-controller@13020000 {
>> 			compatible = "starfive,jh7110-reset";
>> 			#reset-cells = <1>;
> 
> So the answer to the "reg needed?" is what? You have unit address but no
> reg, so this is not correct.

Not needed in the reset-controller node, but needed in its parent node. I am sorry
for missing description to point it out in the bindings. I will rewrite all bindings
for the next version. Unit address here should be deleted.

> 
>> 			starfive,assert-offset = <0x2F8>;
>> 			starfive,status-offset= <0x308>;
>> 			starfive,nr-resets = <JH7110_SYSRST_END>;
>> 		};
>> 	};
>> 
>> In this case, we get the memory mapped space through the parent node with syscon
>> APIs. You can see patch 13 for detail.
>> 
>> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
>> {
> 
> 
> (...)
> 
>> 
>>>
>>>> +
>>>> +  "#reset-cells":
>>>> +    const: 1
>>>> +
>>>> +  starfive,assert-offset:
>>>> +    description: Offset of the first ASSERT register
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>> +
>>>> +  starfive,status-offset:
>>>> +    description: Offset of the first STATUS register
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>
>>> These can't be implied from the compatible string?

Definitely can. We do this is for simplifying the reset driver.
Otherwise, we may need to define more compatibles because there
are multiple reset blocks in JH7110. Another case can be found at
https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml

>> 
>> These two properties are the key differences among different reset controllers.
> 
> Different as in different compatibles? Please answer the questions..> 
>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
>> has different reset ASSERT/STATUS register offset and different number of reset
>> signals. 
> 
> Then these are not exactly the same devices, so using one compatible for
> them does not look correct.

One compatible can just be matched by one device? I think this is what
confuses me.

Best regards,
Hal

> 
>> After storing them in dt, the reset driver can register all reset
>> controllers with the same compatible string. 
> 
> Which is not how the compatible should be used...
> 
>> All we expect is that all reset
>> controllers in a single SoC use the same compatible string for matching and the
>> reset driver can be applied to all StarFive SoCs using different compatible strings.
> 
> Keep driver out of the talks.
> 
>> Just like
> 
> Existing bad pattern is not an argument to keep it going. Fix bad
> patterns instead.
> 
>> 
>> arch/riscv/boot/dts/starfive/jh7100.dtsi:
>> 
>> 	rstgen: reset-controller@11840000 {
>> 		compatible = "starfive,jh7100-reset";
>> 		reg = <0x0 0x11840000 0x0 0x10000>;
>> 		#reset-cells = <1>;
>> 		starfive,assert-offset = <0x0>;
>> 		starfive,status-offset= <0x10>;
>> 		starfive,nr-resets = <JH7100_RSTN_END>;
>> 	};
>> 
>> arch/riscv/boot/dts/starfive/jh7110.dtsi:
>> 
>> 	syscrg: syscrg@13020000 {
>> 		compatible = "syscon", "simple-mfd";
>> 		reg = <0x0 0x13020000 0x0 0x10000>;
>> 
>> 		syscrg_clk: clock-controller@13020000 {
>> 			compatible = "starfive,jh7110-clkgen-sys";
>> 			...
>> 		};
>> 
>> 		syscrg_rst: reset-controller@13020000 {
>> 			compatible = "starfive,jh7110-reset";
>> 			#reset-cells = <1>;
>> 			starfive,assert-offset = <0x2F8>;
>> 			starfive,status-offset= <0x308>;
>> 			starfive,nr-resets = <JH7110_SYSRST_END>;
>> 		};
>> 	};
>> 
>> 	aoncrg: aoncrg@17000000 {
>> 		compatible = "syscon", "simple-mfd";
>> 		reg = <0x0 0x17000000 0x0 0x10000>;
>> 
>> 		aoncrg_clk: clock-controller@17000000 {
>> 			compatible = "starfive,jh7110-clkgen-aon";
>> 			...
>> 		};
>> 
>> 		aoncrg_rst: reset-controller@17000000 {
>> 			compatible = "starfive,jh7110-reset";
>> 			#reset-cells = <1>;
>> 			starfive,assert-offset = <0x38>;
>> 			starfive,status-offset= <0x3C>;
>> 			starfive,nr-resets = <JH7110_AONRST_END>;
>> 		};
>> 	};
>> 
>> 	stgcrg: stgcrg@10230000 {	//Not submmited yet
>> 		compatible = "syscon", "simple-mfd";
>> 		reg = <0x0 0x10230000 0x0 0x10000>;
>> 
>> 		stgcrg_clk: clock-controller@10230000 {
>> 			compatible = "starfive,jh7110-clkgen-stg";
>> 			...
>> 		};
>> 
>> 		stgcrg_rst: reset-controller@10230000 {
>> 			compatible = "starfive,jh7110-reset";
>> 			#reset-cells = <1>;
>> 			starfive,assert-offset = <0x74>;
>> 			starfive,status-offset= <0x78>;
>> 			starfive,nr-resets = <JH7110_STGRST_END>;
>> 		};
>> 	};
>> 	...
>> 
>>>
>>>> +
>>>> +  starfive,nr-resets:
>>>> +    description: Number of reset signals
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>
>>> Why do you need this? Most bindings don't. If just to validate 'resets' 
>>> args, then don't.
>> 
>> Can be removed. Instead, the reset driver should includes some related
>> binding headers or defines some macros for pointing out the number of
>> reset signals of each reset controller.
>> 
>> Best regards,
>> Hal
>> 
>>>
>>>
>>>> +
>>>> +required:
>>>> +  - compatible
>>>> +  - "#reset-cells"
>>>> +  - starfive,assert-offset
>>>> +  - starfive,status-offset
>>>> +  - starfive,nr-resets
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> +  - |
>>>> +    #include <dt-bindings/reset/starfive-jh7110.h>
>>>> +
>>>> +    syscrg_rst: reset-controller@13020000 {
> 
> Please test your patches.
> 
> 
> Best regards,
> Krzysztof
> 
> 

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Krzysztof Kozlowski]

On 12/10/2022 09:16, Hal Feng wrote:
>>>>> +properties:
>>>>> +  compatible:
>>>>> +    enum:
>>>>> +      - starfive,jh7110-reset
>>>>
>>>> 'reg' needed? Is this a sub-block of something else?
>>>
>>> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
>>> You might not see the complete patches at that time due to technical issue of
>>> our smtp email server. Again, I feel so sorry about that.
>>>
>>> 	syscrg: syscrg@13020000 {
>>> 		compatible = "syscon", "simple-mfd";
>>> 		reg = <0x0 0x13020000 0x0 0x10000>;
>>>
>>> 		syscrg_clk: clock-controller@13020000 {
>>> 			compatible = "starfive,jh7110-clkgen-sys";
>>> 			clocks = <&osc>, <&gmac1_rmii_refin>,
>>> 				 <&gmac1_rgmii_rxin>,
>>> 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>>> 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>>> 				 <&tdm_ext>, <&mclk_ext>;
>>> 			clock-names = "osc", "gmac1_rmii_refin",
>>> 				"gmac1_rgmii_rxin",
>>> 				"i2stx_bclk_ext", "i2stx_lrck_ext",
>>> 				"i2srx_bclk_ext", "i2srx_lrck_ext",
>>> 				"tdm_ext", "mclk_ext";
>>> 			#clock-cells = <1>;
>>> 		};
>>>
>>> 		syscrg_rst: reset-controller@13020000 {
>>> 			compatible = "starfive,jh7110-reset";
>>> 			#reset-cells = <1>;
>>
>> So the answer to the "reg needed?" is what? You have unit address but no
>> reg, so this is not correct.
> 
> Not needed in the reset-controller node, but needed in its parent node. 

We do not talk about parent node. Rob's question was in this bindings.
Is this document a binding for the parent node or for this node?

> I am sorry
> for missing description to point it out in the bindings. I will rewrite all bindings
> for the next version. Unit address here should be deleted.
> 
>>
>>> 			starfive,assert-offset = <0x2F8>;
>>> 			starfive,status-offset= <0x308>;
>>> 			starfive,nr-resets = <JH7110_SYSRST_END>;
>>> 		};
>>> 	};
>>>
>>> In this case, we get the memory mapped space through the parent node with syscon
>>> APIs. You can see patch 13 for detail.
>>>
>>> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
>>> {
>>
>>
>> (...)
>>
>>>
>>>>
>>>>> +
>>>>> +  "#reset-cells":
>>>>> +    const: 1
>>>>> +
>>>>> +  starfive,assert-offset:
>>>>> +    description: Offset of the first ASSERT register
>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>> +
>>>>> +  starfive,status-offset:
>>>>> +    description: Offset of the first STATUS register
>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>
>>>> These can't be implied from the compatible string?
> 
> Definitely can. We do this is for simplifying the reset driver.

The role of the bindings is not to simplify some specific driver in some
specific OS...

> Otherwise, we may need to define more compatibles because there
> are multiple reset blocks in JH7110. Another case can be found at
> https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml

And why is this a problem? You have different hardware, so should have
different compatibles. Otherwise we would have a compatible
"all,everything" and use it in all possible devices.

>>> These two properties are the key differences among different reset controllers.
>>
>> Different as in different compatibles? Please answer the questions..> 
>>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
>>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
>>> has different reset ASSERT/STATUS register offset and different number of reset
>>> signals. 
>>
>> Then these are not exactly the same devices, so using one compatible for
>> them does not look correct.
> 
> One compatible can just be matched by one device? I think this is what
> confuses me.

I don't understand the question.

> 
> Best regards,
> Hal
> 

Trim the replies - no need to quote everything (entire message following
last reply/quote).

Best regards,
Krzysztof

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Conor Dooley]

Hey Hal Feng,

On Wed, Oct 12, 2022 at 09:33:42AM -0400, Krzysztof Kozlowski wrote:
> >>> These two properties are the key differences among different reset controllers.
> >>
> >> Different as in different compatibles? Please answer the questions..> 
> >>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> >>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> >>> has different reset ASSERT/STATUS register offset and different number of reset
> >>> signals. 
> >>
> >> Then these are not exactly the same devices, so using one compatible for
> >> them does not look correct.
> > 
> > One compatible can just be matched by one device? I think this is what
> > confuses me.
> 
> I don't understand the question.

If two SoCs have exactly the same device/peripheral then they _can_ use
the same compatible. If they share some common, viable feature-set then
one can "fall back" to the other depending on what your Venn diagram of
common features looks like. I've not been following this too closely,
but I think what Krzysztof is suggesting is that you have a jh7100 and
a jh7110 compatible. Then in your driver you just "know" that if you
match against jh7110 which values to use for register offsets & vice
versa for a match against the jh7100. There's many examples over the
tree for how to handle this sort of thing rather than including it in
the devicetree.

Maybe Rob and Krzysztof will scream at me for this description, but
devicetree is about how periperhals etc are connected together in the
system not about the internals of a given peripheral.

Following that logic, the devicetree should not contain register offsets
etc that are a known quanitity once you've determined that you are running
on vendor,soc-foo.

Hopefully that helps with your confusion somewhat?
Conor.

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Hal Feng]

On Wed, 12 Oct 2022 15:05:04 +0100, Conor Dooley wrote:
> Hey Hal Feng,
> 
> On Wed, Oct 12, 2022 at 09:33:42AM -0400, Krzysztof Kozlowski wrote:
> > >>> These two properties are the key differences among different reset controllers.
> > >>
> > >> Different as in different compatibles? Please answer the questions..> 
> > >>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> > >>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> > >>> has different reset ASSERT/STATUS register offset and different number of reset
> > >>> signals. 
> > >>
> > >> Then these are not exactly the same devices, so using one compatible for
> > >> them does not look correct.
> > > 
> > > One compatible can just be matched by one device? I think this is what
> > > confuses me.
> > 
> > I don't understand the question.
> 
> If two SoCs have exactly the same device/peripheral then they _can_ use
> the same compatible. If they share some common, viable feature-set then
> one can "fall back" to the other depending on what your Venn diagram of
> common features looks like. I've not been following this too closely,
> but I think what Krzysztof is suggesting is that you have a jh7100 and
> a jh7110 compatible. Then in your driver you just "know" that if you
> match against jh7110 which values to use for register offsets & vice
> versa for a match against the jh7100. There's many examples over the
> tree for how to handle this sort of thing rather than including it in
> the devicetree.
> 
> Maybe Rob and Krzysztof will scream at me for this description, but
> devicetree is about how periperhals etc are connected together in the
> system not about the internals of a given peripheral.
> 
> Following that logic, the devicetree should not contain register offsets
> etc that are a known quanitity once you've determined that you are running
> on vendor,soc-foo.
> 
> Hopefully that helps with your confusion somewhat?
> Conor.

Yes, anyway, thank you for the detailed reply.

Best regards,
Hal

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Hal Feng]

On Wed, 12 Oct 2022 09:33:42 -0400, Krzysztof Kozlowski wrote:
> On 12/10/2022 09:16, Hal Feng wrote:
>>>>>> +properties:
>>>>>> +  compatible:
>>>>>> +    enum:
>>>>>> +      - starfive,jh7110-reset
>>>>>
>>>>> 'reg' needed? Is this a sub-block of something else?
>>>>
>>>> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
>>>> You might not see the complete patches at that time due to technical issue of
>>>> our smtp email server. Again, I feel so sorry about that.
>>>>
>>>> 	syscrg: syscrg@13020000 {
>>>> 		compatible = "syscon", "simple-mfd";
>>>> 		reg = <0x0 0x13020000 0x0 0x10000>;
>>>>
>>>> 		syscrg_clk: clock-controller@13020000 {
>>>> 			compatible = "starfive,jh7110-clkgen-sys";
>>>> 			clocks = <&osc>, <&gmac1_rmii_refin>,
>>>> 				 <&gmac1_rgmii_rxin>,
>>>> 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>>>> 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>>>> 				 <&tdm_ext>, <&mclk_ext>;
>>>> 			clock-names = "osc", "gmac1_rmii_refin",
>>>> 				"gmac1_rgmii_rxin",
>>>> 				"i2stx_bclk_ext", "i2stx_lrck_ext",
>>>> 				"i2srx_bclk_ext", "i2srx_lrck_ext",
>>>> 				"tdm_ext", "mclk_ext";
>>>> 			#clock-cells = <1>;
>>>> 		};
>>>>
>>>> 		syscrg_rst: reset-controller@13020000 {
>>>> 			compatible = "starfive,jh7110-reset";
>>>> 			#reset-cells = <1>;
>>>
>>> So the answer to the "reg needed?" is what? You have unit address but no
>>> reg, so this is not correct.
>> 
>> Not needed in the reset-controller node, but needed in its parent node. 
> 
> We do not talk about parent node. Rob's question was in this bindings.
> Is this document a binding for the parent node or for this node?

This node. So not needed.

> 
>> I am sorry
>> for missing description to point it out in the bindings. I will rewrite all bindings
>> for the next version. Unit address here should be deleted.
>> 
>>>
>>>> 			starfive,assert-offset = <0x2F8>;
>>>> 			starfive,status-offset= <0x308>;
>>>> 			starfive,nr-resets = <JH7110_SYSRST_END>;
>>>> 		};
>>>> 	};
>>>>
>>>> In this case, we get the memory mapped space through the parent node with syscon
>>>> APIs. You can see patch 13 for detail.
>>>>
>>>> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
>>>> {
>>>
>>>
>>> (...)
>>>
>>>>
>>>>>
>>>>>> +
>>>>>> +  "#reset-cells":
>>>>>> +    const: 1
>>>>>> +
>>>>>> +  starfive,assert-offset:
>>>>>> +    description: Offset of the first ASSERT register
>>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>>> +
>>>>>> +  starfive,status-offset:
>>>>>> +    description: Offset of the first STATUS register
>>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>>
>>>>> These can't be implied from the compatible string?
>> 
>> Definitely can. We do this is for simplifying the reset driver.
> 
> The role of the bindings is not to simplify some specific driver in some
> specific OS...
> 
>> Otherwise, we may need to define more compatibles because there
>> are multiple reset blocks in JH7110. Another case can be found at
>> https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml
> 
> And why is this a problem? You have different hardware, so should have
> different compatibles. Otherwise we would have a compatible
> "all,everything" and use it in all possible devices.

Okay, I get it. Thanks a lot.

Best regards,
Hal

Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings

[Emil Renner Berthing]

On Tue, 11 Oct 2022 at 18:21, Hal Feng <hal.feng@linux.starfivetech.com> wrote:
>
> On Thu, 29 Sep 2022 13:43:49 -0500, Rob Herring wrote:
> > On Fri, Sep 30, 2022 at 01:51:47AM +0800, Hal Feng wrote:
> > > Add bindings for the reset controller on the JH7110 RISC-V
> > > SoC by StarFive Technology Ltd.
> > >
> > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > > ---
> > >  .../bindings/reset/starfive,jh7110-reset.yaml | 54 +++++++++++++++++++
> > >  1 file changed, 54 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > > new file mode 100644
> > > index 000000000000..bb0010c200f9
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
> > > @@ -0,0 +1,54 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings
> > > +
> > > +maintainers:
> > > +  - Emil Renner Berthing <kernel@esmil.dk>
> > > +  - Hal Feng <hal.feng@linux.starfivetech.com>
> > > +
> > > +properties:
> > > +  compatible:
> > > +    enum:
> > > +      - starfive,jh7110-reset
> >
> > 'reg' needed? Is this a sub-block of something else?
>
> Yes, the reset node is a child node of the syscon node, see patch 27 for detail.
> You might not see the complete patches at that time due to technical issue of
> our smtp email server. Again, I feel so sorry about that.
>
>         syscrg: syscrg@13020000 {
>                 compatible = "syscon", "simple-mfd";
>                 reg = <0x0 0x13020000 0x0 0x10000>;
>
>                 syscrg_clk: clock-controller@13020000 {
>                         compatible = "starfive,jh7110-clkgen-sys";
>                         clocks = <&osc>, <&gmac1_rmii_refin>,
>                                  <&gmac1_rgmii_rxin>,
>                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>                                  <&tdm_ext>, <&mclk_ext>;
>                         clock-names = "osc", "gmac1_rmii_refin",
>                                 "gmac1_rgmii_rxin",
>                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
>                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
>                                 "tdm_ext", "mclk_ext";
>                         #clock-cells = <1>;
>                 };
>
>                 syscrg_rst: reset-controller@13020000 {
>                         compatible = "starfive,jh7110-reset";
>                         #reset-cells = <1>;
>                         starfive,assert-offset = <0x2F8>;
>                         starfive,status-offset= <0x308>;
>                         starfive,nr-resets = <JH7110_SYSRST_END>;
>                 };
>         };
>
> In this case, we get the memory mapped space through the parent node with syscon
> APIs. You can see patch 13 for detail.
>
> static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
> {
>         struct starfive_reset *data;
>         int ret;
>
>         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
>         if (!data)
>                 return -ENOMEM;
>
>         data->regmap = device_node_to_regmap(pdev->dev.of_node);                  //for JH7100
>         if (IS_ERR(data->regmap)) {
>                 data->regmap = syscon_node_to_regmap(pdev->dev.of_node->parent);  //for JH7110
>                 if (IS_ERR(data->regmap)) {
>                         dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
>                                 PTR_ERR(data->regmap));
>                         return PTR_ERR(data->regmap);
>                 }
>         }
>         ...
> }
>
> We use this method to avoid errors when remapping the same address in two
> different drivers, because clock and reset of StarFive JH7110 share a common
> register address region. For similar implementation, refer to file [1] and [2].
>
> [1] arch/riscv/boot/dts/canaan/k210.dtsi
>
>         sysctl: syscon@50440000 {
>                 compatible = "canaan,k210-sysctl",
>                              "syscon", "simple-mfd";
>                 reg = <0x50440000 0x100>;
>                 clocks = <&sysclk K210_CLK_APB1>;
>                 clock-names = "pclk";
>
>                 sysclk: clock-controller {
>                         #clock-cells = <1>;
>                         compatible = "canaan,k210-clk";
>                         clocks = <&in0>;
>                 };
>
>                 sysrst: reset-controller {
>                         compatible = "canaan,k210-rst";
>                         #reset-cells = <1>;
>                 };
>
>                 reboot: syscon-reboot {
>                         compatible = "syscon-reboot";
>                         regmap = <&sysctl>;
>                         offset = <48>;
>                         mask = <1>;
>                         value = <1>;
>                 };
>         };
>
> [2] drivers/reset/reset-k210.c

Here the syscon makes a little more sense since the same memory area
does at least 3 different things, but on the JH7110 it is a dedicated
"clock and reset generator", CRG. So this is much better modelled with
a single driver taking care of both the clock and resets like the
original driver did. If you do

git grep reset_controller_register drivers/clk

..you can see that there are lots of other drivers for such
peripherals that combine clock and reset.

> >
> > > +
> > > +  "#reset-cells":
> > > +    const: 1
> > > +
> > > +  starfive,assert-offset:
> > > +    description: Offset of the first ASSERT register
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > +  starfive,status-offset:
> > > +    description: Offset of the first STATUS register
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> >
> > These can't be implied from the compatible string?
>
> These two properties are the key differences among different reset controllers.
> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> has different reset ASSERT/STATUS register offset and different number of reset
> signals. After storing them in dt, the reset driver can register all reset
> controllers with the same compatible string. All we expect is that all reset
> controllers in a single SoC use the same compatible string for matching and the
> reset driver can be applied to all StarFive SoCs using different compatible strings.
> Just like
>
> arch/riscv/boot/dts/starfive/jh7100.dtsi:
>
>         rstgen: reset-controller@11840000 {
>                 compatible = "starfive,jh7100-reset";
>                 reg = <0x0 0x11840000 0x0 0x10000>;
>                 #reset-cells = <1>;
>                 starfive,assert-offset = <0x0>;
>                 starfive,status-offset= <0x10>;
>                 starfive,nr-resets = <JH7100_RSTN_END>;
>         };
>
> arch/riscv/boot/dts/starfive/jh7110.dtsi:
>
>         syscrg: syscrg@13020000 {
>                 compatible = "syscon", "simple-mfd";
>                 reg = <0x0 0x13020000 0x0 0x10000>;
>
>                 syscrg_clk: clock-controller@13020000 {
>                         compatible = "starfive,jh7110-clkgen-sys";
>                         ...
>                 };
>
>                 syscrg_rst: reset-controller@13020000 {
>                         compatible = "starfive,jh7110-reset";
>                         #reset-cells = <1>;
>                         starfive,assert-offset = <0x2F8>;
>                         starfive,status-offset= <0x308>;
>                         starfive,nr-resets = <JH7110_SYSRST_END>;
>                 };
>         };
>
>         aoncrg: aoncrg@17000000 {
>                 compatible = "syscon", "simple-mfd";
>                 reg = <0x0 0x17000000 0x0 0x10000>;
>
>                 aoncrg_clk: clock-controller@17000000 {
>                         compatible = "starfive,jh7110-clkgen-aon";
>                         ...
>                 };
>
>                 aoncrg_rst: reset-controller@17000000 {
>                         compatible = "starfive,jh7110-reset";
>                         #reset-cells = <1>;
>                         starfive,assert-offset = <0x38>;
>                         starfive,status-offset= <0x3C>;
>                         starfive,nr-resets = <JH7110_AONRST_END>;
>                 };
>         };
>
>         stgcrg: stgcrg@10230000 {       //Not submmited yet
>                 compatible = "syscon", "simple-mfd";
>                 reg = <0x0 0x10230000 0x0 0x10000>;
>
>                 stgcrg_clk: clock-controller@10230000 {
>                         compatible = "starfive,jh7110-clkgen-stg";
>                         ...
>                 };
>
>                 stgcrg_rst: reset-controller@10230000 {
>                         compatible = "starfive,jh7110-reset";
>                         #reset-cells = <1>;
>                         starfive,assert-offset = <0x74>;
>                         starfive,status-offset= <0x78>;
>                         starfive,nr-resets = <JH7110_STGRST_END>;
>                 };
>         };
>         ...
>
> >
> > > +
> > > +  starfive,nr-resets:
> > > +    description: Number of reset signals
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> >
> > Why do you need this? Most bindings don't. If just to validate 'resets'
> > args, then don't.
>
> Can be removed. Instead, the reset driver should includes some related
> binding headers or defines some macros for pointing out the number of
> reset signals of each reset controller.
>
> Best regards,
> Hal
>
> >
> >
> > > +
> > > +required:
> > > +  - compatible
> > > +  - "#reset-cells"
> > > +  - starfive,assert-offset
> > > +  - starfive,status-offset
> > > +  - starfive,nr-resets
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/reset/starfive-jh7110.h>
> > > +
> > > +    syscrg_rst: reset-controller@13020000 {
> > > +        compatible = "starfive,jh7110-reset";
> > > +        #reset-cells = <1>;
> > > +        starfive,assert-offset = <0x2F8>;
> > > +        starfive,status-offset= <0x308>;
> > > +        starfive,nr-resets = <JH7110_SYSRST_END>;
> > > +    };
> > > +
> > > +...
> > > --
> > > 2.17.1
> > >
> > >
> >
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v1 13/30] reset: starfive: Add StarFive JH7110 SoC support

[Hal Feng]

Make the driver be compatible with StarFive JH7110 SoC.
Note that the register base address of clock controller is the
same with the reset controller one. So we store the property
'reg' in the parent node of node 'reset-controller' and use
syscon APIs to get regmap structure.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 drivers/reset/reset-starfive.c | 35 +++++++++++++++++++++++++++-------
 1 file changed, 28 insertions(+), 7 deletions(-)

diff --git a/drivers/reset/reset-starfive.c b/drivers/reset/reset-starfive.c
index 56d07bafadd7..a953fed711fd 100644
--- a/drivers/reset/reset-starfive.c
+++ b/drivers/reset/reset-starfive.c
@@ -8,7 +8,7 @@
 
 #include <linux/mfd/syscon.h>
 #include <linux/of.h>
-#include <linux/platform_device.h>
+#include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
 
@@ -134,7 +134,7 @@ static const struct reset_control_ops starfive_reset_ops = {
 	.status		= starfive_reset_status,
 };
 
-static int __init starfive_reset_probe(struct platform_device *pdev)
+static int reset_starfive_register(struct platform_device *pdev, const u32 *asserted)
 {
 	struct starfive_reset *data;
 	int ret;
@@ -145,9 +145,12 @@ static int __init starfive_reset_probe(struct platform_device *pdev)
 
 	data->regmap = device_node_to_regmap(pdev->dev.of_node);
 	if (IS_ERR(data->regmap)) {
-		dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
-			PTR_ERR(data->regmap));
-		return PTR_ERR(data->regmap);
+		data->regmap = syscon_node_to_regmap(pdev->dev.of_node->parent);
+		if (IS_ERR(data->regmap)) {
+			dev_err(&pdev->dev, "failed to get regmap (error %ld)\n",
+				PTR_ERR(data->regmap));
+			return PTR_ERR(data->regmap);
+		}
 	}
 
 	ret = of_property_read_u32(pdev->dev.of_node, "starfive,assert-offset",
@@ -177,16 +180,34 @@ static int __init starfive_reset_probe(struct platform_device *pdev)
 	data->rcdev.dev = &pdev->dev;
 	data->rcdev.of_node = pdev->dev.of_node;
 
-	data->asserted = jh7100_reset_asserted;
+	data->asserted = asserted;
 
 	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
 }
 
 static const struct of_device_id starfive_reset_dt_ids[] = {
-	{ .compatible = "starfive,jh7100-reset" },
+	{
+		.compatible = "starfive,jh7100-reset",
+		.data = jh7100_reset_asserted,
+	},
+	{
+		.compatible = "starfive,jh7110-reset",
+		.data = NULL,
+	},
 	{ /* sentinel */ }
 };
 
+static int __init starfive_reset_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+
+	match = of_match_device(starfive_reset_dt_ids, &pdev->dev);
+	if (!match)
+		return -EINVAL;
+
+	return reset_starfive_register(pdev, (u32 *)(match->data));
+}
+
 static struct platform_driver starfive_reset_driver = {
 	.driver = {
 		.name = "starfive-reset",
-- 
2.17.1

[PATCH v1 14/30] clk: starfive: Factor out common clock driver code

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

The clock control registers on the StarFive SoCs work identically,
so factor out the code then drivers for different SoCs can share
it without depending on each other. No functional change.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 MAINTAINERS                                   |   9 +-
 drivers/clk/starfive/Kconfig                  |   7 +-
 drivers/clk/starfive/Makefile                 |   3 +-
 .../clk/starfive/clk-starfive-jh7100-audio.c  | 127 +--
 drivers/clk/starfive/clk-starfive-jh7100.c    | 825 ++++++------------
 drivers/clk/starfive/clk-starfive-jh7100.h    | 112 ---
 drivers/clk/starfive/clk-starfive.c           | 333 +++++++
 drivers/clk/starfive/clk-starfive.h           | 114 +++
 8 files changed, 779 insertions(+), 751 deletions(-)
 delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
 create mode 100644 drivers/clk/starfive/clk-starfive.c
 create mode 100644 drivers/clk/starfive/clk-starfive.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f2319a3b708b..70d64d2afb0c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19396,12 +19396,13 @@ M:	Ion Badulescu <ionut@badula.org>
 S:	Odd Fixes
 F:	drivers/net/ethernet/adaptec/starfire*
 
-STARFIVE JH7100 CLOCK DRIVERS
+STARFIVE CLOCK DRIVERS
 M:	Emil Renner Berthing <kernel@esmil.dk>
+M:	Xingyu Wu <xingyu.wu@linux.starfivetech.com>
 S:	Maintained
-F:	Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
-F:	drivers/clk/starfive/clk-starfive-jh7100*
-F:	include/dt-bindings/clock/starfive-jh7100*.h
+F:	Documentation/devicetree/bindings/clock/starfive*
+F:	drivers/clk/starfive/
+F:	include/dt-bindings/clock/starfive*
 
 STARFIVE JH7100 PINCTRL DRIVER
 M:	Emil Renner Berthing <kernel@esmil.dk>
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 003bd2d56ce7..4ff61eb941c8 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -1,8 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0
 
+config CLK_STARFIVE
+	bool
+
 config CLK_STARFIVE_JH7100
 	bool "StarFive JH7100 clock support"
 	depends on SOC_STARFIVE || COMPILE_TEST
+	select CLK_STARFIVE
 	default SOC_STARFIVE
 	help
 	  Say yes here to support the clock controller on the StarFive JH7100
@@ -10,7 +14,8 @@ config CLK_STARFIVE_JH7100
 
 config CLK_STARFIVE_JH7100_AUDIO
 	tristate "StarFive JH7100 audio clock support"
-	depends on CLK_STARFIVE_JH7100
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select CLK_STARFIVE
 	default m if SOC_STARFIVE
 	help
 	  Say Y or M here to support the audio clocks on the StarFive JH7100
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 0fa8ecb9ec1c..ddd04595516f 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
-# StarFive Clock
+obj-$(CONFIG_CLK_STARFIVE)	+= clk-starfive.o
+
 obj-$(CONFIG_CLK_STARFIVE_JH7100)	+= clk-starfive-jh7100.o
 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)	+= clk-starfive-jh7100-audio.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 8473a65e219b..41389cacfe03 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -16,7 +16,7 @@
 
 #include <dt-bindings/clock/starfive-jh7100-audio.h>
 
-#include "clk-starfive-jh7100.h"
+#include "clk-starfive.h"
 
 /* external clocks */
 #define JH7100_AUDCLK_AUDIO_SRC			(JH7100_AUDCLK_END + 0)
@@ -28,66 +28,68 @@
 #define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD	(JH7100_AUDCLK_END + 6)
 #define JH7100_AUDCLK_VAD_INTMEM                (JH7100_AUDCLK_END + 7)
 
-static const struct jh7100_clk_data jh7100_audclk_data[] = {
-	JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
-		    JH7100_AUDCLK_AUDIO_SRC,
-		    JH7100_AUDCLK_AUDIO_12288),
-	JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
-		    JH7100_AUDCLK_AUDIO_SRC,
-		    JH7100_AUDCLK_AUDIO_12288),
-	JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
-		    JH7100_AUDCLK_ADC_MCLK,
-		    JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
-	JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
-	JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
-		    JH7100_AUDCLK_I2SADC_BCLK_N,
-		    JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
-		    JH7100_AUDCLK_I2SADC_BCLK),
-	JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
-		    JH7100_AUDCLK_AUDIO_SRC,
-		    JH7100_AUDCLK_AUDIO_12288),
-	JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
-		    JH7100_AUDCLK_AUDIO_SRC,
-		    JH7100_AUDCLK_AUDIO_12288),
-	JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
-		    JH7100_AUDCLK_AUDIO_SRC,
-		    JH7100_AUDCLK_AUDIO_12288),
-	JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
-		    JH7100_AUDCLK_DAC_MCLK,
-		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
-	JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
-	JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
-		    JH7100_AUDCLK_I2S1_MCLK,
-		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
-	JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
-		    JH7100_AUDCLK_I2S1_MCLK,
-		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
-	JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
-	JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
-		    JH7100_AUDCLK_I2S1_BCLK_N,
-		    JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
-	JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
-	JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
-	JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
-	JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
-	JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
-	JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
-	JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
-	JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
-		    JH7100_AUDCLK_VAD_INTMEM,
-		    JH7100_AUDCLK_AUDIO_12288),
+static const struct starfive_clk_data jh7100_audclk_data[] = {
+	STARFIVE__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
+		      JH7100_AUDCLK_AUDIO_SRC,
+		      JH7100_AUDCLK_AUDIO_12288),
+	STARFIVE__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
+		      JH7100_AUDCLK_AUDIO_SRC,
+		      JH7100_AUDCLK_AUDIO_12288),
+	STARFIVE_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
+		      JH7100_AUDCLK_ADC_MCLK,
+		      JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
+	STARFIVE__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
+	STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
+		      JH7100_AUDCLK_I2SADC_BCLK_N,
+		      JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
+		      JH7100_AUDCLK_I2SADC_BCLK),
+	STARFIVE_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
+		      JH7100_AUDCLK_AUDIO_SRC,
+		      JH7100_AUDCLK_AUDIO_12288),
+	STARFIVE_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
+		      JH7100_AUDCLK_AUDIO_SRC,
+		      JH7100_AUDCLK_AUDIO_12288),
+	STARFIVE_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
+		      JH7100_AUDCLK_AUDIO_SRC,
+		      JH7100_AUDCLK_AUDIO_12288),
+	STARFIVE_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
+		      JH7100_AUDCLK_DAC_MCLK,
+		      JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+	STARFIVE__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
+	STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
+		      JH7100_AUDCLK_I2S1_MCLK,
+		      JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+	STARFIVE_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
+		      JH7100_AUDCLK_I2S1_MCLK,
+		      JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+	STARFIVE__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
+	STARFIVE_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
+		      JH7100_AUDCLK_I2S1_BCLK_N,
+		      JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
+	STARFIVE_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
+	STARFIVE__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+	STARFIVE_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
+	STARFIVE_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
+	STARFIVE_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4,
+		      JH7100_AUDCLK_USB_APB),
+	STARFIVE_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3,
+		      JH7100_AUDCLK_USB_APB),
+	STARFIVE__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+	STARFIVE__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
+		      JH7100_AUDCLK_VAD_INTMEM,
+		      JH7100_AUDCLK_AUDIO_12288),
 };
 
 static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
 {
-	struct jh7100_clk_priv *priv = data;
+	struct starfive_clk_priv *priv = data;
 	unsigned int idx = clkspec->args[0];
 
 	if (idx < JH7100_AUDCLK_END)
@@ -98,7 +100,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d
 
 static int jh7100_audclk_probe(struct platform_device *pdev)
 {
-	struct jh7100_clk_priv *priv;
+	struct starfive_clk_priv *priv;
 	unsigned int idx;
 	int ret;
 
@@ -117,12 +119,13 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
 		struct clk_parent_data parents[4] = {};
 		struct clk_init_data init = {
 			.name = jh7100_audclk_data[idx].name,
-			.ops = starfive_jh7100_clk_ops(max),
+			.ops = starfive_clk_ops(max),
 			.parent_data = parents,
-			.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+			.num_parents =
+				((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
 			.flags = jh7100_audclk_data[idx].flags,
 		};
-		struct jh7100_clk *clk = &priv->reg[idx];
+		struct starfive_clk *clk = &priv->reg[idx];
 		unsigned int i;
 
 		for (i = 0; i < init.num_parents; i++) {
@@ -140,7 +143,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
 
 		clk->hw.init = &init;
 		clk->idx = idx;
-		clk->max_div = max & JH7100_CLK_DIV_MASK;
+		clk->max_div = max & STARFIVE_CLK_DIV_MASK;
 
 		ret = devm_clk_hw_register(priv->dev, &clk->hw);
 		if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 691aeebc7092..014e36f17595 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -7,20 +7,15 @@
  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
  */
 
-#include <linux/bits.h>
 #include <linux/clk-provider.h>
-#include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
 #include <linux/mod_devicetable.h>
-#include <linux/module.h>
 #include <linux/platform_device.h>
 
 #include <dt-bindings/clock/starfive-jh7100.h>
 
-#include "clk-starfive-jh7100.h"
+#include "clk-starfive.h"
 
 /* external clocks */
 #define JH7100_CLK_OSC_SYS		(JH7100_CLK_END + 0)
@@ -28,570 +23,257 @@
 #define JH7100_CLK_GMAC_RMII_REF	(JH7100_CLK_END + 2)
 #define JH7100_CLK_GMAC_GR_MII_RX	(JH7100_CLK_END + 3)
 
-static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
-	JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL0_OUT,
-		    JH7100_CLK_PLL1_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL1_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL0_OUT,
-		    JH7100_CLK_PLL1_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL0_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL0_OUT),
-	JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL1_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
-		    JH7100_CLK_OSC_AUD,
-		    JH7100_CLK_PLL0_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
-	JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL1_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_PLL0_OUT,
-		    JH7100_CLK_PLL1_OUT),
-	JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
-		    JH7100_CLK_OSC_AUD,
-		    JH7100_CLK_PLL0_OUT,
-		    JH7100_CLK_PLL2_OUT),
-	JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
-	JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
-	JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
-	JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
-	JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
-	JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
-	JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_OSC_AUD),
-	JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
-	JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
-	JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
-	JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
-	JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
-	JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
-	JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
-	JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
-	JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
-	JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
-	JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
-	JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
-	JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
-	JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
-	JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
-	JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
-	JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
-	JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
-	JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
-	JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
-	JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
-	JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
-	JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
-	JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
-	JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
-	JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
-	JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
-	JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
-	JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
-	JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
-	JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
-	JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
-	JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
-	JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
-	JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
-	JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
-	JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
-		    JH7100_CLK_DDROSC_DIV2,
-		    JH7100_CLK_DDRPLL_DIV2,
-		    JH7100_CLK_DDRPLL_DIV4,
-		    JH7100_CLK_DDRPLL_DIV8),
-	JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
-		    JH7100_CLK_DDROSC_DIV2,
-		    JH7100_CLK_DDRPLL_DIV2,
-		    JH7100_CLK_DDRPLL_DIV4,
-		    JH7100_CLK_DDRPLL_DIV8),
-	JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
-	JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
-	JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
-		    JH7100_CLK_CPU_AXI,
-		    JH7100_CLK_NNEBUS_SRC1),
-	JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
-	JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
-	JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
-	JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
-	JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
-	JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
-	JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
-	JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
-	JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
-	JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
-	JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
-	JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
-	JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
-	JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
-	JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
-	JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
-	JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
-	JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
-	JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
-		    JH7100_CLK_OSC_SYS,
-		    JH7100_CLK_USBPHY_PLLDIV25M),
-	JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
-	JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
-	JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
-	JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
-	JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
-	JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
-	JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
-	JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
-	JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
-	JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
-	JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
-	JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
-	JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
-	JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
-	JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
-	JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
-	JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
-	JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
-	JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
-	JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
-	JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
-	JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
-	JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
-	JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
-	JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
-	JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
-	JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
-	JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
-	JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
-		    JH7100_CLK_GMAC_GTX,
-		    JH7100_CLK_GMAC_TX_INV,
-		    JH7100_CLK_GMAC_RMII_TX),
-	JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
-	JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
-		    JH7100_CLK_GMAC_GR_MII_RX,
-		    JH7100_CLK_GMAC_RMII_RX),
-	JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
-	JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
-	JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
-	JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
-	JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
-	JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
-	JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
-	JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
-	JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
-	JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
-	JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
-	JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
-	JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
-	JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
-	JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
-	JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
-	JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
-	JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
-	JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
+static const struct starfive_clk_data jh7100_clk_data[] __initconst = {
+	STARFIVE__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL0_OUT,
+		      JH7100_CLK_PLL1_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL1_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL0_OUT,
+		      JH7100_CLK_PLL1_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL0_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL0_OUT),
+	STARFIVE__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL1_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
+		      JH7100_CLK_OSC_AUD,
+		      JH7100_CLK_PLL0_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
+	STARFIVE__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL1_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_PLL0_OUT,
+		      JH7100_CLK_PLL1_OUT),
+	STARFIVE__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
+		      JH7100_CLK_OSC_AUD,
+		      JH7100_CLK_PLL0_OUT,
+		      JH7100_CLK_PLL2_OUT),
+	STARFIVE__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
+	STARFIVE__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
+	STARFIVE__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
+	STARFIVE__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
+	STARFIVE_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
+	STARFIVE_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
+	STARFIVE__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_OSC_AUD),
+	STARFIVE__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
+	STARFIVE__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
+	STARFIVE__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
+	STARFIVE_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+	STARFIVE_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+	STARFIVE_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
+	STARFIVE_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
+	STARFIVE_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
+	STARFIVE_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL,
+		      JH7100_CLK_OSC_SYS),
+	STARFIVE_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
+	STARFIVE_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
+	STARFIVE_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
+	STARFIVE_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
+	STARFIVE_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
+	STARFIVE_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
+	STARFIVE__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
+	STARFIVE_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
+	STARFIVE__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+	STARFIVE__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+	STARFIVE_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
+	STARFIVE_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
+	STARFIVE_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+	STARFIVE_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+	STARFIVE_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
+	STARFIVE_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
+	STARFIVE_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
+	STARFIVE_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
+	STARFIVE__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+	STARFIVE_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
+	STARFIVE_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
+	STARFIVE_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+	STARFIVE_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+	STARFIVE_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2,
+		      JH7100_CLK_PLL1_OUT),
+	STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
+		      JH7100_CLK_DDRPLL_DIV2),
+	STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
+		      JH7100_CLK_DDRPLL_DIV4),
+	STARFIVE_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2,
+		      JH7100_CLK_OSC_SYS),
+	STARFIVE_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
+		      JH7100_CLK_DDROSC_DIV2,
+		      JH7100_CLK_DDRPLL_DIV2,
+		      JH7100_CLK_DDRPLL_DIV4,
+		      JH7100_CLK_DDRPLL_DIV8),
+	STARFIVE_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
+		      JH7100_CLK_DDROSC_DIV2,
+		      JH7100_CLK_DDRPLL_DIV2,
+		      JH7100_CLK_DDRPLL_DIV4,
+		      JH7100_CLK_DDRPLL_DIV8),
+	STARFIVE_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
+	STARFIVE_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
+	STARFIVE__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
+		      JH7100_CLK_CPU_AXI,
+		      JH7100_CLK_NNEBUS_SRC1),
+	STARFIVE_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
+	STARFIVE_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
+	STARFIVE_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
+	STARFIVE_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
+	STARFIVE__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+	STARFIVE__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
+	STARFIVE_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
+	STARFIVE__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
+	STARFIVE_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
+	STARFIVE_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
+	STARFIVE__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+	STARFIVE_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+	STARFIVE_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8,
+		      JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+	STARFIVE_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
+	STARFIVE_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
+	STARFIVE__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
+	STARFIVE_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
+	STARFIVE_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
+		      JH7100_CLK_USBPHY_ROOTDIV),
+	STARFIVE__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
+		      JH7100_CLK_OSC_SYS,
+		      JH7100_CLK_USBPHY_PLLDIV25M),
+	STARFIVE_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
+	STARFIVE_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
+	STARFIVE_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
+	STARFIVE_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
+	STARFIVE__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
+	STARFIVE_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
+	STARFIVE_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
+	STARFIVE_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
+	STARFIVE__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
+	STARFIVE_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
+	STARFIVE_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
+	STARFIVE__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
+	STARFIVE_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
+	STARFIVE_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
+	STARFIVE_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
+	STARFIVE__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
+	STARFIVE__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
+	STARFIVE_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
+	STARFIVE_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
+	STARFIVE_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
+	STARFIVE__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
+	STARFIVE_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
+	STARFIVE__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
+	STARFIVE_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
+	STARFIVE_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
+	STARFIVE_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
+	STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+	STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+	STARFIVE__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
+		      JH7100_CLK_GMAC_GTX,
+		      JH7100_CLK_GMAC_TX_INV,
+		      JH7100_CLK_GMAC_RMII_TX),
+	STARFIVE__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
+	STARFIVE__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
+		      JH7100_CLK_GMAC_GR_MII_RX,
+		      JH7100_CLK_GMAC_RMII_RX),
+	STARFIVE__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
+	STARFIVE_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
+	STARFIVE_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
+	STARFIVE_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
+	STARFIVE_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
+	STARFIVE_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
+	STARFIVE_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
+	STARFIVE_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
+	STARFIVE_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+	STARFIVE_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+	STARFIVE_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+	STARFIVE_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+	STARFIVE_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+	STARFIVE_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+	STARFIVE_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
+	STARFIVE_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+	STARFIVE_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
+	STARFIVE_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
+	STARFIVE_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
 };
 
-static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
-{
-	return container_of(hw, struct jh7100_clk, hw);
-}
-
-static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
-{
-	return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
-}
-
-static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
-{
-	struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
-	void __iomem *reg = priv->base + 4 * clk->idx;
-
-	return readl_relaxed(reg);
-}
-
-static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
-{
-	struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
-	void __iomem *reg = priv->base + 4 * clk->idx;
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->rmw_lock, flags);
-	value |= readl_relaxed(reg) & ~mask;
-	writel_relaxed(value, reg);
-	spin_unlock_irqrestore(&priv->rmw_lock, flags);
-}
-
-static int jh7100_clk_enable(struct clk_hw *hw)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-
-	jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
-	return 0;
-}
-
-static void jh7100_clk_disable(struct clk_hw *hw)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-
-	jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
-}
-
-static int jh7100_clk_is_enabled(struct clk_hw *hw)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-
-	return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
-}
-
-static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
-					    unsigned long parent_rate)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
-
-	return div ? parent_rate / div : 0;
-}
-
-static int jh7100_clk_determine_rate(struct clk_hw *hw,
-				     struct clk_rate_request *req)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	unsigned long parent = req->best_parent_rate;
-	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
-	unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
-	unsigned long result = parent / div;
-
-	/*
-	 * we want the result clamped by min_rate and max_rate if possible:
-	 * case 1: div hits the max divider value, which means it's less than
-	 * parent / rate, so the result is greater than rate and min_rate in
-	 * particular. we can't do anything about result > max_rate because the
-	 * divider doesn't go any further.
-	 * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
-	 * always lower or equal to rate and max_rate. however the result may
-	 * turn out lower than min_rate, but then the next higher rate is fine:
-	 *   div - 1 = ceil(parent / rate) - 1 < parent / rate
-	 * and thus
-	 *   min_rate <= rate < parent / (div - 1)
-	 */
-	if (result < req->min_rate && div > 1)
-		result = parent / (div - 1);
-
-	req->rate = result;
-	return 0;
-}
-
-static int jh7100_clk_set_rate(struct clk_hw *hw,
-			       unsigned long rate,
-			       unsigned long parent_rate)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
-				  1UL, (unsigned long)clk->max_div);
-
-	jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
-	return 0;
-}
-
-static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
-						 unsigned long parent_rate)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	u32 reg = jh7100_clk_reg_get(clk);
-	unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
-			       ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
-
-	return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
-}
-
-static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
-					  struct clk_rate_request *req)
-{
-	unsigned long parent100 = 100 * req->best_parent_rate;
-	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
-	unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
-				     JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
-	unsigned long result = parent100 / div100;
-
-	/* clamp the result as in jh7100_clk_determine_rate() above */
-	if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
-		result = parent100 / (div100 + 1);
-	if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
-		result = parent100 / (div100 - 1);
-
-	req->rate = result;
-	return 0;
-}
-
-static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
-				    unsigned long rate,
-				    unsigned long parent_rate)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
-				     JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
-	u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
-
-	jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
-	return 0;
-}
-
-static u8 jh7100_clk_get_parent(struct clk_hw *hw)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	u32 value = jh7100_clk_reg_get(clk);
-
-	return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
-}
-
-static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
-
-	jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
-	return 0;
-}
-
-static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
-					 struct clk_rate_request *req)
-{
-	return clk_mux_determine_rate_flags(hw, req, 0);
-}
-
-static int jh7100_clk_get_phase(struct clk_hw *hw)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	u32 value = jh7100_clk_reg_get(clk);
-
-	return (value & JH7100_CLK_INVERT) ? 180 : 0;
-}
-
-static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
-{
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	u32 value;
-
-	if (degrees == 0)
-		value = 0;
-	else if (degrees == 180)
-		value = JH7100_CLK_INVERT;
-	else
-		return -EINVAL;
-
-	jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
-	return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
-{
-	static const struct debugfs_reg32 jh7100_clk_reg = {
-		.name = "CTRL",
-		.offset = 0,
-	};
-	struct jh7100_clk *clk = jh7100_clk_from(hw);
-	struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
-	struct debugfs_regset32 *regset;
-
-	regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
-	if (!regset)
-		return;
-
-	regset->regs = &jh7100_clk_reg;
-	regset->nregs = 1;
-	regset->base = priv->base + 4 * clk->idx;
-
-	debugfs_create_regset32("registers", 0400, dentry, regset);
-}
-#else
-#define jh7100_clk_debug_init NULL
-#endif
-
-static const struct clk_ops jh7100_clk_gate_ops = {
-	.enable = jh7100_clk_enable,
-	.disable = jh7100_clk_disable,
-	.is_enabled = jh7100_clk_is_enabled,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_div_ops = {
-	.recalc_rate = jh7100_clk_recalc_rate,
-	.determine_rate = jh7100_clk_determine_rate,
-	.set_rate = jh7100_clk_set_rate,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_fdiv_ops = {
-	.recalc_rate = jh7100_clk_frac_recalc_rate,
-	.determine_rate = jh7100_clk_frac_determine_rate,
-	.set_rate = jh7100_clk_frac_set_rate,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gdiv_ops = {
-	.enable = jh7100_clk_enable,
-	.disable = jh7100_clk_disable,
-	.is_enabled = jh7100_clk_is_enabled,
-	.recalc_rate = jh7100_clk_recalc_rate,
-	.determine_rate = jh7100_clk_determine_rate,
-	.set_rate = jh7100_clk_set_rate,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_mux_ops = {
-	.determine_rate = jh7100_clk_mux_determine_rate,
-	.set_parent = jh7100_clk_set_parent,
-	.get_parent = jh7100_clk_get_parent,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gmux_ops = {
-	.enable = jh7100_clk_enable,
-	.disable = jh7100_clk_disable,
-	.is_enabled = jh7100_clk_is_enabled,
-	.determine_rate = jh7100_clk_mux_determine_rate,
-	.set_parent = jh7100_clk_set_parent,
-	.get_parent = jh7100_clk_get_parent,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_mdiv_ops = {
-	.recalc_rate = jh7100_clk_recalc_rate,
-	.determine_rate = jh7100_clk_determine_rate,
-	.get_parent = jh7100_clk_get_parent,
-	.set_parent = jh7100_clk_set_parent,
-	.set_rate = jh7100_clk_set_rate,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gmd_ops = {
-	.enable = jh7100_clk_enable,
-	.disable = jh7100_clk_disable,
-	.is_enabled = jh7100_clk_is_enabled,
-	.recalc_rate = jh7100_clk_recalc_rate,
-	.determine_rate = jh7100_clk_determine_rate,
-	.get_parent = jh7100_clk_get_parent,
-	.set_parent = jh7100_clk_set_parent,
-	.set_rate = jh7100_clk_set_rate,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_inv_ops = {
-	.get_phase = jh7100_clk_get_phase,
-	.set_phase = jh7100_clk_set_phase,
-	.debug_init = jh7100_clk_debug_init,
-};
-
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
-{
-	if (max & JH7100_CLK_DIV_MASK) {
-		if (max & JH7100_CLK_MUX_MASK) {
-			if (max & JH7100_CLK_ENABLE)
-				return &jh7100_clk_gmd_ops;
-			return &jh7100_clk_mdiv_ops;
-		}
-		if (max & JH7100_CLK_ENABLE)
-			return &jh7100_clk_gdiv_ops;
-		if (max == JH7100_CLK_FRAC_MAX)
-			return &jh7100_clk_fdiv_ops;
-		return &jh7100_clk_div_ops;
-	}
-
-	if (max & JH7100_CLK_MUX_MASK) {
-		if (max & JH7100_CLK_ENABLE)
-			return &jh7100_clk_gmux_ops;
-		return &jh7100_clk_mux_ops;
-	}
-
-	if (max & JH7100_CLK_ENABLE)
-		return &jh7100_clk_gate_ops;
-
-	return &jh7100_clk_inv_ops;
-}
-EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
-
 static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
 {
-	struct jh7100_clk_priv *priv = data;
+	struct starfive_clk_priv *priv = data;
 	unsigned int idx = clkspec->args[0];
 
 	if (idx < JH7100_CLK_PLL0_OUT)
@@ -605,7 +287,7 @@ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data
 
 static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
 {
-	struct jh7100_clk_priv *priv;
+	struct starfive_clk_priv *priv;
 	unsigned int idx;
 	int ret;
 
@@ -639,12 +321,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
 		struct clk_parent_data parents[4] = {};
 		struct clk_init_data init = {
 			.name = jh7100_clk_data[idx].name,
-			.ops = starfive_jh7100_clk_ops(max),
+			.ops = starfive_clk_ops(max),
 			.parent_data = parents,
-			.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+			.num_parents =
+				((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
 			.flags = jh7100_clk_data[idx].flags,
 		};
-		struct jh7100_clk *clk = &priv->reg[idx];
+		struct starfive_clk *clk = &priv->reg[idx];
 		unsigned int i;
 
 		for (i = 0; i < init.num_parents; i++) {
@@ -666,7 +349,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
 
 		clk->hw.init = &init;
 		clk->idx = idx;
-		clk->max_div = max & JH7100_CLK_DIV_MASK;
+		clk->max_div = max & STARFIVE_CLK_DIV_MASK;
 
 		ret = devm_clk_hw_register(priv->dev, &clk->hw);
 		if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h
deleted file mode 100644
index f116be5740a5..000000000000
--- a/drivers/clk/starfive/clk-starfive-jh7100.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CLK_STARFIVE_JH7100_H
-#define __CLK_STARFIVE_JH7100_H
-
-#include <linux/bits.h>
-#include <linux/clk-provider.h>
-
-/* register fields */
-#define JH7100_CLK_ENABLE	BIT(31)
-#define JH7100_CLK_INVERT	BIT(30)
-#define JH7100_CLK_MUX_MASK	GENMASK(27, 24)
-#define JH7100_CLK_MUX_SHIFT	24
-#define JH7100_CLK_DIV_MASK	GENMASK(23, 0)
-#define JH7100_CLK_FRAC_MASK	GENMASK(15, 8)
-#define JH7100_CLK_FRAC_SHIFT	8
-#define JH7100_CLK_INT_MASK	GENMASK(7, 0)
-
-/* fractional divider min/max */
-#define JH7100_CLK_FRAC_MIN	100UL
-#define JH7100_CLK_FRAC_MAX	25599UL
-
-/* clock data */
-struct jh7100_clk_data {
-	const char *name;
-	unsigned long flags;
-	u32 max;
-	u8 parents[4];
-};
-
-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = {			\
-	.name = _name,								\
-	.flags = CLK_SET_RATE_PARENT | (_flags),				\
-	.max = JH7100_CLK_ENABLE,						\
-	.parents = { [0] = _parent },						\
-}
-
-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = {			\
-	.name = _name,								\
-	.flags = 0,								\
-	.max = _max,								\
-	.parents = { [0] = _parent },						\
-}
-
-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = {		\
-	.name = _name,								\
-	.flags = _flags,							\
-	.max = JH7100_CLK_ENABLE | (_max),					\
-	.parents = { [0] = _parent },						\
-}
-
-#define JH7100_FDIV(_idx, _name, _parent) [_idx] = {				\
-	.name = _name,								\
-	.flags = 0,								\
-	.max = JH7100_CLK_FRAC_MAX,						\
-	.parents = { [0] = _parent },						\
-}
-
-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = {			\
-	.name = _name,								\
-	.flags = 0,								\
-	.max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT,			\
-	.parents = { __VA_ARGS__ },						\
-}
-
-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = {		\
-	.name = _name,								\
-	.flags = _flags,							\
-	.max = JH7100_CLK_ENABLE |						\
-		(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT),			\
-	.parents = { __VA_ARGS__ },						\
-}
-
-#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = {		\
-	.name = _name,								\
-	.flags = 0,								\
-	.max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max),		\
-	.parents = { __VA_ARGS__ },						\
-}
-
-#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = {	\
-	.name = _name,								\
-	.flags = _flags,							\
-	.max = JH7100_CLK_ENABLE |						\
-		(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max),		\
-	.parents = { __VA_ARGS__ },						\
-}
-
-#define JH7100__INV(_idx, _name, _parent) [_idx] = {				\
-	.name = _name,								\
-	.flags = CLK_SET_RATE_PARENT,						\
-	.max = JH7100_CLK_INVERT,						\
-	.parents = { [0] = _parent },						\
-}
-
-struct jh7100_clk {
-	struct clk_hw hw;
-	unsigned int idx;
-	unsigned int max_div;
-};
-
-struct jh7100_clk_priv {
-	/* protect clk enable and set rate/parent from happening at the same time */
-	spinlock_t rmw_lock;
-	struct device *dev;
-	void __iomem *base;
-	struct clk_hw *pll[3];
-	struct jh7100_clk reg[];
-};
-
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
-
-#endif
diff --git a/drivers/clk/starfive/clk-starfive.c b/drivers/clk/starfive/clk-starfive.c
new file mode 100644
index 000000000000..76e3d45b5d86
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive Clock Generator Driver
+ *
+ * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/io.h>
+
+#include "clk-starfive.h"
+
+static struct starfive_clk *starfive_clk_from(struct clk_hw *hw)
+{
+	return container_of(hw, struct starfive_clk, hw);
+}
+
+static struct starfive_clk_priv *starfive_priv_from(struct starfive_clk *clk)
+{
+	return container_of(clk, struct starfive_clk_priv, reg[clk->idx]);
+}
+
+static u32 starfive_clk_reg_get(struct starfive_clk *clk)
+{
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	void __iomem *reg = priv->base + 4 * clk->idx;
+
+	return readl_relaxed(reg);
+}
+
+static void starfive_clk_reg_rmw(struct starfive_clk *clk, u32 mask, u32 value)
+{
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	void __iomem *reg = priv->base + 4 * clk->idx;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->rmw_lock, flags);
+	value |= readl_relaxed(reg) & ~mask;
+	writel_relaxed(value, reg);
+	spin_unlock_irqrestore(&priv->rmw_lock, flags);
+}
+
+static int starfive_clk_enable(struct clk_hw *hw)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+
+	starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
+	return 0;
+}
+
+static void starfive_clk_disable(struct clk_hw *hw)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+
+	starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, 0);
+}
+
+static int starfive_clk_is_enabled(struct clk_hw *hw)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+
+	return !!(starfive_clk_reg_get(clk) & STARFIVE_CLK_ENABLE);
+}
+
+static unsigned long starfive_clk_recalc_rate(struct clk_hw *hw,
+					      unsigned long parent_rate)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	u32 div = starfive_clk_reg_get(clk) & STARFIVE_CLK_DIV_MASK;
+
+	return div ? parent_rate / div : 0;
+}
+
+static int starfive_clk_determine_rate(struct clk_hw *hw,
+				       struct clk_rate_request *req)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	unsigned long parent = req->best_parent_rate;
+	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+	unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
+	unsigned long result = parent / div;
+
+	/*
+	 * we want the result clamped by min_rate and max_rate if possible:
+	 * case 1: div hits the max divider value, which means it's less than
+	 * parent / rate, so the result is greater than rate and min_rate in
+	 * particular. we can't do anything about result > max_rate because the
+	 * divider doesn't go any further.
+	 * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
+	 * always lower or equal to rate and max_rate. however the result may
+	 * turn out lower than min_rate, but then the next higher rate is fine:
+	 *   div - 1 = ceil(parent / rate) - 1 < parent / rate
+	 * and thus
+	 *   min_rate <= rate < parent / (div - 1)
+	 */
+	if (result < req->min_rate && div > 1)
+		result = parent / (div - 1);
+
+	req->rate = result;
+	return 0;
+}
+
+static int starfive_clk_set_rate(struct clk_hw *hw,
+				 unsigned long rate,
+				 unsigned long parent_rate)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
+				  1UL, (unsigned long)clk->max_div);
+
+	starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, div);
+	return 0;
+}
+
+static unsigned long starfive_clk_frac_recalc_rate(struct clk_hw *hw,
+						   unsigned long parent_rate)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	u32 reg = starfive_clk_reg_get(clk);
+	unsigned long div100 = 100 * (reg & STARFIVE_CLK_INT_MASK) +
+			       ((reg & STARFIVE_CLK_FRAC_MASK) >> STARFIVE_CLK_FRAC_SHIFT);
+
+	return (div100 >= STARFIVE_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
+}
+
+static int starfive_clk_frac_determine_rate(struct clk_hw *hw,
+					    struct clk_rate_request *req)
+{
+	unsigned long parent100 = 100 * req->best_parent_rate;
+	unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+	unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
+				     STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
+	unsigned long result = parent100 / div100;
+
+	/* clamp the result as in starfive_clk_determine_rate() above */
+	if (result > req->max_rate && div100 < STARFIVE_CLK_FRAC_MAX)
+		result = parent100 / (div100 + 1);
+	if (result < req->min_rate && div100 > STARFIVE_CLK_FRAC_MIN)
+		result = parent100 / (div100 - 1);
+
+	req->rate = result;
+	return 0;
+}
+
+static int starfive_clk_frac_set_rate(struct clk_hw *hw,
+				      unsigned long rate,
+				      unsigned long parent_rate)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
+				     STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
+	u32 value = ((div100 % 100) << STARFIVE_CLK_FRAC_SHIFT) | (div100 / 100);
+
+	starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, value);
+	return 0;
+}
+
+static u8 starfive_clk_get_parent(struct clk_hw *hw)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	u32 value = starfive_clk_reg_get(clk);
+
+	return (value & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT;
+}
+
+static int starfive_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	u32 value = (u32)index << STARFIVE_CLK_MUX_SHIFT;
+
+	starfive_clk_reg_rmw(clk, STARFIVE_CLK_MUX_MASK, value);
+	return 0;
+}
+
+static int starfive_clk_mux_determine_rate(struct clk_hw *hw,
+					   struct clk_rate_request *req)
+{
+	return clk_mux_determine_rate_flags(hw, req, 0);
+}
+
+static int starfive_clk_get_phase(struct clk_hw *hw)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	u32 value = starfive_clk_reg_get(clk);
+
+	return (value & STARFIVE_CLK_INVERT) ? 180 : 0;
+}
+
+static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
+{
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	u32 value;
+
+	if (degrees == 0)
+		value = 0;
+	else if (degrees == 180)
+		value = STARFIVE_CLK_INVERT;
+	else
+		return -EINVAL;
+
+	starfive_clk_reg_rmw(clk, STARFIVE_CLK_INVERT, value);
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+	static const struct debugfs_reg32 starfive_clk_reg = {
+		.name = "CTRL",
+		.offset = 0,
+	};
+	struct starfive_clk *clk = starfive_clk_from(hw);
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	struct debugfs_regset32 *regset;
+
+	regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
+	if (!regset)
+		return;
+
+	regset->regs = &starfive_clk_reg;
+	regset->nregs = 1;
+	regset->base = priv->base + 4 * clk->idx;
+
+	debugfs_create_regset32("registers", 0400, dentry, regset);
+}
+#else
+#define starfive_clk_debug_init NULL
+#endif
+
+static const struct clk_ops starfive_clk_gate_ops = {
+	.enable = starfive_clk_enable,
+	.disable = starfive_clk_disable,
+	.is_enabled = starfive_clk_is_enabled,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_div_ops = {
+	.recalc_rate = starfive_clk_recalc_rate,
+	.determine_rate = starfive_clk_determine_rate,
+	.set_rate = starfive_clk_set_rate,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_fdiv_ops = {
+	.recalc_rate = starfive_clk_frac_recalc_rate,
+	.determine_rate = starfive_clk_frac_determine_rate,
+	.set_rate = starfive_clk_frac_set_rate,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_gdiv_ops = {
+	.enable = starfive_clk_enable,
+	.disable = starfive_clk_disable,
+	.is_enabled = starfive_clk_is_enabled,
+	.recalc_rate = starfive_clk_recalc_rate,
+	.determine_rate = starfive_clk_determine_rate,
+	.set_rate = starfive_clk_set_rate,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_mux_ops = {
+	.determine_rate = starfive_clk_mux_determine_rate,
+	.set_parent = starfive_clk_set_parent,
+	.get_parent = starfive_clk_get_parent,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_gmux_ops = {
+	.enable = starfive_clk_enable,
+	.disable = starfive_clk_disable,
+	.is_enabled = starfive_clk_is_enabled,
+	.determine_rate = starfive_clk_mux_determine_rate,
+	.set_parent = starfive_clk_set_parent,
+	.get_parent = starfive_clk_get_parent,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_mdiv_ops = {
+	.recalc_rate = starfive_clk_recalc_rate,
+	.determine_rate = starfive_clk_determine_rate,
+	.get_parent = starfive_clk_get_parent,
+	.set_parent = starfive_clk_set_parent,
+	.set_rate = starfive_clk_set_rate,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_gmd_ops = {
+	.enable = starfive_clk_enable,
+	.disable = starfive_clk_disable,
+	.is_enabled = starfive_clk_is_enabled,
+	.recalc_rate = starfive_clk_recalc_rate,
+	.determine_rate = starfive_clk_determine_rate,
+	.get_parent = starfive_clk_get_parent,
+	.set_parent = starfive_clk_set_parent,
+	.set_rate = starfive_clk_set_rate,
+	.debug_init = starfive_clk_debug_init,
+};
+
+static const struct clk_ops starfive_clk_inv_ops = {
+	.get_phase = starfive_clk_get_phase,
+	.set_phase = starfive_clk_set_phase,
+	.debug_init = starfive_clk_debug_init,
+};
+
+const struct clk_ops *starfive_clk_ops(u32 max)
+{
+	if (max & STARFIVE_CLK_DIV_MASK) {
+		if (max & STARFIVE_CLK_MUX_MASK) {
+			if (max & STARFIVE_CLK_ENABLE)
+				return &starfive_clk_gmd_ops;
+			return &starfive_clk_mdiv_ops;
+		}
+		if (max & STARFIVE_CLK_ENABLE)
+			return &starfive_clk_gdiv_ops;
+		if (max == STARFIVE_CLK_FRAC_MAX)
+			return &starfive_clk_fdiv_ops;
+		return &starfive_clk_div_ops;
+	}
+
+	if (max & STARFIVE_CLK_MUX_MASK) {
+		if (max & STARFIVE_CLK_ENABLE)
+			return &starfive_clk_gmux_ops;
+		return &starfive_clk_mux_ops;
+	}
+
+	if (max & STARFIVE_CLK_ENABLE)
+		return &starfive_clk_gate_ops;
+
+	return &starfive_clk_inv_ops;
+}
+EXPORT_SYMBOL_GPL(starfive_clk_ops);
diff --git a/drivers/clk/starfive/clk-starfive.h b/drivers/clk/starfive/clk-starfive.h
new file mode 100644
index 000000000000..6b05cf1bfbb6
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CLK_STARFIVE_H
+#define __CLK_STARFIVE_H
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+
+/* register fields */
+#define STARFIVE_CLK_ENABLE	BIT(31)
+#define STARFIVE_CLK_INVERT	BIT(30)
+#define STARFIVE_CLK_MUX_MASK	GENMASK(27, 24)
+#define STARFIVE_CLK_MUX_SHIFT	24
+#define STARFIVE_CLK_DIV_MASK	GENMASK(23, 0)
+#define STARFIVE_CLK_FRAC_MASK	GENMASK(15, 8)
+#define STARFIVE_CLK_FRAC_SHIFT	8
+#define STARFIVE_CLK_INT_MASK	GENMASK(7, 0)
+
+/* fractional divider min/max */
+#define STARFIVE_CLK_FRAC_MIN	100UL
+#define STARFIVE_CLK_FRAC_MAX	25599UL
+
+/* clock data */
+struct starfive_clk_data {
+	const char *name;
+	unsigned long flags;
+	u32 max;
+	u8 parents[4];
+};
+
+#define STARFIVE_GATE(_idx, _name, _flags, _parent) [_idx] = {			\
+	.name = _name,								\
+	.flags = CLK_SET_RATE_PARENT | (_flags),				\
+	.max = STARFIVE_CLK_ENABLE,						\
+	.parents = { [0] = _parent },						\
+}
+
+#define STARFIVE__DIV(_idx, _name, _max, _parent) [_idx] = {			\
+	.name = _name,								\
+	.flags = 0,								\
+	.max = _max,								\
+	.parents = { [0] = _parent },						\
+}
+
+#define STARFIVE_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = {		\
+	.name = _name,								\
+	.flags = _flags,							\
+	.max = STARFIVE_CLK_ENABLE | (_max),					\
+	.parents = { [0] = _parent },						\
+}
+
+#define STARFIVE_FDIV(_idx, _name, _parent) [_idx] = {				\
+	.name = _name,								\
+	.flags = 0,								\
+	.max = STARFIVE_CLK_FRAC_MAX,						\
+	.parents = { [0] = _parent },						\
+}
+
+#define STARFIVE__MUX(_idx, _name, _nparents, ...) [_idx] = {			\
+	.name = _name,								\
+	.flags = 0,								\
+	.max = ((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT,			\
+	.parents = { __VA_ARGS__ },						\
+}
+
+#define STARFIVE_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = {		\
+	.name = _name,								\
+	.flags = _flags,							\
+	.max = STARFIVE_CLK_ENABLE |						\
+		(((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT),			\
+	.parents = { __VA_ARGS__ },						\
+}
+
+#define STARFIVE_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = {		\
+	.name = _name,								\
+	.flags = 0,								\
+	.max = (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max),		\
+	.parents = { __VA_ARGS__ },						\
+}
+
+#define STARFIVE__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = {	\
+	.name = _name,								\
+	.flags = _flags,							\
+	.max = STARFIVE_CLK_ENABLE |						\
+		(((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max),		\
+	.parents = { __VA_ARGS__ },						\
+}
+
+#define STARFIVE__INV(_idx, _name, _parent) [_idx] = {				\
+	.name = _name,								\
+	.flags = CLK_SET_RATE_PARENT,						\
+	.max = STARFIVE_CLK_INVERT,						\
+	.parents = { [0] = _parent },						\
+}
+
+struct starfive_clk {
+	struct clk_hw hw;
+	unsigned int idx;
+	unsigned int max_div;
+};
+
+struct starfive_clk_priv {
+	/* protect clk enable and set rate/parent from happening at the same time */
+	spinlock_t rmw_lock;
+	struct device *dev;
+	void __iomem *base;
+	struct clk_hw *pll[3];
+	struct starfive_clk reg[];
+};
+
+const struct clk_ops *starfive_clk_ops(u32 max);
+
+#endif
-- 
2.17.1

Re: [PATCH v1 14/30] clk: starfive: Factor out common clock driver code

[Stephen Boyd]

Quoting Hal Feng (2022-09-29 10:54:59)
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> The clock control registers on the StarFive SoCs work identically,
> so factor out the code then drivers for different SoCs can share
> it without depending on each other. No functional change.

Sounds great! No functional change! But to verify that it is pretty
hard.  Can you generate the patch with `git format-patch -M -C` and not
rename anything initially? I hope that will allow us to see that really
nothing has changed except code is moved from one file to another. Then
the next patch can be the sed command to rename to starfive.

As the patch is right now, I'm not particularly interested in going
through 700 lines to make sure nothing really changed.

[PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Hal Feng]

Clock registers address region is shared with reset controller
on the new StarFive JH7110 SoC. Change to use regmap framework
to allow base address sharing and preparation for JH7110 clock
support.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../clk/starfive/clk-starfive-jh7100-audio.c  | 11 ++--
 drivers/clk/starfive/clk-starfive-jh7100.c    | 11 ++--
 drivers/clk/starfive/clk-starfive.c           | 66 ++++++++++++-------
 drivers/clk/starfive/clk-starfive.h           |  4 +-
 4 files changed, 56 insertions(+), 36 deletions(-)

diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 41389cacfe03..4168209d6600 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -9,6 +9,7 @@
 #include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
@@ -108,11 +109,13 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
 	if (!priv)
 		return -ENOMEM;
 
-	spin_lock_init(&priv->rmw_lock);
 	priv->dev = &pdev->dev;
-	priv->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
+	priv->regmap = device_node_to_regmap(priv->dev->of_node);
+	if (IS_ERR(priv->regmap)) {
+		dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+			PTR_ERR(priv->regmap));
+		return PTR_ERR(priv->regmap);
+	}
 
 	for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
 		u32 max = jh7100_audclk_data[idx].max;
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 014e36f17595..410aa6e06842 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -10,6 +10,7 @@
 #include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/init.h>
+#include <linux/mfd/syscon.h>
 #include <linux/mod_devicetable.h>
 #include <linux/platform_device.h>
 
@@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
 	if (!priv)
 		return -ENOMEM;
 
-	spin_lock_init(&priv->rmw_lock);
 	priv->dev = &pdev->dev;
-	priv->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
+	priv->regmap = device_node_to_regmap(priv->dev->of_node);
+	if (IS_ERR(priv->regmap)) {
+		dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+			PTR_ERR(priv->regmap));
+		return PTR_ERR(priv->regmap);
+	}
 
 	priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
 							 "osc_sys", 0, 40, 1);
diff --git a/drivers/clk/starfive/clk-starfive.c b/drivers/clk/starfive/clk-starfive.c
index 76e3d45b5d86..e428476417c5 100644
--- a/drivers/clk/starfive/clk-starfive.c
+++ b/drivers/clk/starfive/clk-starfive.c
@@ -9,6 +9,9 @@
 #include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
 
 #include "clk-starfive.h"
 
@@ -25,36 +28,36 @@ static struct starfive_clk_priv *starfive_priv_from(struct starfive_clk *clk)
 static u32 starfive_clk_reg_get(struct starfive_clk *clk)
 {
 	struct starfive_clk_priv *priv = starfive_priv_from(clk);
-	void __iomem *reg = priv->base + 4 * clk->idx;
+	unsigned int reg = sizeof(u32) * clk->idx;
+	unsigned int value;
+	int ret;
 
-	return readl_relaxed(reg);
-}
-
-static void starfive_clk_reg_rmw(struct starfive_clk *clk, u32 mask, u32 value)
-{
-	struct starfive_clk_priv *priv = starfive_priv_from(clk);
-	void __iomem *reg = priv->base + 4 * clk->idx;
-	unsigned long flags;
+	ret = regmap_read(priv->regmap, reg, &value);
+	if (ret) {
+		dev_warn(priv->dev, "Failed to read clock register: %d\n", ret);
+		value = 0;
+	}
 
-	spin_lock_irqsave(&priv->rmw_lock, flags);
-	value |= readl_relaxed(reg) & ~mask;
-	writel_relaxed(value, reg);
-	spin_unlock_irqrestore(&priv->rmw_lock, flags);
+	return value;
 }
 
 static int starfive_clk_enable(struct clk_hw *hw)
 {
 	struct starfive_clk *clk = starfive_clk_from(hw);
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	unsigned int reg = sizeof(u32) * clk->idx;
 
-	starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
-	return 0;
+	return regmap_update_bits(priv->regmap, reg,
+				  STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
 }
 
 static void starfive_clk_disable(struct clk_hw *hw)
 {
 	struct starfive_clk *clk = starfive_clk_from(hw);
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	unsigned int reg = sizeof(u32) * clk->idx;
 
-	starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, 0);
+	regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_ENABLE, 0);
 }
 
 static int starfive_clk_is_enabled(struct clk_hw *hw)
@@ -107,11 +110,12 @@ static int starfive_clk_set_rate(struct clk_hw *hw,
 				 unsigned long parent_rate)
 {
 	struct starfive_clk *clk = starfive_clk_from(hw);
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	unsigned int reg = sizeof(u32) * clk->idx;
 	unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
 				  1UL, (unsigned long)clk->max_div);
 
-	starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, div);
-	return 0;
+	return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_DIV_MASK, div);
 }
 
 static unsigned long starfive_clk_frac_recalc_rate(struct clk_hw *hw,
@@ -149,12 +153,13 @@ static int starfive_clk_frac_set_rate(struct clk_hw *hw,
 				      unsigned long parent_rate)
 {
 	struct starfive_clk *clk = starfive_clk_from(hw);
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	unsigned int reg = sizeof(u32) * clk->idx;
 	unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
 				     STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
 	u32 value = ((div100 % 100) << STARFIVE_CLK_FRAC_SHIFT) | (div100 / 100);
 
-	starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, value);
-	return 0;
+	return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_DIV_MASK, value);
 }
 
 static u8 starfive_clk_get_parent(struct clk_hw *hw)
@@ -168,10 +173,11 @@ static u8 starfive_clk_get_parent(struct clk_hw *hw)
 static int starfive_clk_set_parent(struct clk_hw *hw, u8 index)
 {
 	struct starfive_clk *clk = starfive_clk_from(hw);
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	unsigned int reg = sizeof(u32) * clk->idx;
 	u32 value = (u32)index << STARFIVE_CLK_MUX_SHIFT;
 
-	starfive_clk_reg_rmw(clk, STARFIVE_CLK_MUX_MASK, value);
-	return 0;
+	return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_MUX_MASK, value);
 }
 
 static int starfive_clk_mux_determine_rate(struct clk_hw *hw,
@@ -191,6 +197,8 @@ static int starfive_clk_get_phase(struct clk_hw *hw)
 static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
 {
 	struct starfive_clk *clk = starfive_clk_from(hw);
+	struct starfive_clk_priv *priv = starfive_priv_from(clk);
+	unsigned int reg = sizeof(u32) * clk->idx;
 	u32 value;
 
 	if (degrees == 0)
@@ -200,8 +208,7 @@ static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
 	else
 		return -EINVAL;
 
-	starfive_clk_reg_rmw(clk, STARFIVE_CLK_INVERT, value);
-	return 0;
+	return regmap_update_bits(priv->regmap, reg, STARFIVE_CLK_INVERT, value);
 }
 
 #ifdef CONFIG_DEBUG_FS
@@ -214,6 +221,7 @@ static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
 	struct starfive_clk *clk = starfive_clk_from(hw);
 	struct starfive_clk_priv *priv = starfive_priv_from(clk);
 	struct debugfs_regset32 *regset;
+	void __iomem *base;
 
 	regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
 	if (!regset)
@@ -221,7 +229,15 @@ static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
 
 	regset->regs = &starfive_clk_reg;
 	regset->nregs = 1;
-	regset->base = priv->base + 4 * clk->idx;
+
+	base = of_iomap(priv->dev->of_node, 0);
+	if (!base) {
+		base = of_iomap(priv->dev->of_node->parent, 0);
+		if (!base)
+			return;
+	}
+
+	regset->base = base + sizeof(u32) * clk->idx;
 
 	debugfs_create_regset32("registers", 0400, dentry, regset);
 }
diff --git a/drivers/clk/starfive/clk-starfive.h b/drivers/clk/starfive/clk-starfive.h
index 6b05cf1bfbb6..99cf74e8cbde 100644
--- a/drivers/clk/starfive/clk-starfive.h
+++ b/drivers/clk/starfive/clk-starfive.h
@@ -101,10 +101,8 @@ struct starfive_clk {
 };
 
 struct starfive_clk_priv {
-	/* protect clk enable and set rate/parent from happening at the same time */
-	spinlock_t rmw_lock;
 	struct device *dev;
-	void __iomem *base;
+	struct regmap *regmap;
 	struct clk_hw *pll[3];
 	struct starfive_clk reg[];
 };
-- 
2.17.1

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Stephen Boyd]

Quoting Hal Feng (2022-09-29 10:56:02)
> Clock registers address region is shared with reset controller
> on the new StarFive JH7110 SoC. Change to use regmap framework
> to allow base address sharing and preparation for JH7110 clock
> support.

Do the reset and clk parts share actual registers, where we would need
to lock between rmw? Or is regmap just nice to have because it wraps up
the register APIs with some extra features?

> 
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
[...]
> diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
> index 014e36f17595..410aa6e06842 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7100.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
> @@ -10,6 +10,7 @@
>  #include <linux/clk-provider.h>
>  #include <linux/device.h>
>  #include <linux/init.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/mod_devicetable.h>
>  #include <linux/platform_device.h>
>  
> @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
>         if (!priv)
>                 return -ENOMEM;
>  
> -       spin_lock_init(&priv->rmw_lock);
>         priv->dev = &pdev->dev;
> -       priv->base = devm_platform_ioremap_resource(pdev, 0);
> -       if (IS_ERR(priv->base))
> -               return PTR_ERR(priv->base);
> +       priv->regmap = device_node_to_regmap(priv->dev->of_node);

This is sad. Why do we need to make a syscon? Can we instead use the
auxiliary bus to make a reset device that either gets a regmap made here
in this driver or uses a void __iomem * mapped with ioremap
(priv->base)?

> +       if (IS_ERR(priv->regmap)) {
> +               dev_err(priv->dev, "failed to get regmap (error %ld)\n",
> +                       PTR_ERR(priv->regmap));
> +               return PTR_ERR(priv->regmap);

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Emil Renner Berthing]

On Fri, 30 Sept 2022 at 23:50, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Hal Feng (2022-09-29 10:56:02)
> > Clock registers address region is shared with reset controller
> > on the new StarFive JH7110 SoC. Change to use regmap framework
> > to allow base address sharing and preparation for JH7110 clock
> > support.
>
> Do the reset and clk parts share actual registers, where we would need
> to lock between rmw? Or is regmap just nice to have because it wraps up
> the register APIs with some extra features?

No, the registers aren't shared, but on the JH7100 clock and reset had
separate ranges, but on the JH7110 there is just one memory range for
each "CRG", clock and reset generator I presume, and the reset
registers are placed after the clock registers in the same range.

> >
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> [...]
> > diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
> > index 014e36f17595..410aa6e06842 100644
> > --- a/drivers/clk/starfive/clk-starfive-jh7100.c
> > +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
> > @@ -10,6 +10,7 @@
> >  #include <linux/clk-provider.h>
> >  #include <linux/device.h>
> >  #include <linux/init.h>
> > +#include <linux/mfd/syscon.h>
> >  #include <linux/mod_devicetable.h>
> >  #include <linux/platform_device.h>
> >
> > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> >         if (!priv)
> >                 return -ENOMEM;
> >
> > -       spin_lock_init(&priv->rmw_lock);
> >         priv->dev = &pdev->dev;
> > -       priv->base = devm_platform_ioremap_resource(pdev, 0);
> > -       if (IS_ERR(priv->base))
> > -               return PTR_ERR(priv->base);
> > +       priv->regmap = device_node_to_regmap(priv->dev->of_node);
>
> This is sad. Why do we need to make a syscon? Can we instead use the
> auxiliary bus to make a reset device that either gets a regmap made here
> in this driver or uses a void __iomem * mapped with ioremap
> (priv->base)?

In my original code the clock driver just registers the resets too
similar to other combined clock and reset drivers. I wonder what you
think about that approach:
https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
and
https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471

> > +       if (IS_ERR(priv->regmap)) {
> > +               dev_err(priv->dev, "failed to get regmap (error %ld)\n",
> > +                       PTR_ERR(priv->regmap));
> > +               return PTR_ERR(priv->regmap);
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Stephen Boyd]

Quoting Emil Renner Berthing (2022-10-05 06:14:44)
> > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> > >         if (!priv)
> > >                 return -ENOMEM;
> > >
> > > -       spin_lock_init(&priv->rmw_lock);
> > >         priv->dev = &pdev->dev;
> > > -       priv->base = devm_platform_ioremap_resource(pdev, 0);
> > > -       if (IS_ERR(priv->base))
> > > -               return PTR_ERR(priv->base);
> > > +       priv->regmap = device_node_to_regmap(priv->dev->of_node);
> >
> > This is sad. Why do we need to make a syscon? Can we instead use the
> > auxiliary bus to make a reset device that either gets a regmap made here
> > in this driver or uses a void __iomem * mapped with ioremap
> > (priv->base)?
> 
> In my original code the clock driver just registers the resets too
> similar to other combined clock and reset drivers. I wonder what you
> think about that approach:
> https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
> and
> https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471

I think we should use auxiliary bus and split the driver logically into
a reset driver in drivers/reset and a clk driver in drivers/clk. That
way the appropriate maintainers can review the code. There is only one
platform device with a single reg property and node in DT, but there are
two drivers.

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Hal Feng]

On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> Quoting Emil Renner Berthing (2022-10-05 06:14:44)
> > > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> > > >         if (!priv)
> > > >                 return -ENOMEM;
> > > >
> > > > -       spin_lock_init(&priv->rmw_lock);
> > > >         priv->dev = &pdev->dev;
> > > > -       priv->base = devm_platform_ioremap_resource(pdev, 0);
> > > > -       if (IS_ERR(priv->base))
> > > > -               return PTR_ERR(priv->base);
> > > > +       priv->regmap = device_node_to_regmap(priv->dev->of_node);
> > >
> > > This is sad. Why do we need to make a syscon? Can we instead use the
> > > auxiliary bus to make a reset device that either gets a regmap made here
> > > in this driver or uses a void __iomem * mapped with ioremap
> > > (priv->base)?
> > 
> > In my original code the clock driver just registers the resets too
> > similar to other combined clock and reset drivers. I wonder what you
> > think about that approach:
> > https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
> > and
> > https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
> 
> I think we should use auxiliary bus and split the driver logically into
> a reset driver in drivers/reset and a clk driver in drivers/clk. That
> way the appropriate maintainers can review the code. There is only one
> platform device with a single reg property and node in DT, but there are
> two drivers. 

Yes, I agree that the reset driver and the clock driver should be split.
However, I think using auxiliary bus is a little bit complicated in this
case, because the reset is not a part of functionality of the clock in 
JH7110. They just share a common register base address. I think it is 
better to use ioremap for the same address, and the dt will be like

syscrg_clk: clock-controller@13020000 {
	compatible = "starfive,jh7110-clkgen-sys";
	reg = <0x0 0x13020000 0x0 0x10000>;
	...
};
syscrg_rst: reset-controller@13020000 {
	compatible = "starfive,jh7110-reset-sys";
	reg = <0x0 0x13020000 0x0 0x10000>;
	...
};

What do you think of this approach? I would appreciate your suggestions.

Best regards,
Hal

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Conor Dooley]

On 23 October 2022 05:11:41 IST, Hal Feng <hal.feng@linux.starfivetech.com> wrote:
>On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
>> Quoting Emil Renner Berthing (2022-10-05 06:14:44)
>> > > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
>> > > >         if (!priv)
>> > > >                 return -ENOMEM;
>> > > >
>> > > > -       spin_lock_init(&priv->rmw_lock);
>> > > >         priv->dev = &pdev->dev;
>> > > > -       priv->base = devm_platform_ioremap_resource(pdev, 0);
>> > > > -       if (IS_ERR(priv->base))
>> > > > -               return PTR_ERR(priv->base);
>> > > > +       priv->regmap = device_node_to_regmap(priv->dev->of_node);
>> > >
>> > > This is sad. Why do we need to make a syscon? Can we instead use the
>> > > auxiliary bus to make a reset device that either gets a regmap made here
>> > > in this driver or uses a void __iomem * mapped with ioremap
>> > > (priv->base)?
>> > 
>> > In my original code the clock driver just registers the resets too
>> > similar to other combined clock and reset drivers. I wonder what you
>> > think about that approach:
>> > https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
>> > and
>> > https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
>> 
>> I think we should use auxiliary bus and split the driver logically into
>> a reset driver in drivers/reset and a clk driver in drivers/clk. That
>> way the appropriate maintainers can review the code. There is only one
>> platform device with a single reg property and node in DT, but there are
>> two drivers. 
>
>Yes, I agree that the reset driver and the clock driver should be split.
>However, I think using auxiliary bus is a little bit complicated in this
>case, because the reset is not a part of functionality of the clock in 
>JH7110. They just share a common register base address. I think it is 
>better to use ioremap for the same address, and the dt will be like
>
>syscrg_clk: clock-controller@13020000 {
>	compatible = "starfive,jh7110-clkgen-sys";
>	reg = <0x0 0x13020000 0x0 0x10000>;
>	...
>};
>syscrg_rst: reset-controller@13020000 {
>	compatible = "starfive,jh7110-reset-sys";
>	reg = <0x0 0x13020000 0x0 0x10000>;
>	...
>};
>
>What do you think of this approach? I would appreciate your suggestions.

No, the dtb checks will all start warning for this.
Aux bus is not that difficult, you can likely copy much of what I did recently in clk-mpfs.c
>
>Best regards,
>Hal

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Hal Feng]

On Sun, 23 Oct 2022 11:25:26 +0100, Conor Dooley wrote:
> On 23 October 2022 05:11:41 IST, Hal Feng <hal.feng@linux.starfivetech.com> wrote:
> >On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> >> Quoting Emil Renner Berthing (2022-10-05 06:14:44)
> >> > > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> >> > > >         if (!priv)
> >> > > >                 return -ENOMEM;
> >> > > >
> >> > > > -       spin_lock_init(&priv->rmw_lock);
> >> > > >         priv->dev = &pdev->dev;
> >> > > > -       priv->base = devm_platform_ioremap_resource(pdev, 0);
> >> > > > -       if (IS_ERR(priv->base))
> >> > > > -               return PTR_ERR(priv->base);
> >> > > > +       priv->regmap = device_node_to_regmap(priv->dev->of_node);
> >> > >
> >> > > This is sad. Why do we need to make a syscon? Can we instead use the
> >> > > auxiliary bus to make a reset device that either gets a regmap made here
> >> > > in this driver or uses a void __iomem * mapped with ioremap
> >> > > (priv->base)?
> >> > 
> >> > In my original code the clock driver just registers the resets too
> >> > similar to other combined clock and reset drivers. I wonder what you
> >> > think about that approach:
> >> > https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
> >> > and
> >> > https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
> >> 
> >> I think we should use auxiliary bus and split the driver logically into
> >> a reset driver in drivers/reset and a clk driver in drivers/clk. That
> >> way the appropriate maintainers can review the code. There is only one
> >> platform device with a single reg property and node in DT, but there are
> >> two drivers. 
> >
> >Yes, I agree that the reset driver and the clock driver should be split.
> >However, I think using auxiliary bus is a little bit complicated in this
> >case, because the reset is not a part of functionality of the clock in 
> >JH7110. They just share a common register base address. I think it is 
> >better to use ioremap for the same address, and the dt will be like
> >
> >syscrg_clk: clock-controller@13020000 {
> >	compatible = "starfive,jh7110-clkgen-sys";
> >	reg = <0x0 0x13020000 0x0 0x10000>;
> >	...
> >};
> >syscrg_rst: reset-controller@13020000 {
> >	compatible = "starfive,jh7110-reset-sys";
> >	reg = <0x0 0x13020000 0x0 0x10000>;
> >	...
> >};
> >
> >What do you think of this approach? I would appreciate your suggestions.
> 
> No, the dtb checks will all start warning for this.
> Aux bus is not that difficult, you can likely copy much of what I did recently in clk-mpfs.c

Thanks for reminding and your helpful example.

Best regards,
Hal

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Stephen Boyd]

Quoting Hal Feng (2022-10-22 21:11:41)
> On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> > I think we should use auxiliary bus and split the driver logically into
> > a reset driver in drivers/reset and a clk driver in drivers/clk. That
> > way the appropriate maintainers can review the code. There is only one
> > platform device with a single reg property and node in DT, but there are
> > two drivers. 
> 
> Yes, I agree that the reset driver and the clock driver should be split.
> However, I think using auxiliary bus is a little bit complicated in this
> case, because the reset is not a part of functionality of the clock in 
> JH7110. They just share a common register base address.

That is why auxiliary bus exists.

> I think it is 
> better to use ioremap for the same address, and the dt will be like
> 
> syscrg_clk: clock-controller@13020000 {
>         compatible = "starfive,jh7110-clkgen-sys";
>         reg = <0x0 0x13020000 0x0 0x10000>;
>         ...
> };
> syscrg_rst: reset-controller@13020000 {
>         compatible = "starfive,jh7110-reset-sys";
>         reg = <0x0 0x13020000 0x0 0x10000>;
>         ...
> };
> 
> What do you think of this approach? I would appreciate your suggestions.
> 

We shouldn't have two different nodes with the same reg property. Please
ioremap in whatever driver probes and creates the auxiliary device(s)
and then pass the void __iomem * to it.

Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Hal Feng]

On Wed, 26 Oct 2022 18:26:03 -0700, Stephen Boyd wrote:
> Quoting Hal Feng (2022-10-22 21:11:41)
> > On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
> > > I think we should use auxiliary bus and split the driver logically into
> > > a reset driver in drivers/reset and a clk driver in drivers/clk. That
> > > way the appropriate maintainers can review the code. There is only one
> > > platform device with a single reg property and node in DT, but there are
> > > two drivers. 
> > 
> > Yes, I agree that the reset driver and the clock driver should be split.
> > However, I think using auxiliary bus is a little bit complicated in this
> > case, because the reset is not a part of functionality of the clock in 
> > JH7110. They just share a common register base address.
> 
> That is why auxiliary bus exists.
> 
> > I think it is 
> > better to use ioremap for the same address, and the dt will be like
> > 
> > syscrg_clk: clock-controller@13020000 {
> >         compatible = "starfive,jh7110-clkgen-sys";
> >         reg = <0x0 0x13020000 0x0 0x10000>;
> >         ...
> > };
> > syscrg_rst: reset-controller@13020000 {
> >         compatible = "starfive,jh7110-reset-sys";
> >         reg = <0x0 0x13020000 0x0 0x10000>;
> >         ...
> > };
> > 
> > What do you think of this approach? I would appreciate your suggestions.
> > 
> 
> We shouldn't have two different nodes with the same reg property. Please
> ioremap in whatever driver probes and creates the auxiliary device(s)
> and then pass the void __iomem * to it.

Okay, I will use auxiliary bus for clock and reset driver on the next version.

Best regards,
Hal

[PATCH v1 16/30] dt-bindings: clock: Add StarFive JH7110 system clock definitions

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add all clock outputs for the StarFive JH7110 system clock generator.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../dt-bindings/clock/starfive-jh7110-sys.h   | 215 ++++++++++++++++++
 1 file changed, 215 insertions(+)
 create mode 100644 include/dt-bindings/clock/starfive-jh7110-sys.h

diff --git a/include/dt-bindings/clock/starfive-jh7110-sys.h b/include/dt-bindings/clock/starfive-jh7110-sys.h
new file mode 100644
index 000000000000..d1186abd732b
--- /dev/null
+++ b/include/dt-bindings/clock/starfive-jh7110-sys.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__
+
+#define JH7110_SYSCLK_CPU_ROOT			  0
+#define JH7110_SYSCLK_CPU_CORE			  1
+#define JH7110_SYSCLK_CPU_BUS			  2
+#define JH7110_SYSCLK_GPU_ROOT			  3
+#define JH7110_SYSCLK_PERH_ROOT			  4
+#define JH7110_SYSCLK_BUS_ROOT			  5
+#define JH7110_SYSCLK_NOCSTG_BUS		  6
+#define JH7110_SYSCLK_AXI_CFG0			  7
+#define JH7110_SYSCLK_STG_AXIAHB		  8
+#define JH7110_SYSCLK_AHB0			  9
+#define JH7110_SYSCLK_AHB1			 10
+#define JH7110_SYSCLK_APB_BUS_FUNC		 11
+#define JH7110_SYSCLK_APB0			 12
+#define JH7110_SYSCLK_PLL0_DIV2			 13
+#define JH7110_SYSCLK_PLL1_DIV2			 14
+#define JH7110_SYSCLK_PLL2_DIV2			 15
+#define JH7110_SYSCLK_AUDIO_ROOT		 16
+#define JH7110_SYSCLK_MCLK_INNER		 17
+#define JH7110_SYSCLK_MCLK			 18
+#define JH7110_SYSCLK_MCLK_OUT			 19
+#define JH7110_SYSCLK_ISP_2X			 20
+#define JH7110_SYSCLK_ISP_AXI			 21
+#define JH7110_SYSCLK_GCLK0			 22
+#define JH7110_SYSCLK_GCLK1			 23
+#define JH7110_SYSCLK_GCLK2			 24
+#define JH7110_SYSCLK_CORE			 25
+#define JH7110_SYSCLK_CORE1			 26
+#define JH7110_SYSCLK_CORE2			 27
+#define JH7110_SYSCLK_CORE3			 28
+#define JH7110_SYSCLK_CORE4			 29
+#define JH7110_SYSCLK_DEBUG			 30
+#define JH7110_SYSCLK_RTC_TOGGLE		 31
+#define JH7110_SYSCLK_TRACE0			 32
+#define JH7110_SYSCLK_TRACE1			 33
+#define JH7110_SYSCLK_TRACE2			 34
+#define JH7110_SYSCLK_TRACE3			 35
+#define JH7110_SYSCLK_TRACE4			 36
+#define JH7110_SYSCLK_TRACE_COM			 37
+#define JH7110_SYSCLK_NOC_BUS_CPU_AXI		 38
+#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI	 39
+#define JH7110_SYSCLK_OSC_DIV2			 40
+#define JH7110_SYSCLK_PLL1_DIV4			 41
+#define JH7110_SYSCLK_PLL1_DIV8			 42
+#define JH7110_SYSCLK_DDR_BUS			 43
+#define JH7110_SYSCLK_DDR_AXI			 44
+#define JH7110_SYSCLK_GPU_CORE			 45
+#define JH7110_SYSCLK_GPU_CORE_CLK		 46
+#define JH7110_SYSCLK_GPU_SYS_CLK		 47
+#define JH7110_SYSCLK_GPU_APB			 48
+#define JH7110_SYSCLK_GPU_RTC_TOGGLE		 49
+#define JH7110_SYSCLK_NOC_BUS_GPU_AXI		 50
+#define JH7110_SYSCLK_ISP_TOP_ISPCORE_2X	 51
+#define JH7110_SYSCLK_ISP_TOP_ISP_AXI		 52
+#define JH7110_SYSCLK_NOC_BUS_ISP_AXI		 53
+#define JH7110_SYSCLK_HIFI4_CORE		 54
+#define JH7110_SYSCLK_HIFI4_AXI			 55
+#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN		 56
+#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB		 57
+#define JH7110_SYSCLK_VOUT_SRC			 58
+#define JH7110_SYSCLK_VOUT_AXI			 59
+#define JH7110_SYSCLK_NOC_BUS_DISP_AXI		 60
+#define JH7110_SYSCLK_VOUT_TOP_VOUT_AHB		 61
+#define JH7110_SYSCLK_VOUT_TOP_VOUT_AXI		 62
+#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK	 63
+#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF	 64
+#define JH7110_SYSCLK_JPEGC_AXI			 65
+#define JH7110_SYSCLK_CODAJ12_AXI		 66
+#define JH7110_SYSCLK_CODAJ12_CORE		 67
+#define JH7110_SYSCLK_CODAJ12_APB		 68
+#define JH7110_SYSCLK_VDEC_AXI			 69
+#define JH7110_SYSCLK_WAVE511_AXI		 70
+#define JH7110_SYSCLK_WAVE511_BPU		 71
+#define JH7110_SYSCLK_WAVE511_VCE		 72
+#define JH7110_SYSCLK_WAVE511_APB		 73
+#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG		 74
+#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN		 75
+#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI		 76
+#define JH7110_SYSCLK_VENC_AXI			 77
+#define JH7110_SYSCLK_WAVE420L_AXI		 78
+#define JH7110_SYSCLK_WAVE420L_BPU		 79
+#define JH7110_SYSCLK_WAVE420L_VCE		 80
+#define JH7110_SYSCLK_WAVE420L_APB		 81
+#define JH7110_SYSCLK_NOC_BUS_VENC_AXI		 82
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV	 83
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN		 84
+#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4	 85
+#define JH7110_SYSCLK_AXIMEM2_128B_AXI		 86
+#define JH7110_SYSCLK_QSPI_AHB			 87
+#define JH7110_SYSCLK_QSPI_APB			 88
+#define JH7110_SYSCLK_QSPI_REF_SRC		 89
+#define JH7110_SYSCLK_QSPI_REF			 90
+#define JH7110_SYSCLK_SDIO0_AHB			 91
+#define JH7110_SYSCLK_SDIO1_AHB			 92
+#define JH7110_SYSCLK_SDIO0_SDCARD		 93
+#define JH7110_SYSCLK_SDIO1_SDCARD		 94
+#define JH7110_SYSCLK_USB_125M			 95
+#define JH7110_SYSCLK_NOC_BUS_STG_AXI		 96
+#define JH7110_SYSCLK_GMAC1_AHB			 97
+#define JH7110_SYSCLK_GMAC1_AXI			 98
+#define JH7110_SYSCLK_GMAC_SRC			 99
+#define JH7110_SYSCLK_GMAC1_GTXCLK		100
+#define JH7110_SYSCLK_GMAC1_RMII_RTX		101
+#define JH7110_SYSCLK_GMAC1_PTP			102
+#define JH7110_SYSCLK_GMAC1_RX			103
+#define JH7110_SYSCLK_GMAC1_RX_INV		104
+#define JH7110_SYSCLK_GMAC1_TX			105
+#define JH7110_SYSCLK_GMAC1_TX_INV		106
+#define JH7110_SYSCLK_GMAC1_GTXC		107
+#define JH7110_SYSCLK_GMAC0_GTXCLK		108
+#define JH7110_SYSCLK_GMAC0_PTP			109
+#define JH7110_SYSCLK_GMAC_PHY			110
+#define JH7110_SYSCLK_GMAC0_GTXC		111
+#define JH7110_SYSCLK_IOMUX			112
+#define JH7110_SYSCLK_MAILBOX			113
+#define JH7110_SYSCLK_INT_CTRL_APB		114
+#define JH7110_SYSCLK_CAN0_APB			115
+#define JH7110_SYSCLK_CAN0_TIMER		116
+#define JH7110_SYSCLK_CAN0_CAN			117
+#define JH7110_SYSCLK_CAN1_APB			118
+#define JH7110_SYSCLK_CAN1_TIMER		119
+#define JH7110_SYSCLK_CAN1_CAN			120
+#define JH7110_SYSCLK_PWM_APB			121
+#define JH7110_SYSCLK_WDT_APB			122
+#define JH7110_SYSCLK_WDT_CORE			123
+#define JH7110_SYSCLK_TIMER_APB			124
+#define JH7110_SYSCLK_TIMER0			125
+#define JH7110_SYSCLK_TIMER1			126
+#define JH7110_SYSCLK_TIMER2			127
+#define JH7110_SYSCLK_TIMER3			128
+#define JH7110_SYSCLK_TEMP_APB			129
+#define JH7110_SYSCLK_TEMP_CORE			130
+#define JH7110_SYSCLK_SPI0_APB			131
+#define JH7110_SYSCLK_SPI1_APB			132
+#define JH7110_SYSCLK_SPI2_APB			133
+#define JH7110_SYSCLK_SPI3_APB			134
+#define JH7110_SYSCLK_SPI4_APB			135
+#define JH7110_SYSCLK_SPI5_APB			136
+#define JH7110_SYSCLK_SPI6_APB			137
+#define JH7110_SYSCLK_I2C0_APB			138
+#define JH7110_SYSCLK_I2C1_APB			139
+#define JH7110_SYSCLK_I2C2_APB			140
+#define JH7110_SYSCLK_I2C3_APB			141
+#define JH7110_SYSCLK_I2C4_APB			142
+#define JH7110_SYSCLK_I2C5_APB			143
+#define JH7110_SYSCLK_I2C6_APB			144
+#define JH7110_SYSCLK_UART0_APB			145
+#define JH7110_SYSCLK_UART0_CORE		146
+#define JH7110_SYSCLK_UART1_APB			147
+#define JH7110_SYSCLK_UART1_CORE		148
+#define JH7110_SYSCLK_UART2_APB			149
+#define JH7110_SYSCLK_UART2_CORE		150
+#define JH7110_SYSCLK_UART3_APB			151
+#define JH7110_SYSCLK_UART3_CORE		152
+#define JH7110_SYSCLK_UART4_APB			153
+#define JH7110_SYSCLK_UART4_CORE		154
+#define JH7110_SYSCLK_UART5_APB			155
+#define JH7110_SYSCLK_UART5_CORE		156
+#define JH7110_SYSCLK_PWMDAC_APB		157
+#define JH7110_SYSCLK_PWMDAC_CORE		158
+#define JH7110_SYSCLK_SPDIF_APB			159
+#define JH7110_SYSCLK_SPDIF_CORE		160
+#define JH7110_SYSCLK_I2STX0_APB		161
+#define JH7110_SYSCLK_I2STX0_BCLK_MST		162
+#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV	163
+#define JH7110_SYSCLK_I2STX0_LRCK_MST		164
+#define JH7110_SYSCLK_I2STX0_BCLK		165
+#define JH7110_SYSCLK_I2STX0_BCLK_INV		166
+#define JH7110_SYSCLK_I2STX0_LRCK		167
+#define JH7110_SYSCLK_I2STX1_APB		168
+#define JH7110_SYSCLK_I2STX1_BCLK_MST		169
+#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV	170
+#define JH7110_SYSCLK_I2STX1_LRCK_MST		171
+#define JH7110_SYSCLK_I2STX1_BCLK		172
+#define JH7110_SYSCLK_I2STX1_BCLK_INV		173
+#define JH7110_SYSCLK_I2STX1_LRCK		174
+#define JH7110_SYSCLK_I2SRX_APB			175
+#define JH7110_SYSCLK_I2SRX_BCLK_MST		176
+#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV	177
+#define JH7110_SYSCLK_I2SRX_LRCK_MST		178
+#define JH7110_SYSCLK_I2SRX_BCLK		179
+#define JH7110_SYSCLK_I2SRX_BCLK_INV		180
+#define JH7110_SYSCLK_I2SRX_LRCK		181
+#define JH7110_SYSCLK_PDM_DMIC			182
+#define JH7110_SYSCLK_PDM_APB			183
+#define JH7110_SYSCLK_TDM_AHB			184
+#define JH7110_SYSCLK_TDM_APB			185
+#define JH7110_SYSCLK_TDM_INTERNAL		186
+#define JH7110_SYSCLK_TDM_CLK_TDM		187
+#define JH7110_SYSCLK_TDM_CLK_TDM_N		188
+#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG	189
+
+#define JH7110_SYSCLK_PLL0_OUT			190
+#define JH7110_SYSCLK_PLL1_OUT			191
+#define JH7110_SYSCLK_PLL2_OUT			192
+#define JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK	193
+#define JH7110_SYSCLK_U2_PCLK_MUX_PCLK		194
+#define JH7110_SYSCLK_APB_BUS			195
+#define JH7110_SYSCLK_AXI_CFG1			196
+#define JH7110_SYSCLK_APB12			197
+#define JH7110_SYSCLK_VOUT_ROOT			198
+#define JH7110_SYSCLK_VENC_ROOT			199
+#define JH7110_SYSCLK_VDEC_ROOT			200
+#define JH7110_SYSCLK_GMACUSB_ROOT		201
+
+#define JH7110_SYSCLK_END			202
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__ */
-- 
2.17.1

[PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add bindings for the system clock generator on the JH7110
RISC-V SoC by StarFive Technology Ltd.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../clock/starfive,jh7110-clkgen-sys.yaml     | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
new file mode 100644
index 000000000000..290b730145ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-sys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 System Clock Generator
+
+maintainers:
+  - Emil Renner Berthing <kernel@esmil.dk>
+  - Xingyu Wu <xingyu.wu@linux.starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-clkgen-sys
+
+  clocks:
+    items:
+      - description: Main Oscillator (24 MHz)
+      - description: RMII reference clock
+      - description: RGMII RX clock
+      - description: I2S TX bit clock
+      - description: I2S TX left/right clock
+      - description: I2S RX bit clock
+      - description: I2S RX left/right clock
+      - description: TDM
+      - description: mclk
+
+  clock-names:
+    items:
+      - const: osc
+      - const: gmac1_rmii_refin
+      - const: gmac1_rgmii_rxin
+      - const: i2stx_bclk_ext
+      - const: i2stx_lrck_ext
+      - const: i2srx_bclk_ext
+      - const: i2srx_lrck_ext
+      - const: tdm_ext
+      - const: mclk_ext
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices.
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    syscrg_clk: clock-controller@13020000 {
+        compatible = "starfive,jh7110-clkgen-sys";
+        clocks = <&osc>, <&gmac1_rmii_refin>,
+                 <&gmac1_rgmii_rxin>,
+                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+                 <&tdm_ext>, <&mclk_ext>;
+        clock-names = "osc", "gmac1_rmii_refin",
+                      "gmac1_rgmii_rxin",
+                      "i2stx_bclk_ext", "i2stx_lrck_ext",
+                      "i2srx_bclk_ext", "i2srx_lrck_ext",
+                      "tdm_ext", "mclk_ext";
+        #clock-cells = <1>;
+    };
-- 
2.17.1

Re: [PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings

[Rob Herring]

On Fri, 30 Sep 2022 06:26:47 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add bindings for the system clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../clock/starfive,jh7110-clkgen-sys.yaml     | 69 +++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.example.dts:18.47-31.11: Warning (unit_address_vs_reg): /example-0/clock-controller@13020000: node has a unit name, but no reg or ranges property

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings

[Krzysztof Kozlowski]

On 30/09/2022 00:26, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add bindings for the system clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>

(...)

> +  '#clock-cells':
> +    const: 1
> +    description:
> +      See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices.
> +
> +required:
> +  - compatible
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    syscrg_clk: clock-controller@13020000 {

Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).

> +        compatible = "starfive,jh7110-clkgen-sys";
> +        clocks = <&osc>, <&gmac1_rmii_refin>,
> +                 <&gmac1_rgmii_rxin>,
> +                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> +                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> +                 <&tdm_ext>, <&mclk_ext>;
> +        clock-names = "osc", "gmac1_rmii_refin",
> +                      "gmac1_rgmii_rxin",
> +                      "i2stx_bclk_ext", "i2stx_lrck_ext",
> +                      "i2srx_bclk_ext", "i2srx_lrck_ext",
> +                      "tdm_ext", "mclk_ext";
> +        #clock-cells = <1>;
> +    };

Best regards,
Krzysztof

Re: [PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings

[Hal Feng]

On Fri, 30 Sep 2022 12:58:12 +0200, Krzysztof Kozlowski wrote:
> On 30/09/2022 00:26, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> > 
> > Add bindings for the system clock generator on the JH7110
> > RISC-V SoC by StarFive Technology Ltd.
> > 
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> 
> (...)
> 
> > +  '#clock-cells':
> > +    const: 1
> > +    description:
> > +      See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices.
> > +
> > +required:
> > +  - compatible
> > +  - clocks
> > +  - clock-names
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    syscrg_clk: clock-controller@13020000 {
> 
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).

Will rewrite the bindings and test them. Thanks.

Best regards,
Hal

[PATCH v1 18/30] clk: starfive: Add StarFive JH7110 system clock driver

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add driver for the StarFive JH7110 system clock controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 drivers/clk/starfive/Kconfig                  |   9 +
 drivers/clk/starfive/Makefile                 |   2 +
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 648 ++++++++++++++++++
 drivers/clk/starfive/clk-starfive.h           |   2 +-
 4 files changed, 660 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 4ff61eb941c8..c13096543a8b 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -20,3 +20,12 @@ config CLK_STARFIVE_JH7100_AUDIO
 	help
 	  Say Y or M here to support the audio clocks on the StarFive JH7100
 	  SoC.
+
+config CLK_STARFIVE_JH7110_SYS
+	bool "StarFive JH7110 system clock support"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select CLK_STARFIVE
+	default SOC_STARFIVE
+	help
+	  Say yes here to support the system clock controller on the
+	  StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index ddd04595516f..2bc126cc91f2 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_STARFIVE)	+= clk-starfive.o
 
 obj-$(CONFIG_CLK_STARFIVE_JH7100)	+= clk-starfive-jh7100.o
 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)	+= clk-starfive-jh7100-audio.o
+
+obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS)	+= clk-starfive-jh7110-sys.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
new file mode 100644
index 000000000000..91ce17fae68c
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -0,0 +1,648 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 System Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive-jh7110-sys.h>
+
+#include "clk-starfive.h"
+
+/* external clocks */
+#define JH7110_SYSCLK_OSC			(JH7110_SYSCLK_END + 0)
+#define JH7110_SYSCLK_GMAC1_RMII_REFIN		(JH7110_SYSCLK_END + 1)
+#define JH7110_SYSCLK_GMAC1_RGMII_RXIN		(JH7110_SYSCLK_END + 2)
+#define JH7110_SYSCLK_I2STX_BCLK_EXT		(JH7110_SYSCLK_END + 3)
+#define JH7110_SYSCLK_I2STX_LRCK_EXT		(JH7110_SYSCLK_END + 4)
+#define JH7110_SYSCLK_I2SRX_BCLK_EXT		(JH7110_SYSCLK_END + 5)
+#define JH7110_SYSCLK_I2SRX_LRCK_EXT		(JH7110_SYSCLK_END + 6)
+#define JH7110_SYSCLK_TDM_EXT			(JH7110_SYSCLK_END + 7)
+#define JH7110_SYSCLK_MCLK_EXT			(JH7110_SYSCLK_END + 8)
+
+static const struct starfive_clk_data jh7110_sysclk_data[] __initconst = {
+	/* root */
+	STARFIVE__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
+		      JH7110_SYSCLK_OSC,
+		      JH7110_SYSCLK_PLL0_OUT),
+	STARFIVE__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7,
+		      JH7110_SYSCLK_CPU_ROOT),
+	STARFIVE__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
+		      JH7110_SYSCLK_PLL2_OUT,
+		      JH7110_SYSCLK_PLL1_OUT),
+	STARFIVE_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
+		      JH7110_SYSCLK_PLL0_OUT,
+		      JH7110_SYSCLK_PLL2_OUT),
+	STARFIVE__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
+		      JH7110_SYSCLK_OSC,
+		      JH7110_SYSCLK_PLL2_OUT),
+	STARFIVE__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3,
+		      JH7110_SYSCLK_BUS_ROOT),
+	STARFIVE__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3,
+		      JH7110_SYSCLK_BUS_ROOT),
+	STARFIVE__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2,
+		      JH7110_SYSCLK_AXI_CFG0),
+	STARFIVE_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL,
+		      JH7110_SYSCLK_STG_AXIAHB),
+	STARFIVE_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL,
+		      JH7110_SYSCLK_STG_AXIAHB),
+	STARFIVE__DIV(JH7110_SYSCLK_APB_BUS_FUNC, "apb_bus_func", 8,
+		      JH7110_SYSCLK_STG_AXIAHB),
+	STARFIVE_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB_BUS),
+	STARFIVE__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2,
+		      JH7110_SYSCLK_PLL0_OUT),
+	STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2,
+		      JH7110_SYSCLK_PLL1_OUT),
+	STARFIVE__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2,
+		      JH7110_SYSCLK_PLL2_OUT),
+	STARFIVE__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8,
+		      JH7110_SYSCLK_PLL2_OUT),
+	STARFIVE__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64,
+		      JH7110_SYSCLK_AUDIO_ROOT),
+	STARFIVE__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
+		      JH7110_SYSCLK_MCLK_INNER,
+		      JH7110_SYSCLK_MCLK_EXT),
+	STARFIVE_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0,
+		      JH7110_SYSCLK_MCLK_INNER),
+	STARFIVE_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
+		      JH7110_SYSCLK_PLL2_OUT,
+		      JH7110_SYSCLK_PLL1_OUT),
+	STARFIVE__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4,
+		      JH7110_SYSCLK_ISP_2X),
+	STARFIVE_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62,
+		      JH7110_SYSCLK_PLL0_DIV2),
+	STARFIVE_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62,
+		      JH7110_SYSCLK_PLL1_DIV2),
+	STARFIVE_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62,
+		      JH7110_SYSCLK_PLL2_DIV2),
+	/* cores */
+	STARFIVE_GATE(JH7110_SYSCLK_CORE, "core_clk", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_CORE1, "core_clk1", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_CORE2, "core_clk2", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_CORE3, "core_clk3", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_CORE4, "core_clk4", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_DEBUG, "debug_clk", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_BUS),
+	STARFIVE__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_TRACE0, "trace_clk0", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_TRACE1, "trace_clk1", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_TRACE2, "trace_clk2", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_TRACE3, "trace_clk3", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_TRACE4, "trace_clk4", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_CPU_BUS),
+	/* noc */
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi",
+		      CLK_IS_CRITICAL,
+		      JH7110_SYSCLK_CPU_BUS),
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi",
+		      CLK_IS_CRITICAL,
+		      JH7110_SYSCLK_AXI_CFG0),
+	/* ddr */
+	STARFIVE__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2,
+		      JH7110_SYSCLK_PLL1_DIV2),
+	STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2,
+		      JH7110_SYSCLK_PLL1_DIV4),
+	STARFIVE__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
+		      JH7110_SYSCLK_OSC_DIV2,
+		      JH7110_SYSCLK_PLL1_DIV2,
+		      JH7110_SYSCLK_PLL1_DIV4,
+		      JH7110_SYSCLK_PLL1_DIV8),
+	STARFIVE_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_DDR_BUS),
+	/* gpu */
+	STARFIVE__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7,
+		      JH7110_SYSCLK_GPU_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0,
+		      JH7110_SYSCLK_GPU_CORE),
+	STARFIVE_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0,
+		      JH7110_SYSCLK_AXI_CFG1),
+	STARFIVE_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0,
+		      JH7110_SYSCLK_GPU_CORE),
+	/* isp */
+	STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_ISPCORE_2X,
+		      "isp_top_ispcore_2x", 0,
+		      JH7110_SYSCLK_ISP_2X),
+	STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_ISP_AXI, "isp_top_isp_axi", 0,
+		      JH7110_SYSCLK_ISP_AXI),
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_ISP_AXI),
+	/* hifi4 */
+	STARFIVE__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15,
+		      JH7110_SYSCLK_BUS_ROOT),
+	STARFIVE__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2,
+		      JH7110_SYSCLK_HIFI4_CORE),
+	/* axi_cfg1_dec */
+	STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_DEC_MAIN, "axi_cfg1_dec_main",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AXI_CFG1),
+	STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_DEC_AHB, "cfg1_dec_ahb",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AHB0),
+	/* vout */
+	STARFIVE_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0,
+		      JH7110_SYSCLK_VOUT_ROOT),
+	STARFIVE__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7,
+		      JH7110_SYSCLK_VOUT_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0,
+		      JH7110_SYSCLK_VOUT_AXI),
+	STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_VOUT_AHB, "vout_top_vout_ahb", 0,
+		      JH7110_SYSCLK_AHB1),
+	STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_VOUT_AXI, "vout_top_vout_axi", 0,
+		      JH7110_SYSCLK_VOUT_AXI),
+	STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK,
+		      "vout_top_hdmitx0_mclk", 0,
+		      JH7110_SYSCLK_MCLK),
+	STARFIVE__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF,
+		      "vout_top_mipiphy_ref", 2,
+		      JH7110_SYSCLK_OSC),
+	/* jpegc */
+	STARFIVE__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16,
+		      JH7110_SYSCLK_VENC_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_AXI, "CODAJ12_axi", 0,
+		      JH7110_SYSCLK_JPEGC_AXI),
+	STARFIVE_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "CODAJ12_core", 0, 16,
+		      JH7110_SYSCLK_VENC_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_APB, "CODAJ12_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	/* vdec */
+	STARFIVE__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7,
+		      JH7110_SYSCLK_BUS_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_WAVE511_AXI, "WAVE511_axi", 0,
+		      JH7110_SYSCLK_VDEC_AXI),
+	STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_BPU, "WAVE511_bpu", 0, 7,
+		      JH7110_SYSCLK_BUS_ROOT),
+	STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_VCE, "WAVE511_vce", 0, 7,
+		      JH7110_SYSCLK_VDEC_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_WAVE511_APB, "WAVE511_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_VDEC_JPG_ARB_JPG, "vdec_jpg_arb_jpg",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_JPEGC_AXI),
+	STARFIVE_GATE(JH7110_SYSCLK_VDEC_JPG_ARB_MAIN, "vdec_jpg_arb_main",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_VDEC_AXI),
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0,
+		      JH7110_SYSCLK_VDEC_AXI),
+	/* venc */
+	STARFIVE__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15,
+		      JH7110_SYSCLK_VENC_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0,
+		      JH7110_SYSCLK_VENC_AXI),
+	STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15,
+		      JH7110_SYSCLK_VENC_ROOT),
+	STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15,
+		      JH7110_SYSCLK_VENC_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0,
+		      JH7110_SYSCLK_VENC_AXI),
+	/* intmem */
+	STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV,
+		      "axi_cfg0_dec_main_div", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AHB1),
+	STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_DEC_MAIN, "axi_cfg0_dec_main",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AXI_CFG0),
+	STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4, "axi_cfg0_dec_hifi4",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_HIFI4_AXI),
+	STARFIVE_GATE(JH7110_SYSCLK_AXIMEM2_128B_AXI, "aximem2_128b_axi",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AXI_CFG0),
+	/* qspi */
+	STARFIVE_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AHB1),
+	STARFIVE_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16,
+		      JH7110_SYSCLK_GMACUSB_ROOT),
+	STARFIVE_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", CLK_IGNORE_UNUSED, 2,
+		      JH7110_SYSCLK_OSC,
+		      JH7110_SYSCLK_QSPI_REF_SRC),
+	/* sdio */
+	STARFIVE_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AHB0),
+	STARFIVE_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_AHB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard",
+		      CLK_IGNORE_UNUSED, 15,
+		      JH7110_SYSCLK_AXI_CFG0),
+	STARFIVE_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard",
+		      CLK_IGNORE_UNUSED, 15,
+		      JH7110_SYSCLK_AXI_CFG0),
+	/* stg */
+	STARFIVE__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15,
+		      JH7110_SYSCLK_GMACUSB_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_NOCSTG_BUS),
+	/* gmac1 */
+	STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0,
+		      JH7110_SYSCLK_AHB0),
+	STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0,
+		      JH7110_SYSCLK_STG_AXIAHB),
+	STARFIVE__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7,
+		      JH7110_SYSCLK_GMACUSB_ROOT),
+	STARFIVE__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15,
+		      JH7110_SYSCLK_GMACUSB_ROOT),
+	STARFIVE__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
+		      JH7110_SYSCLK_GMAC1_RMII_REFIN),
+	STARFIVE_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31,
+		      JH7110_SYSCLK_GMAC_SRC),
+	STARFIVE__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
+		      JH7110_SYSCLK_GMAC1_RGMII_RXIN,
+		      JH7110_SYSCLK_GMAC1_RMII_RTX),
+	STARFIVE__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv",
+		      JH7110_SYSCLK_GMAC1_RX),
+	STARFIVE_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", 0, 2,
+		      JH7110_SYSCLK_GMAC1_GTXCLK,
+		      JH7110_SYSCLK_GMAC1_RMII_RTX),
+	STARFIVE__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv",
+		      JH7110_SYSCLK_GMAC1_TX),
+	STARFIVE_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0,
+		      JH7110_SYSCLK_GMAC1_GTXCLK),
+	/* gmac0 */
+	STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15,
+		      JH7110_SYSCLK_GMACUSB_ROOT),
+	STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31,
+		      JH7110_SYSCLK_GMAC_SRC),
+	STARFIVE_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31,
+		      JH7110_SYSCLK_GMAC_SRC),
+	STARFIVE__DIV(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 32,
+		      JH7110_SYSCLK_GMAC0_GTXCLK),
+	/* sys misc */
+	STARFIVE_GATE(JH7110_SYSCLK_IOMUX, "iomux_pclk", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_MAILBOX, "mailbox_apb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB12),
+	/* can0 */
+	STARFIVE_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63,
+		      JH7110_SYSCLK_PERH_ROOT),
+	/* can1 */
+	STARFIVE_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63,
+		      JH7110_SYSCLK_PERH_ROOT),
+	/* pwm */
+	STARFIVE_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	/* wdt */
+	STARFIVE_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_OSC),
+	/* timer */
+	STARFIVE_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_TIMER0, "timer0_clk", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_TIMER1, "timer1_clk", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_TIMER2, "timer2_clk", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_TIMER3, "timer3_clk", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_OSC),
+	/* temp sensor */
+	STARFIVE_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24,
+		      JH7110_SYSCLK_OSC),
+	/* spi */
+	STARFIVE_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	/* i2c */
+	STARFIVE_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	STARFIVE_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0,
+		      JH7110_SYSCLK_APB12),
+	/* uart */
+	STARFIVE_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core",
+		      CLK_IGNORE_UNUSED,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0,
+		      JH7110_SYSCLK_OSC),
+	STARFIVE_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10,
+		      JH7110_SYSCLK_PERH_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10,
+		      JH7110_SYSCLK_PERH_ROOT),
+	STARFIVE_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10,
+		      JH7110_SYSCLK_PERH_ROOT),
+	/* pwmdac */
+	STARFIVE_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256,
+		      JH7110_SYSCLK_AUDIO_ROOT),
+	/* spdif */
+	STARFIVE_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0,
+		      JH7110_SYSCLK_MCLK),
+	/* i2stx0 */
+	STARFIVE_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32,
+		      JH7110_SYSCLK_MCLK),
+	STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
+		      JH7110_SYSCLK_I2STX0_BCLK_MST),
+	STARFIVE_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
+		      JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
+		      JH7110_SYSCLK_I2STX0_BCLK_MST),
+	STARFIVE__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk",	2,
+		      JH7110_SYSCLK_I2STX0_BCLK_MST,
+		      JH7110_SYSCLK_I2STX_BCLK_EXT),
+	STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv",
+		      JH7110_SYSCLK_I2STX0_BCLK),
+	STARFIVE__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
+		      JH7110_SYSCLK_I2STX0_LRCK_MST,
+		      JH7110_SYSCLK_I2STX_LRCK_EXT),
+	/* i2stx1 */
+	STARFIVE_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32,
+		      JH7110_SYSCLK_MCLK),
+	STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
+		      JH7110_SYSCLK_I2STX1_BCLK_MST),
+	STARFIVE_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
+		      JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
+		      JH7110_SYSCLK_I2STX1_BCLK_MST),
+	STARFIVE__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
+		      JH7110_SYSCLK_I2STX1_BCLK_MST,
+		      JH7110_SYSCLK_I2STX_BCLK_EXT),
+	STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv",
+		      JH7110_SYSCLK_I2STX1_BCLK),
+	STARFIVE__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
+		      JH7110_SYSCLK_I2STX1_LRCK_MST,
+		      JH7110_SYSCLK_I2STX_LRCK_EXT),
+	/* i2srx */
+	STARFIVE_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32,
+		      JH7110_SYSCLK_MCLK),
+	STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
+		      JH7110_SYSCLK_I2SRX_BCLK_MST),
+	STARFIVE_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
+		      JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
+		      JH7110_SYSCLK_I2SRX_BCLK_MST),
+	STARFIVE__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
+		      JH7110_SYSCLK_I2SRX_BCLK_MST,
+		      JH7110_SYSCLK_I2SRX_BCLK_EXT),
+	STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv",
+		      JH7110_SYSCLK_I2SRX_BCLK),
+	STARFIVE__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
+		      JH7110_SYSCLK_I2SRX_LRCK_MST,
+		      JH7110_SYSCLK_I2SRX_LRCK_EXT),
+	/* pdm */
+	STARFIVE_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64,
+		      JH7110_SYSCLK_MCLK),
+	STARFIVE_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	/* tdm */
+	STARFIVE_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0,
+		      JH7110_SYSCLK_AHB0),
+	STARFIVE_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0,
+		      JH7110_SYSCLK_APB0),
+	STARFIVE_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64,
+		      JH7110_SYSCLK_MCLK),
+	STARFIVE__MUX(JH7110_SYSCLK_TDM_CLK_TDM, "tdm_clk_tdm", 2,
+		      JH7110_SYSCLK_TDM_INTERNAL,
+		      JH7110_SYSCLK_TDM_EXT),
+	STARFIVE__INV(JH7110_SYSCLK_TDM_CLK_TDM_N, "tdm_clk_tdm_n",
+		      JH7110_SYSCLK_TDM_CLK_TDM),
+	/* jtag */
+	STARFIVE__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG,
+		      "jtag_certification_trng", 4,
+		      JH7110_SYSCLK_OSC),
+};
+
+static const struct {
+	const char *name;
+	const char *parent;
+	unsigned int mul;
+	unsigned int div;
+} jh7110_fixed_factor_clocks[JH7110_SYSCLK_END - JH7110_SYSCLK_PLL0_OUT] __initconst = {
+	[JH7110_SYSCLK_PLL0_OUT - JH7110_SYSCLK_PLL0_OUT] = {
+		"pll0_out", "osc", 625, 12 /* 24MHz -> 1250.0MHz */
+	},
+	[JH7110_SYSCLK_PLL1_OUT - JH7110_SYSCLK_PLL0_OUT] = {
+		"pll1_out", "osc", 533, 12 /* 24MHz -> 1066.0MHz */
+	},
+	[JH7110_SYSCLK_PLL2_OUT - JH7110_SYSCLK_PLL0_OUT] = {
+		"pll2_out", "osc", 256,  5 /* 24MHz -> 1228.8MHz */
+	},
+	[JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK - JH7110_SYSCLK_PLL0_OUT] = {
+		"u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1
+	},
+	[JH7110_SYSCLK_U2_PCLK_MUX_PCLK - JH7110_SYSCLK_PLL0_OUT] = {
+		"u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1
+	},
+	[JH7110_SYSCLK_APB_BUS - JH7110_SYSCLK_PLL0_OUT] = {
+		"apb_bus", "u2_pclk_mux_pclk", 1, 1
+	},
+	[JH7110_SYSCLK_AXI_CFG1 - JH7110_SYSCLK_PLL0_OUT] = {
+		"axi_cfg1", "isp_axi", 1, 1
+	},
+	[JH7110_SYSCLK_APB12 - JH7110_SYSCLK_PLL0_OUT] = {
+		"apb12", "apb_bus", 1, 1
+	},
+	[JH7110_SYSCLK_VOUT_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+		"vout_root", "pll2_out", 1, 1
+	},
+	[JH7110_SYSCLK_VENC_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+		"venc_root", "pll2_out", 1, 1
+	},
+	[JH7110_SYSCLK_VDEC_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+		"vdec_root", "pll0_out", 1, 1
+	},
+	[JH7110_SYSCLK_GMACUSB_ROOT - JH7110_SYSCLK_PLL0_OUT] = {
+		"gmacusb_root", "pll0_out", 1, 1
+	},
+};
+
+static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct starfive_clk_priv *priv = data;
+	unsigned int idx = clkspec->args[0];
+
+	if (idx < JH7110_SYSCLK_PLL0_OUT)
+		return &priv->reg[idx].hw;
+
+	if (idx < JH7110_SYSCLK_END)
+		return priv->pll[idx - JH7110_SYSCLK_PLL0_OUT];
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int __init jh7110_syscrg_probe(struct platform_device *pdev)
+{
+	struct starfive_clk_priv *priv;
+	unsigned int idx;
+	int i, ret;
+
+	priv = devm_kzalloc(&pdev->dev,
+			    struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+
+	priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
+	if (IS_ERR(priv->regmap)) {
+		dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+			PTR_ERR(priv->regmap));
+		return PTR_ERR(priv->regmap);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(jh7110_fixed_factor_clocks); i++) {
+		priv->pll[i] =
+			devm_clk_hw_register_fixed_factor(&pdev->dev,
+							  jh7110_fixed_factor_clocks[i].name,
+							  jh7110_fixed_factor_clocks[i].parent,
+							  0,
+							  jh7110_fixed_factor_clocks[i].mul,
+							  jh7110_fixed_factor_clocks[i].div);
+		if (IS_ERR(priv->pll[i]))
+			return PTR_ERR(priv->pll[i]);
+	}
+
+	for (idx = 0; idx < JH7110_SYSCLK_PLL0_OUT; idx++) {
+		u32 max = jh7110_sysclk_data[idx].max;
+		struct clk_parent_data parents[4] = {};
+		struct clk_init_data init = {
+			.name = jh7110_sysclk_data[idx].name,
+			.ops = starfive_clk_ops(max),
+			.parent_data = parents,
+			.num_parents =
+				((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+			.flags = jh7110_sysclk_data[idx].flags,
+		};
+		struct starfive_clk *clk = &priv->reg[idx];
+		unsigned int i;
+
+		for (i = 0; i < init.num_parents; i++) {
+			unsigned int pidx = jh7110_sysclk_data[idx].parents[i];
+
+			if (pidx < JH7110_SYSCLK_PLL0_OUT)
+				parents[i].hw = &priv->reg[pidx].hw;
+			else if (pidx < JH7110_SYSCLK_END)
+				parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
+			else if (pidx == JH7110_SYSCLK_OSC)
+				parents[i].fw_name = "osc";
+			else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN)
+				parents[i].fw_name = "gmac1_rmii_refin";
+			else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN)
+				parents[i].fw_name = "gmac1_rgmii_rxin";
+			else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT)
+				parents[i].fw_name = "i2stx_bclk_ext";
+			else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT)
+				parents[i].fw_name = "i2stx_lrck_ext";
+			else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT)
+				parents[i].fw_name = "i2srx_bclk_ext";
+			else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT)
+				parents[i].fw_name = "i2srx_lrck_ext";
+			else if (pidx == JH7110_SYSCLK_TDM_EXT)
+				parents[i].fw_name = "tdm_ext";
+			else if (pidx == JH7110_SYSCLK_MCLK_EXT)
+				parents[i].fw_name = "mclk_ext";
+		}
+
+		clk->hw.init = &init;
+		clk->idx = idx;
+		clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+		if (ret)
+			return ret;
+	}
+
+	return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);
+}
+
+static const struct of_device_id jh7110_syscrg_match[] = {
+	{ .compatible = "starfive,jh7110-clkgen-sys" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver jh7110_syscrg_driver = {
+	.driver = {
+		.name = "clk-starfive-jh7110-sys",
+		.of_match_table = jh7110_syscrg_match,
+		.suppress_bind_attrs = true,
+	},
+};
+builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe);
diff --git a/drivers/clk/starfive/clk-starfive.h b/drivers/clk/starfive/clk-starfive.h
index 99cf74e8cbde..b717bd033e26 100644
--- a/drivers/clk/starfive/clk-starfive.h
+++ b/drivers/clk/starfive/clk-starfive.h
@@ -103,7 +103,7 @@ struct starfive_clk {
 struct starfive_clk_priv {
 	struct device *dev;
 	struct regmap *regmap;
-	struct clk_hw *pll[3];
+	struct clk_hw *pll[12];
 	struct starfive_clk reg[];
 };
 
-- 
2.17.1

[PATCH v1 19/30] dt-bindings: clock: Add StarFive JH7110 always-on definitions

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add all clock outputs for the StarFive JH7110 always-on clock generator.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../dt-bindings/clock/starfive-jh7110-aon.h   | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 include/dt-bindings/clock/starfive-jh7110-aon.h

diff --git a/include/dt-bindings/clock/starfive-jh7110-aon.h b/include/dt-bindings/clock/starfive-jh7110-aon.h
new file mode 100644
index 000000000000..5f1f7f2f1533
--- /dev/null
+++ b/include/dt-bindings/clock/starfive-jh7110-aon.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_AON_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_AON_H__
+
+#define JH7110_AONCLK_OSC_DIV4			 0
+#define JH7110_AONCLK_APB_FUNC			 1
+#define JH7110_AONCLK_GMAC0_AHB			 2
+#define JH7110_AONCLK_GMAC0_AXI			 3
+#define JH7110_AONCLK_GMAC0_RMII_RTX		 4
+#define JH7110_AONCLK_GMAC0_TX			 5
+#define JH7110_AONCLK_GMAC0_TX_INV		 6
+#define JH7110_AONCLK_GMAC0_RX			 7
+#define JH7110_AONCLK_GMAC0_RX_INV		 8
+#define JH7110_AONCLK_OTPC_APB			 9
+#define JH7110_AONCLK_RTC_APB			10
+#define JH7110_AONCLK_RTC_INTERNAL		11
+#define JH7110_AONCLK_RTC_32K			12
+#define JH7110_AONCLK_RTC_CAL			13
+
+#define JH7110_AONCLK_END			14
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
-- 
2.17.1

[PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add bindings for the always-on clock generator on the JH7110
RISC-V SoC by StarFive Technology Ltd.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../clock/starfive,jh7110-clkgen-aon.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
new file mode 100644
index 000000000000..029ff57b9e3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Always-On Clock Generator
+
+maintainers:
+  - Emil Renner Berthing <kernel@esmil.dk>
+  - Xingyu Wu <xingyu.wu@linux.starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-clkgen-aon
+
+  clocks:
+    items:
+      - description: Main Oscillator
+      - description: RTC clock
+      - description: RMII reference clock
+      - description: RGMII RX clock
+      - description: STG AXI/AHB clock
+      - description: APB Bus clock
+
+  clock-names:
+    items:
+      - const: osc
+      - const: clk_rtc
+      - const: gmac0_rmii_refin
+      - const: gmac0_rgmii_rxin
+      - const: stg_axiahb
+      - const: apb_bus_func
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-aon.h> for valid indices.
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-sys.h>
+
+    aoncrg: clock-controller@17000000 {
+        compatible = "starfive,jh7110-aoncrg";
+        clocks = <&osc>, <&clk_rtc>,
+                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+                 <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>;
+        clock-names = "osc", "clk_rtc",
+                      "gmac0_rmii_refin", "gmac0_rgmii_rxin",
+                      "stg_axiahb", "apb_bus_func";
+        #clock-cells = <1>;
+    };
-- 
2.17.1

Re: [PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings

[Krzysztof Kozlowski]

On 30/09/2022 07:56, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add bindings for the always-on clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
> 

(...)

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive-jh7110-sys.h>
> +
> +    aoncrg: clock-controller@17000000 {

Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).


Best regards,
Krzysztof

Re: [PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings

[Hal Feng]

On Fri, 30 Sep 2022 12:59:01 +0200, Krzysztof Kozlowski wrote:
> On 30/09/2022 07:56, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> > 
> > Add bindings for the always-on clock generator on the JH7110
> > RISC-V SoC by StarFive Technology Ltd.
> > 
> 
> (...)
> 
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/starfive-jh7110-sys.h>
> > +
> > +    aoncrg: clock-controller@17000000 {
> 
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
Will rewrite the bindings and test them. Thanks.

Best regards,
Hal

Re: [PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings

[Rob Herring]

On Fri, Sep 30, 2022 at 01:56:32PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add bindings for the always-on clock generator on the JH7110
> RISC-V SoC by StarFive Technology Ltd.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../clock/starfive,jh7110-clkgen-aon.yaml     | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
> new file mode 100644
> index 000000000000..029ff57b9e3e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-aon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Always-On Clock Generator
> +
> +maintainers:
> +  - Emil Renner Berthing <kernel@esmil.dk>
> +  - Xingyu Wu <xingyu.wu@linux.starfivetech.com>
> +
> +properties:
> +  compatible:
> +    const: starfive,jh7110-clkgen-aon
> +
> +  clocks:
> +    items:
> +      - description: Main Oscillator
> +      - description: RTC clock
> +      - description: RMII reference clock
> +      - description: RGMII RX clock
> +      - description: STG AXI/AHB clock
> +      - description: APB Bus clock
> +
> +  clock-names:
> +    items:
> +      - const: osc
> +      - const: clk_rtc
> +      - const: gmac0_rmii_refin
> +      - const: gmac0_rgmii_rxin
> +      - const: stg_axiahb
> +      - const: apb_bus_func
> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      See <dt-bindings/clock/starfive-jh7110-aon.h> for valid indices.

No 'reg'? How do you access this h/w then? If it is part of some block, 
we need to see the full picture.

Rob

[PATCH v1 21/30] clk: starfive: Add StarFive JH7110 always-on clock driver

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add driver for the StarFive JH7110 always-on clock controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 drivers/clk/starfive/Kconfig                  |   9 +
 drivers/clk/starfive/Makefile                 |   1 +
 .../clk/starfive/clk-starfive-jh7110-aon.c    | 161 ++++++++++++++++++
 3 files changed, 171 insertions(+)
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index c13096543a8b..42aad3b553cb 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -29,3 +29,12 @@ config CLK_STARFIVE_JH7110_SYS
 	help
 	  Say yes here to support the system clock controller on the
 	  StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_AON
+	tristate "StarFive JH7110 always-on clock support"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select CLK_STARFIVE
+	default m if SOC_STARFIVE
+	help
+	  Say yes here to support the always-on clock controller on the
+	  StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 2bc126cc91f2..b54d11340704 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100)	+= clk-starfive-jh7100.o
 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)	+= clk-starfive-jh7100-audio.o
 
 obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS)	+= clk-starfive-jh7110-sys.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_AON)	+= clk-starfive-jh7110-aon.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
new file mode 100644
index 000000000000..4975e7ad67be
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Always-On Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive-jh7110-aon.h>
+
+#include "clk-starfive.h"
+
+/* external clocks */
+#define JH7110_AONCLK_OSC		(JH7110_AONCLK_END + 0)
+#define JH7110_AONCLK_RTC		(JH7110_AONCLK_END + 1)
+#define JH7110_AONCLK_GMAC0_RMII_REFIN	(JH7110_AONCLK_END + 2)
+#define JH7110_AONCLK_GMAC0_RGMII_RXIN	(JH7110_AONCLK_END + 3)
+#define JH7110_AONCLK_STG_AXIAHB	(JH7110_AONCLK_END + 4)
+#define JH7110_AONCLK_APB_BUS_FUNC	(JH7110_AONCLK_END + 5)
+#define JH7110_AONCLK_GMAC0_GTXCLK	(JH7110_AONCLK_END + 6)
+
+static const struct starfive_clk_data jh7110_aonclk_data[] = {
+	/* source */
+	STARFIVE__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4,
+		      JH7110_AONCLK_OSC),
+	STARFIVE__MUX(JH7110_AONCLK_APB_FUNC, "aon_apb_func", 2,
+		      JH7110_AONCLK_OSC_DIV4,
+		      JH7110_AONCLK_OSC),
+	/* gmac0 */
+	STARFIVE_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0,
+		      JH7110_AONCLK_STG_AXIAHB),
+	STARFIVE_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0,
+		      JH7110_AONCLK_STG_AXIAHB),
+	STARFIVE__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
+		      JH7110_AONCLK_GMAC0_RMII_REFIN),
+	STARFIVE_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", 0, 2,
+		      JH7110_AONCLK_GMAC0_GTXCLK,
+		      JH7110_AONCLK_GMAC0_RMII_RTX),
+	STARFIVE__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv",
+		      JH7110_AONCLK_GMAC0_TX),
+	STARFIVE__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
+		      JH7110_AONCLK_GMAC0_RGMII_RXIN,
+		      JH7110_AONCLK_GMAC0_RMII_RTX),
+	STARFIVE__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv",
+		      JH7110_AONCLK_GMAC0_RX),
+	/* otpc */
+	STARFIVE_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", CLK_IGNORE_UNUSED,
+		      JH7110_AONCLK_APB_BUS_FUNC),
+	/* rtc */
+	STARFIVE_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", CLK_IGNORE_UNUSED,
+		      JH7110_AONCLK_APB_BUS_FUNC),
+	STARFIVE__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022,
+		      JH7110_AONCLK_OSC),
+	STARFIVE__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
+		      JH7110_AONCLK_RTC,
+		      JH7110_AONCLK_RTC_INTERNAL),
+	STARFIVE_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0,
+		      JH7110_AONCLK_OSC),
+};
+
+static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct starfive_clk_priv *priv = data;
+	unsigned int idx = clkspec->args[0];
+
+	if (idx < JH7110_AONCLK_END)
+		return &priv->reg[idx].hw;
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_aoncrg_probe(struct platform_device *pdev)
+{
+	struct starfive_clk_priv *priv;
+	unsigned int idx;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev,
+			    struct_size(priv, reg, JH7110_AONCLK_END),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+
+	priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
+	if (IS_ERR(priv->regmap)) {
+		dev_err(priv->dev, "failed to get regmap (error %ld)\n",
+			PTR_ERR(priv->regmap));
+		return PTR_ERR(priv->regmap);
+	}
+
+	for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
+		u32 max = jh7110_aonclk_data[idx].max;
+		struct clk_parent_data parents[4] = {};
+		struct clk_init_data init = {
+			.name = jh7110_aonclk_data[idx].name,
+			.ops = starfive_clk_ops(max),
+			.parent_data = parents,
+			.num_parents = ((max & STARFIVE_CLK_MUX_MASK)
+					>> STARFIVE_CLK_MUX_SHIFT) + 1,
+			.flags = jh7110_aonclk_data[idx].flags,
+		};
+		struct starfive_clk *clk = &priv->reg[idx];
+		unsigned int i;
+
+		for (i = 0; i < init.num_parents; i++) {
+			unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
+
+			if (pidx < JH7110_AONCLK_END)
+				parents[i].hw = &priv->reg[pidx].hw;
+			else if (pidx == JH7110_AONCLK_OSC)
+				parents[i].fw_name = "osc";
+			else if (pidx == JH7110_AONCLK_RTC)
+				parents[i].fw_name = "clk_rtc";
+			else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
+				parents[i].fw_name = "gmac0_rmii_refin";
+			else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
+				parents[i].fw_name = "gmac0_rgmii_rxin";
+			else if (pidx == JH7110_AONCLK_STG_AXIAHB)
+				parents[i].fw_name = "stg_axiahb";
+			else if (pidx == JH7110_AONCLK_APB_BUS_FUNC)
+				parents[i].fw_name = "apb_bus_func";
+		}
+
+		clk->hw.init = &init;
+		clk->idx = idx;
+		clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+		if (ret)
+			return ret;
+	}
+
+	return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
+}
+
+static const struct of_device_id jh7110_aoncrg_match[] = {
+	{ .compatible = "starfive,jh7110-clkgen-aon" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
+
+static struct platform_driver jh7110_aoncrg_driver = {
+	.probe = jh7110_aoncrg_probe,
+	.driver = {
+		.name = "clk-starfive-jh7110-aon",
+		.of_match_table = jh7110_aoncrg_match,
+	},
+};
+module_platform_driver(jh7110_aoncrg_driver);
+
+MODULE_AUTHOR("Emil Renner Berthing");
+MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1

[PATCH v1 22/30] pinctrl: Create subdirectory for StarFive drivers

[Hal Feng]

From: Jianlong Huang <jianlong.huang@starfivetech.com>

Move the StarFive JH7100 pinctrl driver to a new subdirectory
in preparation for adding more StarFive pinctrl drivers. No
functional change.

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 drivers/pinctrl/Kconfig                       | 18 +-----------------
 drivers/pinctrl/Makefile                      |  2 +-
 drivers/pinctrl/starfive/Kconfig              | 19 +++++++++++++++++++
 drivers/pinctrl/starfive/Makefile             |  3 +++
 .../pinctrl/{ => starfive}/pinctrl-starfive.c |  8 ++++----
 5 files changed, 28 insertions(+), 22 deletions(-)
 create mode 100644 drivers/pinctrl/starfive/Kconfig
 create mode 100644 drivers/pinctrl/starfive/Makefile
 rename drivers/pinctrl/{ => starfive}/pinctrl-starfive.c (99%)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1cf74b0c42e5..5abf1961f4d4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -412,23 +412,6 @@ config PINCTRL_ST
 	select PINCONF
 	select GPIOLIB_IRQCHIP
 
-config PINCTRL_STARFIVE
-	tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
-	depends on SOC_STARFIVE || COMPILE_TEST
-	depends on OF
-	default SOC_STARFIVE
-	select GENERIC_PINCTRL_GROUPS
-	select GENERIC_PINMUX_FUNCTIONS
-	select GENERIC_PINCONF
-	select GPIOLIB
-	select GPIOLIB_IRQCHIP
-	select OF_GPIO
-	help
-	  Say yes here to support pin control on the StarFive JH7100 SoC.
-	  This also provides an interface to the GPIO pins not used by other
-	  peripherals supporting inputs, outputs, configuring pull-up/pull-down
-	  and interrupts on input changes.
-
 config PINCTRL_STMFX
 	tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
 	depends on I2C
@@ -526,6 +509,7 @@ source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/samsung/Kconfig"
 source "drivers/pinctrl/spear/Kconfig"
 source "drivers/pinctrl/sprd/Kconfig"
+source "drivers/pinctrl/starfive/Kconfig"
 source "drivers/pinctrl/stm32/Kconfig"
 source "drivers/pinctrl/sunplus/Kconfig"
 source "drivers/pinctrl/sunxi/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e76f5cdc64b0..eccd4d568a3d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -43,7 +43,6 @@ obj-$(CONFIG_PINCTRL_RK805)	+= pinctrl-rk805.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_ST) 	+= pinctrl-st.o
-obj-$(CONFIG_PINCTRL_STARFIVE)	+= pinctrl-starfive.o
 obj-$(CONFIG_PINCTRL_STMFX) 	+= pinctrl-stmfx.o
 obj-$(CONFIG_PINCTRL_SX150X)	+= pinctrl-sx150x.o
 obj-$(CONFIG_PINCTRL_TB10X)	+= pinctrl-tb10x.o
@@ -70,6 +69,7 @@ obj-$(CONFIG_PINCTRL_RENESAS)	+= renesas/
 obj-$(CONFIG_PINCTRL_SAMSUNG)	+= samsung/
 obj-$(CONFIG_PINCTRL_SPEAR)	+= spear/
 obj-y				+= sprd/
+obj-$(CONFIG_SOC_STARFIVE)	+= starfive/
 obj-$(CONFIG_PINCTRL_STM32)	+= stm32/
 obj-y				+= sunplus/
 obj-$(CONFIG_PINCTRL_SUNXI)	+= sunxi/
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
new file mode 100644
index 000000000000..ed8c6a920886
--- /dev/null
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PINCTRL_STARFIVE
+	tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on OF
+	select GENERIC_PINCTRL_GROUPS
+	select GENERIC_PINMUX_FUNCTIONS
+	select GENERIC_PINCONF
+	select GPIOLIB
+	select GPIOLIB_IRQCHIP
+	select OF_GPIO
+	default SOC_STARFIVE
+	help
+	  Say yes here to support pin control on the StarFive JH7100 SoC.
+	  This also provides an interface to the GPIO pins not used by other
+	  peripherals supporting inputs, outputs, configuring pull-up/pull-down
+	  and interrupts on input changes.
+
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
new file mode 100644
index 000000000000..4c96e2f86292
--- /dev/null
+++ b/drivers/pinctrl/starfive/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PINCTRL_STARFIVE)	+= pinctrl-starfive.o
diff --git a/drivers/pinctrl/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c
similarity index 99%
rename from drivers/pinctrl/pinctrl-starfive.c
rename to drivers/pinctrl/starfive/pinctrl-starfive.c
index 3eb40e230d98..74a084740e8c 100644
--- a/drivers/pinctrl/pinctrl-starfive.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.c
@@ -22,10 +22,10 @@
 
 #include <dt-bindings/pinctrl/pinctrl-starfive.h>
 
-#include "core.h"
-#include "pinctrl-utils.h"
-#include "pinmux.h"
-#include "pinconf.h"
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinmux.h"
+#include "../pinconf.h"
 
 #define DRIVER_NAME "pinctrl-starfive"
 
-- 
2.17.1

Re: [PATCH v1 22/30] pinctrl: Create subdirectory for StarFive drivers

[Linus Walleij]

On Fri, Sep 30, 2022 at 8:08 AM Hal Feng
<hal.feng@linux.starfivetech.com> wrote:

> From: Jianlong Huang <jianlong.huang@starfivetech.com>
>
> Move the StarFive JH7100 pinctrl driver to a new subdirectory
> in preparation for adding more StarFive pinctrl drivers. No
> functional change.
>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>

I applied this patch for v6.1 so you don't have to reiterate it, it's clearly
just infrastructure that you'll need going forward.

Yours,
Linus Walleij

[PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Hal Feng]

From: Jianlong Huang <jianlong.huang@starfivetech.com>

Add the SoC name to make it more clear. Also the next generation StarFive
SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
No functional change.

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
 drivers/pinctrl/starfive/Kconfig                            | 2 +-
 drivers/pinctrl/starfive/Makefile                           | 2 +-
 .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
 .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
 6 files changed, 8 insertions(+), 8 deletions(-)
 rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
 rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)

diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
index 92963604422f..a6140dddd39a 100644
--- a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
@@ -165,7 +165,7 @@ examples:
   - |
     #include <dt-bindings/clock/starfive-jh7100.h>
     #include <dt-bindings/reset/starfive-jh7100.h>
-    #include <dt-bindings/pinctrl/pinctrl-starfive.h>
+    #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
 
     soc {
         #address-cells = <2>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
index c9af67f7a0d2..f7a230110512 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
@@ -8,7 +8,7 @@
 #include "jh7100.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/pinctrl-starfive.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
 
 / {
 	model = "BeagleV Starlight Beta";
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index ed8c6a920886..5cedb546f93d 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-config PINCTRL_STARFIVE
+config PINCTRL_STARFIVE_JH7100
 	tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
 	depends on SOC_STARFIVE || COMPILE_TEST
 	depends on OF
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 4c96e2f86292..0293f26a0a99 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 
-obj-$(CONFIG_PINCTRL_STARFIVE)	+= pinctrl-starfive.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JH7100)	+= pinctrl-starfive-jh7100.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
similarity index 99%
rename from drivers/pinctrl/starfive/pinctrl-starfive.c
rename to drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
index 74a084740e8c..5b544fb7f3d8 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
@@ -20,7 +20,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 
-#include <dt-bindings/pinctrl/pinctrl-starfive.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
 
 #include "../core.h"
 #include "../pinctrl-utils.h"
diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
similarity index 98%
rename from include/dt-bindings/pinctrl/pinctrl-starfive.h
rename to include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
index de4f75c2c9e8..a200f546d078 100644
--- a/include/dt-bindings/pinctrl/pinctrl-starfive.h
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
@@ -3,8 +3,8 @@
  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
  */
 
-#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_H__
-#define __DT_BINDINGS_PINCTRL_STARFIVE_H__
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__
 
 #define PAD_GPIO_OFFSET		0
 #define PAD_FUNC_SHARE_OFFSET	64
@@ -272,4 +272,4 @@
 
 #define GPI_NONE				0xff
 
-#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_H__ */
+#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ */
-- 
2.17.1

Re: [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Rob Herring]

On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> From: Jianlong Huang <jianlong.huang@starfivetech.com>
> 
> Add the SoC name to make it more clear. Also the next generation StarFive
> SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> No functional change.
> 
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
>  arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
>  drivers/pinctrl/starfive/Kconfig                            | 2 +-
>  drivers/pinctrl/starfive/Makefile                           | 2 +-
>  .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
>  .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
>  6 files changed, 8 insertions(+), 8 deletions(-)
>  rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
>  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Would be good to pull this out separately and apply for 6.1. It's kind 
of messy with cross tree dependencies.

Re: [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Linus Walleij]

On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <robh@kernel.org> wrote:
> On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> >
> > Add the SoC name to make it more clear. Also the next generation StarFive
> > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > No functional change.
> >
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> >  .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
> >  arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
> >  drivers/pinctrl/starfive/Kconfig                            | 2 +-
> >  drivers/pinctrl/starfive/Makefile                           | 2 +-
> >  .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
> >  .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
> >  6 files changed, 8 insertions(+), 8 deletions(-)
> >  rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> >  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> >
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> Would be good to pull this out separately and apply for 6.1. It's kind
> of messy with cross tree dependencies.

OK I applied this for V6.1.

Yours,
Linus Walleij

Re: [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Conor Dooley]

On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <robh@kernel.org> wrote:
> > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> > >
> > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > No functional change.
> > >
> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > > ---
> > >  .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
> > >  arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
> > >  drivers/pinctrl/starfive/Kconfig                            | 2 +-
> > >  drivers/pinctrl/starfive/Makefile                           | 2 +-
> > >  .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
> > >  .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
> > >  6 files changed, 8 insertions(+), 8 deletions(-)
> > >  rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > >  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > >
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> >
> > Would be good to pull this out separately and apply for 6.1. It's kind
> > of messy with cross tree dependencies.
> 
> OK I applied this for V6.1.

Will this need to be done immutably so it can be pulled into the riscv
tree in case this gets applied as a late change for 6.1:
https://lore.kernel.org/linux-riscv/c5169131-486e-9808-ba48-b7abe1be6a99@collabora.com/

Thanks,
Conor.

Re: [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Linus Walleij]

On Tue, Oct 4, 2022 at 10:59 AM Conor Dooley <conor.dooley@microchip.com> wrote:
> On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> > On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <robh@kernel.org> wrote:
> > > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > >
> > > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > > No functional change.
> > > >
> > > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > > > ---
> > > >  .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
> > > >  arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
> > > >  drivers/pinctrl/starfive/Kconfig                            | 2 +-
> > > >  drivers/pinctrl/starfive/Makefile                           | 2 +-
> > > >  .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
> > > >  .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
> > > >  6 files changed, 8 insertions(+), 8 deletions(-)
> > > >  rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > >  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > > >
> > >
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > >
> > > Would be good to pull this out separately and apply for 6.1. It's kind
> > > of messy with cross tree dependencies.
> >
> > OK I applied this for V6.1.
>
> Will this need to be done immutably so it can be pulled into the riscv
> tree in case this gets applied as a late change for 6.1:
> https://lore.kernel.org/linux-riscv/c5169131-486e-9808-ba48-b7abe1be6a99@collabora.com/

Always one finger on the fast-forward button have we? ;)

Rob's point was that I should apply this for v6.1 so that exactly
that kind of cross-dependencies and immutable branches could
be avoided for the v6.2 development cycle.

The merge window is already open, it's a bit late for completely
new stuff I think.

Yours,
Linus Walleij

Re: [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Conor Dooley]

On Tue, Oct 04, 2022 at 11:13:37AM +0200, Linus Walleij wrote:
> On Tue, Oct 4, 2022 at 10:59 AM Conor Dooley <conor.dooley@microchip.com> wrote:
> > On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> > > On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <robh@kernel.org> wrote:
> > > > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > > > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > > >
> > > > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > > > No functional change.
> > > > >
> > > > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > > > > ---
> > > > >  .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
> > > > >  arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
> > > > >  drivers/pinctrl/starfive/Kconfig                            | 2 +-
> > > > >  drivers/pinctrl/starfive/Makefile                           | 2 +-
> > > > >  .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
> > > > >  .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
> > > > >  6 files changed, 8 insertions(+), 8 deletions(-)
> > > > >  rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > > >  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > > > >
> > > >
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > >
> > > > Would be good to pull this out separately and apply for 6.1. It's kind
> > > > of messy with cross tree dependencies.
> > >
> > > OK I applied this for V6.1.
> >
> > Will this need to be done immutably so it can be pulled into the riscv
> > tree in case this gets applied as a late change for 6.1:
> > https://lore.kernel.org/linux-riscv/c5169131-486e-9808-ba48-b7abe1be6a99@collabora.com/
> 
> Always one finger on the fast-forward button have we? ;)

Dunno what you mean by that mate, sorry!

I just saw the mail wanted to have the decency to reply to that fellow
& tell him to rebase after rc1 to avoid a conflict.

> Rob's point was that I should apply this for v6.1 so that exactly
> that kind of cross-dependencies and immutable branches could
> be avoided for the v6.2 development cycle.
> 
> The merge window is already open, it's a bit late for completely
> new stuff I think.

History suggests otherwise, but I'd be lying if I said I disagreed.

Re: [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Conor Dooley]

On Tue, Oct 04, 2022 at 10:21:24AM +0100, Conor Dooley wrote:
> On Tue, Oct 04, 2022 at 11:13:37AM +0200, Linus Walleij wrote:
> > On Tue, Oct 4, 2022 at 10:59 AM Conor Dooley <conor.dooley@microchip.com> wrote:
> > > On Tue, Oct 04, 2022 at 10:48:38AM +0200, Linus Walleij wrote:
> > > > On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <robh@kernel.org> wrote:
> > > > > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > > > > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > > > >
> > > > > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > > > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > > > > No functional change.
> > > > > >
> > > > > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > > > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > > > > > ---
> > > > > >  .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
> > > > > >  arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
> > > > > >  drivers/pinctrl/starfive/Kconfig                            | 2 +-
> > > > > >  drivers/pinctrl/starfive/Makefile                           | 2 +-
> > > > > >  .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
> > > > > >  .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
> > > > > >  6 files changed, 8 insertions(+), 8 deletions(-)
> > > > > >  rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > > > > >  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > > > > >
> > > > >
> > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > >
> > > > > Would be good to pull this out separately and apply for 6.1. It's kind
> > > > > of messy with cross tree dependencies.
> > > >
> > > > OK I applied this for V6.1.
> > >
> > > Will this need to be done immutably so it can be pulled into the riscv
> > > tree in case this gets applied as a late change for 6.1:
> > > https://lore.kernel.org/linux-riscv/c5169131-486e-9808-ba48-b7abe1be6a99@collabora.com/
> > 
> > Always one finger on the fast-forward button have we? ;)
> 
> Dunno what you mean by that mate, sorry!
> 
> I just saw the mail wanted to have the decency to reply to that fellow

s/wanted/want

> & tell him to rebase after rc1 to avoid a conflict.
> 
> > Rob's point was that I should apply this for v6.1 so that exactly
> > that kind of cross-dependencies and immutable branches could
> > be avoided for the v6.2 development cycle.
> > 
> > The merge window is already open, it's a bit late for completely
> > new stuff I think.
> 
> History suggests otherwise, but I'd be lying if I said I disagreed.

Re: [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"

[Geert Uytterhoeven]

Hi Linus,

On Tue, Oct 4, 2022 at 10:50 AM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Sep 30, 2022 at 11:28 PM Rob Herring <robh@kernel.org> wrote:
> > On Fri, 30 Sep 2022 14:14:04 +0800, Hal Feng wrote:
> > > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> > >
> > > Add the SoC name to make it more clear. Also the next generation StarFive
> > > SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver.
> > > No functional change.
> > >
> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > > ---
> > >  .../bindings/pinctrl/starfive,jh7100-pinctrl.yaml           | 2 +-
> > >  arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts   | 2 +-
> > >  drivers/pinctrl/starfive/Kconfig                            | 2 +-
> > >  drivers/pinctrl/starfive/Makefile                           | 2 +-
> > >  .../{pinctrl-starfive.c => pinctrl-starfive-jh7100.c}       | 2 +-
> > >  .../{pinctrl-starfive.h => pinctrl-starfive-jh7100.h}       | 6 +++---
> > >  6 files changed, 8 insertions(+), 8 deletions(-)
> > >  rename drivers/pinctrl/starfive/{pinctrl-starfive.c => pinctrl-starfive-jh7100.c} (99%)
> > >  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
> > >
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> >
> > Would be good to pull this out separately and apply for 6.1. It's kind
> > of messy with cross tree dependencies.
>
> OK I applied this for V6.1.

Isn't the name of the DT bindings header file part of the DT bindings,
i.e. it cannot be changed afterwards?
As of v5.17, it is in active use by
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v1 24/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions

[Hal Feng]

From: Jianlong Huang <jianlong.huang@starfivetech.com>

Add pinctrl definitions for StarFive JH7110 SoC.

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../pinctrl/pinctrl-starfive-jh7110.h         | 931 ++++++++++++++++++
 1 file changed, 931 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h

diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
new file mode 100644
index 000000000000..159cfcf6b915
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
@@ -0,0 +1,931 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+
+/* aon_iomux pin */
+#define	PAD_TESTEN	0
+#define	PAD_RGPIO0	1
+#define	PAD_RGPIO1	2
+#define	PAD_RGPIO2	3
+#define	PAD_RGPIO3	4
+#define	PAD_RSTN	5
+#define	PAD_GMAC0_MDC	6
+#define	PAD_GMAC0_MDIO	7
+#define	PAD_GMAC0_RXD0	8
+#define	PAD_GMAC0_RXD1	9
+#define	PAD_GMAC0_RXD2	10
+#define	PAD_GMAC0_RXD3	11
+#define	PAD_GMAC0_RXDV	12
+#define	PAD_GMAC0_RXC	13
+#define	PAD_GMAC0_TXD0	14
+#define	PAD_GMAC0_TXD1	15
+#define	PAD_GMAC0_TXD2	16
+#define	PAD_GMAC0_TXD3	17
+#define	PAD_GMAC0_TXEN	18
+#define	PAD_GMAC0_TXC	19
+
+/* aon_iomux dout */
+#define GPO_AON_CLK_32K_OUT		2
+#define GPO_AON_PTC0_PWM4		3
+#define GPO_AON_PTC0_PWM5		4
+#define GPO_AON_PTC0_PWM6		5
+#define GPO_AON_PTC0_PWM7		6
+#define GPO_AON_CLK_GCLK0		7
+#define GPO_AON_CLK_GCLK1		8
+#define GPO_AON_CLK_GCLK2		9
+
+/* aon_iomux doen */
+#define OEN_AON_PTC0_OE_N_4		2
+#define OEN_AON_PTC0_OE_N_5		3
+#define OEN_AON_PTC0_OE_N_6		4
+#define OEN_AON_PTC0_OE_N_7		5
+
+/* aon_iomux gin */
+#define GPI_AON_PMU_GPIO_WAKEUP_0	0
+#define GPI_AON_PMU_GPIO_WAKEUP_1	1
+#define GPI_AON_PMU_GPIO_WAKEUP_2	2
+#define GPI_AON_PMU_GPIO_WAKEUP_3	3
+
+/* aon_iomux gmac0 syscon */
+#define PADCFG_PAD_GMAC0_MDC_SYSCON	0x58
+#define PADCFG_PAD_GMAC0_MDIO_SYSCON	0x5c
+#define PADCFG_PAD_GMAC0_RXD0_SYSCON	0x60
+#define PADCFG_PAD_GMAC0_RXD1_SYSCON	0x64
+#define PADCFG_PAD_GMAC0_RXD2_SYSCON	0x68
+#define PADCFG_PAD_GMAC0_RXD3_SYSCON	0x6c
+#define PADCFG_PAD_GMAC0_RXDV_SYSCON	0x70
+#define PADCFG_PAD_GMAC0_RXC_SYSCON	0x74
+#define PADCFG_PAD_GMAC0_TXD0_SYSCON	0x78
+#define PADCFG_PAD_GMAC0_TXD1_SYSCON	0x7c
+#define PADCFG_PAD_GMAC0_TXD2_SYSCON	0x80
+#define PADCFG_PAD_GMAC0_TXD3_SYSCON	0x84
+#define PADCFG_PAD_GMAC0_TXEN_SYSCON	0x88
+#define PADCFG_PAD_GMAC0_TXC_SYSCON	0x8c
+
+/* aon_iomux func sel */
+#define AON_IOMUX_CFGSAIF_144_ADDR	0x90
+#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT	0x0
+#define PAD_GMAC0_RXC_FUNC_SEL_MASK	0x3
+
+#define PAD_GMAC0_RXC_FUNC_SEL		\
+	AON_IOMUX_CFGSAIF_144_ADDR	\
+	PAD_GMAC0_RXC_FUNC_SEL_SHIFT	\
+	PAD_GMAC0_RXC_FUNC_SEL_MASK
+
+/* sys_iomux pin */
+#define	PAD_GPIO0	0
+#define	PAD_GPIO1	1
+#define	PAD_GPIO2	2
+#define	PAD_GPIO3	3
+#define	PAD_GPIO4	4
+#define	PAD_GPIO5	5
+#define	PAD_GPIO6	6
+#define	PAD_GPIO7	7
+#define	PAD_GPIO8	8
+#define	PAD_GPIO9	9
+#define	PAD_GPIO10	10
+#define	PAD_GPIO11	11
+#define	PAD_GPIO12	12
+#define	PAD_GPIO13	13
+#define	PAD_GPIO14	14
+#define	PAD_GPIO15	15
+#define	PAD_GPIO16	16
+#define	PAD_GPIO17	17
+#define	PAD_GPIO18	18
+#define	PAD_GPIO19	19
+#define	PAD_GPIO20	20
+#define	PAD_GPIO21	21
+#define	PAD_GPIO22	22
+#define	PAD_GPIO23	23
+#define	PAD_GPIO24	24
+#define	PAD_GPIO25	25
+#define	PAD_GPIO26	26
+#define	PAD_GPIO27	27
+#define	PAD_GPIO28	28
+#define	PAD_GPIO29	29
+#define	PAD_GPIO30	30
+#define	PAD_GPIO31	31
+#define	PAD_GPIO32	32
+#define	PAD_GPIO33	33
+#define	PAD_GPIO34	34
+#define	PAD_GPIO35	35
+#define	PAD_GPIO36	36
+#define	PAD_GPIO37	37
+#define	PAD_GPIO38	38
+#define	PAD_GPIO39	39
+#define	PAD_GPIO40	40
+#define	PAD_GPIO41	41
+#define	PAD_GPIO42	42
+#define	PAD_GPIO43	43
+#define	PAD_GPIO44	44
+#define	PAD_GPIO45	45
+#define	PAD_GPIO46	46
+#define	PAD_GPIO47	47
+#define	PAD_GPIO48	48
+#define	PAD_GPIO49	49
+#define	PAD_GPIO50	50
+#define	PAD_GPIO51	51
+#define	PAD_GPIO52	52
+#define	PAD_GPIO53	53
+#define	PAD_GPIO54	54
+#define	PAD_GPIO55	55
+#define	PAD_GPIO56	56
+#define	PAD_GPIO57	57
+#define	PAD_GPIO58	58
+#define	PAD_GPIO59	59
+#define	PAD_GPIO60	60
+#define	PAD_GPIO61	61
+#define	PAD_GPIO62	62
+#define	PAD_GPIO63	63
+#define	PAD_SD0_CLK	64
+#define	PAD_SD0_CMD	65
+#define	PAD_SD0_DATA0	66
+#define	PAD_SD0_DATA1	67
+#define	PAD_SD0_DATA2	68
+#define	PAD_SD0_DATA3	69
+#define	PAD_SD0_DATA4	70
+#define	PAD_SD0_DATA5	71
+#define	PAD_SD0_DATA6	72
+#define	PAD_SD0_DATA7	73
+#define	PAD_SD0_STRB	74
+#define	PAD_GMAC1_MDC	75
+#define	PAD_GMAC1_MDIO	76
+#define	PAD_GMAC1_RXD0	77
+#define	PAD_GMAC1_RXD1	78
+#define	PAD_GMAC1_RXD2	79
+#define	PAD_GMAC1_RXD3	80
+#define	PAD_GMAC1_RXDV	81
+#define	PAD_GMAC1_RXC	82
+#define	PAD_GMAC1_TXD0	83
+#define	PAD_GMAC1_TXD1	84
+#define	PAD_GMAC1_TXD2	85
+#define	PAD_GMAC1_TXD3	86
+#define	PAD_GMAC1_TXEN	87
+#define	PAD_GMAC1_TXC	88
+#define	PAD_QSPI_SCLK	89
+#define	PAD_QSPI_CSn0	90
+#define	PAD_QSPI_DATA0	91
+#define	PAD_QSPI_DATA1	92
+#define	PAD_QSPI_DATA2	93
+#define	PAD_QSPI_DATA3	94
+
+#define GPO_LOW					0
+#define GPO_HIGH				1
+#define GPO_WAVE511_0_O_UART_TXSOUT		2
+#define GPO_CAN0_CTRL_STBY			3
+#define GPO_CAN0_CTRL_TST_NEXT_BIT		4
+#define GPO_CAN0_CTRL_TST_SAMPLE_POINT		5
+#define GPO_CAN0_CTRL_TXD			6
+#define GPO_USB0_DRIVE_VBUS_IO			7
+#define GPO_QSPI0_CSN1				8
+#define GPO_SPDIF0_SPDIFO			9
+#define GPO_HDMI0_CEC_SDA_OUT			10
+#define GPO_HDMI0_DDC_SCL_OUT			11
+#define GPO_HDMI0_DDC_SDA_OUT			12
+#define GPO_WDT0_WDOGRES			13
+#define GPO_I2C0_IC_CLK_OUT_A			14
+#define GPO_I2C0_IC_DATA_OUT_A			15
+#define GPO_SDIO0_BACK_END_POWER		16
+#define GPO_SDIO0_CARD_POWER_EN			17
+#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N		18
+#define GPO_SDIO0_RST_N				19
+#define GPO_UART0_SOUT				20
+#define GPO_JTAG_DSP_TDO			21
+#define GPO_JTAG_CPU_CERTIFICATION_TDO		22
+#define GPO_PDM_4MIC0_DMIC_MCLK			23
+#define GPO_PTC0_PWM_0				24
+#define GPO_PTC0_PWM_1				25
+#define GPO_PTC0_PWM_2				26
+#define GPO_PTC0_PWM_3				27
+#define GPO_PWMDAC0_LEFT_OUTPUT			28
+#define GPO_PWMDAC0_RIGHT_OUTPUT		29
+#define GPO_SPI0_SSPCLKOUT			30
+#define GPO_SPI0_SSPFSSOUT			31
+#define GPO_SPI0_SSPTXD				32
+#define GPO_GMAC0_CLK_PHY			33
+#define GPO_I2SRX0_BCLK_MST			34
+#define GPO_I2SRX0_LRCK_MST			35
+#define GPO_I2STX0_BCLK_MST			36
+#define GPO_I2STX0_LRCK_MST			37
+#define GPO_CRG0_MCLK_OUT			38
+#define GPO_TDM0_CLK_MST			39
+#define GPO_TDM0_PCM_SYNCOUT			40
+#define GPO_TDM0_PCM_TXD			41
+#define GPO_U7MC_TRACE0_TDATA_0			42
+#define GPO_U7MC_TRACE0_TDATA_1			43
+#define GPO_U7MC_TRACE0_TDATA_2			44
+#define GPO_U7MC_TRACE0_TDATA_3			45
+#define GPO_U7MC_TRACE0_TREF			46
+#define GPO_CAN1_CTRL_STBY			47
+#define GPO_CAN1_CTRL_TST_NEXT_BIT		48
+#define GPO_CAN1_CTRL_TST_SAMPLE_POINT		49
+#define GPO_CAN1_CTRL_TXD			50
+#define GPO_I2C1_IC_CLK_OUT_A			51
+#define GPO_I2C1_IC_DATA_OUT_A			52
+#define GPO_SDIO1_BACK_END_POWER		53
+#define GPO_SDIO1_CARD_POWER_EN			54
+#define GPO_SDIO1_CCLK_OUT			55
+#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N		56
+#define GPO_SDIO1_CCMD_OUT			57
+#define GPO_SDIO1_CDATA_OUT_0			58
+#define GPO_SDIO1_CDATA_OUT_1			59
+#define GPO_SDIO1_CDATA_OUT_2			60
+#define GPO_SDIO1_CDATA_OUT_3			61
+#define GPO_SDIO1_CDATA_OUT_4			62
+#define GPO_SDIO1_CDATA_OUT_5			63
+#define GPO_SDIO1_CDATA_OUT_6			64
+#define GPO_SDIO1_CDATA_OUT_7			65
+#define GPO_SDIO1_RST_N				66
+#define GPO_UART1_RTS_N				67
+#define GPO_UART1_SOUT				68
+#define GPO_I2STX_4CH1_SDO0			69
+#define GPO_I2STX_4CH1_SDO1			70
+#define GPO_I2STX_4CH1_SDO2			71
+#define GPO_I2STX_4CH1_SDO3			72
+#define GPO_SPI1_SSPCLKOUT			73
+#define GPO_SPI1_SSPFSSOUT			74
+#define GPO_SPI1_SSPTXD				75
+#define GPO_I2C2_IC_CLK_OUT_A			76
+#define GPO_I2C2_IC_DATA_OUT_A			77
+#define GPO_UART2_RTS_N				78
+#define GPO_UART2_SOUT				79
+#define GPO_SPI2_SSPCLKOUT			80
+#define GPO_SPI2_SSPFSSOUT			81
+#define GPO_SPI2_SSPTXD				82
+#define GPO_I2C3_IC_CLK_OUT_A			83
+#define GPO_I2C3_IC_DATA_OUT_A			84
+#define GPO_UART3_SOUT				85
+#define GPO_SPI3_SSPCLKOUT			86
+#define GPO_SPI3_SSPFSSOUT			87
+#define GPO_SPI3_SSPTXD				88
+#define GPO_I2C4_IC_CLK_OUT_A			89
+#define GPO_I2C4_IC_DATA_OUT_A			90
+#define GPO_UART4_RTS_N				91
+#define GPO_UART4_SOUT				92
+#define GPO_SPI4_SSPCLKOUT			93
+#define GPO_SPI4_SSPFSSOUT			94
+#define GPO_SPI4_SSPTXD				95
+#define GPO_I2C5_IC_CLK_OUT_A			96
+#define GPO_I2C5_IC_DATA_OUT_A			97
+#define GPO_UART5_RTS_N				98
+#define GPO_UART5_SOUT				99
+#define GPO_SPI5_SSPCLKOUT			100
+#define GPO_SPI5_SSPFSSOUT			101
+#define GPO_SPI5_SSPTXD				102
+#define GPO_I2C6_IC_CLK_OUT_A			103
+#define GPO_I2C6_IC_DATA_OUT_A			104
+#define GPO_SPI6_SSPCLKOUT			105
+#define GPO_SPI6_SSPFSSOUT			106
+#define GPO_SPI6_SSPTXD				107
+#define GPO_NONE				108
+
+#define OEN_LOW					0
+#define OEN_HIGH				1
+#define OEN_HDMI0_CEC_SDA_OEN			2
+#define OEN_HDMI0_DDC_SCL_OEN			3
+#define OEN_HDMI0_DDC_SDA_OEN			4
+#define OEN_I2C0_IC_CLK_OE			5
+#define OEN_I2C0_IC_DATA_OE			6
+#define OEN_JTAG_DSP_TDO_OEN			7
+#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE	8
+#define OEN_PTC0_PWM_0_OE_N			9
+#define OEN_PTC0_PWM_1_OE_N			10
+#define OEN_PTC0_PWM_2_OE_N			11
+#define OEN_PTC0_PWM_3_OE_N			12
+#define OEN_SPI0_NSSPCTLOE			13
+#define OEN_SPI0_NSSPOE				14
+#define OEN_TDM0_NPCM_SYNCOE			15
+#define OEN_TDM0_NPCM_TXDOE			16
+#define OEN_I2C1_IC_CLK_OE			17
+#define OEN_I2C1_IC_DATA_OE			18
+#define OEN_SDIO1_CCMD_OUT_EN			19
+#define OEN_SDIO1_CDATA_OUT_EN_0		20
+#define OEN_SDIO1_CDATA_OUT_EN_1		21
+#define OEN_SDIO1_CDATA_OUT_EN_2		22
+#define OEN_SDIO1_CDATA_OUT_EN_3		23
+#define OEN_SDIO1_CDATA_OUT_EN_4		24
+#define OEN_SDIO1_CDATA_OUT_EN_5		25
+#define OEN_SDIO1_CDATA_OUT_EN_6		26
+#define OEN_SDIO1_CDATA_OUT_EN_7		27
+#define OEN_SPI1_NSSPCTLOE			28
+#define OEN_SPI1_NSSPOE				29
+#define OEN_I2C2_IC_CLK_OE			30
+#define OEN_I2C2_IC_DATA_OE			31
+#define OEN_SPI2_NSSPCTLOE			32
+#define OEN_SPI2_NSSPOE				33
+#define OEN_I2C3_IC_CLK_OE			34
+#define OEN_I2C3_IC_DATA_OE			35
+#define OEN_SPI3_NSSPCTLOE			36
+#define OEN_SPI3_NSSPOE				37
+#define OEN_I2C4_IC_CLK_OE			38
+#define OEN_I2C4_IC_DATA_OE			39
+#define OEN_SPI4_NSSPCTLOE			40
+#define OEN_SPI4_NSSPOE				41
+#define OEN_I2C5_IC_CLK_OE			42
+#define OEN_I2C5_IC_DATA_OE			43
+#define OEN_SPI5_NSSPCTLOE			44
+#define OEN_SPI5_NSSPOE				45
+#define OEN_I2C6_IC_CLK_OE			46
+#define OEN_I2C6_IC_DATA_OE			47
+#define OEN_SPI6_NSSPCTLOE			48
+#define OEN_SPI6_NSSPOE				49
+#define OEN_NONE				50
+
+#define GPI_WAVE511_0_I_UART_RXSIN		0
+#define GPI_CAN0_CTRL_RXD			1
+#define GPI_USB0_OVERCURRENT_N_IO		2
+#define GPI_SPDIF0_SPDIFI			3
+#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN	4
+#define GPI_HDMI0_CEC_SDA_IN			5
+#define GPI_HDMI0_DDC_SCL_IN			6
+#define GPI_HDMI0_DDC_SDA_IN			7
+#define GPI_HDMI0_HPD				8
+#define GPI_I2C0_IC_CLK_IN_A			9
+#define GPI_I2C0_IC_DATA_IN_A			10
+#define GPI_SDIO0_CARD_DETECT_N			11
+#define GPI_SDIO0_CARD_INT_N			12
+#define GPI_SDIO0_CARD_WRITE_PRT		13
+#define GPI_UART0_SIN				14
+#define GPI_JTAG_DSP_TCK			15
+#define GPI_JTAG_DSP_TDI			16
+#define GPI_JTAG_DSP_TMS			17
+#define GPI_JTAG_DSP_TRST_N			18
+#define GPI_JTAG_CPU_CERTIFICATION_TDI		19
+#define GPI_JTAG_CPU_CERTIFICATION_TMS		20
+#define GPI_PDM_4MIC0_DMIC0_DIN			21
+#define GPI_PDM_4MIC0_DMIC1_DIN			22
+#define GPI_I2SRX0_EXT_SDIN0			23
+#define GPI_I2SRX0_EXT_SDIN1			24
+#define GPI_I2SRX0_EXT_SDIN2			25
+#define GPI_SPI0_SSPCLKIN			26
+#define GPI_SPI0_SSPFSSIN			27
+#define GPI_SPI0_SSPRXD				28
+#define GPI_JTAG_CPU_CERTIFICATION_TCK		29
+#define GPI_CRG0_EXT_MCLK			30
+#define GPI_I2SRX0_BCLK_SLV			31
+#define GPI_I2SRX0_LRCK_SLV			32
+#define GPI_I2STX0_BCLK_SLV			33
+#define GPI_I2STX0_LRCK_SLV			34
+#define GPI_TDM0_CLK_SLV			35
+#define GPI_TDM0_PCM_RXD			36
+#define GPI_TDM0_PCM_SYNCIN			37
+#define GPI_CAN1_CTRL_RXD			38
+#define GPI_I2C1_IC_CLK_IN_A			39
+#define GPI_I2C1_IC_DATA_IN_A			40
+#define GPI_SDIO1_CARD_DETECT_N			41
+#define GPI_SDIO1_CARD_INT_N			42
+#define GPI_SDIO1_CARD_WRITE_PRT		43
+#define GPI_SDIO1_CCMD_IN			44
+#define GPI_SDIO1_CDATA_IN_0			45
+#define GPI_SDIO1_CDATA_IN_1			46
+#define GPI_SDIO1_CDATA_IN_2			47
+#define GPI_SDIO1_CDATA_IN_3			48
+#define GPI_SDIO1_CDATA_IN_4			49
+#define GPI_SDIO1_CDATA_IN_5			50
+#define GPI_SDIO1_CDATA_IN_6			51
+#define GPI_SDIO1_CDATA_IN_7			52
+#define GPI_SDIO1_DATA_STROBE			53
+#define GPI_UART1_CTS_N				54
+#define GPI_UART1_SIN				55
+#define GPI_SPI1_SSPCLKIN			56
+#define GPI_SPI1_SSPFSSIN			57
+#define GPI_SPI1_SSPRXD				58
+#define GPI_I2C2_IC_CLK_IN_A			59
+#define GPI_I2C2_IC_DATA_IN_A			60
+#define GPI_UART2_CTS_N				61
+#define GPI_UART2_SIN				62
+#define GPI_SPI2_SSPCLKIN			63
+#define GPI_SPI2_SSPFSSIN			64
+#define GPI_SPI2_SSPRXD				65
+#define GPI_I2C3_IC_CLK_IN_A			66
+#define GPI_I2C3_IC_DATA_IN_A			67
+#define GPI_UART3_SIN				68
+#define GPI_SPI3_SSPCLKIN			69
+#define GPI_SPI3_SSPFSSIN			70
+#define GPI_SPI3_SSPRXD				71
+#define GPI_I2C4_IC_CLK_IN_A			72
+#define GPI_I2C4_IC_DATA_IN_A			73
+#define GPI_UART4_CTS_N				74
+#define GPI_UART4_SIN				75
+#define GPI_SPI4_SSPCLKIN			76
+#define GPI_SPI4_SSPFSSIN			77
+#define GPI_SPI4_SSPRXD				78
+#define GPI_I2C5_IC_CLK_IN_A			79
+#define GPI_I2C5_IC_DATA_IN_A			80
+#define GPI_UART5_CTS_N				81
+#define GPI_UART5_SIN				82
+#define GPI_SPI5_SSPCLKIN			83
+#define GPI_SPI5_SSPFSSIN			84
+#define GPI_SPI5_SSPRXD				85
+#define GPI_I2C6_IC_CLK_IN_A			86
+#define GPI_I2C6_IC_DATA_IN_A			87
+#define GPI_SPI6_SSPCLKIN			88
+#define GPI_SPI6_SSPFSSIN			89
+#define GPI_SPI6_SSPRXD				90
+#define	GPI_NONE				91
+
+/* sys_iomux syscon */
+#define PADCFG_PAD_GMAC1_MDC_SYSCON		0x24c
+#define PADCFG_PAD_GMAC1_MDIO_SYSCON		0x250
+#define PADCFG_PAD_GMAC1_RXD0_SYSCON		0x254
+#define PADCFG_PAD_GMAC1_RXD1_SYSCON		0x258
+#define PADCFG_PAD_GMAC1_RXD2_SYSCON		0x25c
+#define PADCFG_PAD_GMAC1_RXD3_SYSCON		0x260
+#define PADCFG_PAD_GMAC1_RXDV_SYSCON		0x264
+#define PADCFG_PAD_GMAC1_RXC_SYSCON		0x268
+#define PADCFG_PAD_GMAC1_TXD0_SYSCON		0x26c
+#define PADCFG_PAD_GMAC1_TXD1_SYSCON		0x270
+#define PADCFG_PAD_GMAC1_TXD2_SYSCON		0x274
+#define PADCFG_PAD_GMAC1_TXD3_SYSCON		0x278
+#define PADCFG_PAD_GMAC1_TXEN_SYSCON		0x27c
+#define PADCFG_PAD_GMAC1_TXC_SYSCON		0x280
+
+/* sys_iomux func sel setting */
+#define SYS_IOMUX_CFGSAIF_668_ADDR		0x29c
+#define PAD_GMAC1_RXC_FUNC_SEL_SHIFT		0x0
+#define PAD_GMAC1_RXC_FUNC_SEL_MASK		0x3
+#define PAD_GPIO10_FUNC_SEL_SHIFT		0x2
+#define PAD_GPIO10_FUNC_SEL_MASK		0x1C
+#define PAD_GPIO11_FUNC_SEL_SHIFT		0x5
+#define PAD_GPIO11_FUNC_SEL_MASK		0xE0
+#define PAD_GPIO12_FUNC_SEL_SHIFT		0x8
+#define PAD_GPIO12_FUNC_SEL_MASK		0x700
+#define PAD_GPIO13_FUNC_SEL_SHIFT		0xB
+#define PAD_GPIO13_FUNC_SEL_MASK		0x3800
+#define PAD_GPIO14_FUNC_SEL_SHIFT		0xE
+#define PAD_GPIO14_FUNC_SEL_MASK		0x1C000
+#define PAD_GPIO15_FUNC_SEL_SHIFT		0x11
+#define PAD_GPIO15_FUNC_SEL_MASK		0xE0000
+#define PAD_GPIO16_FUNC_SEL_SHIFT		0x14
+#define PAD_GPIO16_FUNC_SEL_MASK		0x700000
+#define PAD_GPIO17_FUNC_SEL_SHIFT		0x17
+#define PAD_GPIO17_FUNC_SEL_MASK		0x3800000
+#define PAD_GPIO18_FUNC_SEL_SHIFT		0x1A
+#define PAD_GPIO18_FUNC_SEL_MASK		0x1C000000
+#define PAD_GPIO19_FUNC_SEL_SHIFT		0x1D
+#define PAD_GPIO19_FUNC_SEL_MASK		0xE0000000
+#define SYS_IOMUX_CFGSAIF_672_ADDR		0x2a0
+#define PAD_GPIO20_FUNC_SEL_SHIFT		0x0
+#define PAD_GPIO20_FUNC_SEL_MASK		0x7
+#define PAD_GPIO21_FUNC_SEL_SHIFT		0x3
+#define PAD_GPIO21_FUNC_SEL_MASK		0x38
+#define PAD_GPIO22_FUNC_SEL_SHIFT		0x6
+#define PAD_GPIO22_FUNC_SEL_MASK		0x1C0
+#define PAD_GPIO23_FUNC_SEL_SHIFT		0x9
+#define PAD_GPIO23_FUNC_SEL_MASK		0xE00
+#define PAD_GPIO24_FUNC_SEL_SHIFT		0xC
+#define PAD_GPIO24_FUNC_SEL_MASK		0x7000
+#define PAD_GPIO25_FUNC_SEL_SHIFT		0xF
+#define PAD_GPIO25_FUNC_SEL_MASK		0x38000
+#define PAD_GPIO26_FUNC_SEL_SHIFT		0x12
+#define PAD_GPIO26_FUNC_SEL_MASK		0x1C0000
+#define PAD_GPIO27_FUNC_SEL_SHIFT		0x15
+#define PAD_GPIO27_FUNC_SEL_MASK		0xE00000
+#define PAD_GPIO28_FUNC_SEL_SHIFT		0x18
+#define PAD_GPIO28_FUNC_SEL_MASK		0x7000000
+#define PAD_GPIO29_FUNC_SEL_SHIFT		0x1B
+#define PAD_GPIO29_FUNC_SEL_MASK		0x38000000
+#define SYS_IOMUX_CFGSAIF_676_ADDR		0x2a4
+#define PAD_GPIO30_FUNC_SEL_SHIFT		0x0
+#define PAD_GPIO30_FUNC_SEL_MASK		0x7
+#define PAD_GPIO31_FUNC_SEL_SHIFT		0x3
+#define PAD_GPIO31_FUNC_SEL_MASK		0x38
+#define PAD_GPIO32_FUNC_SEL_SHIFT		0x6
+#define PAD_GPIO32_FUNC_SEL_MASK		0x1C0
+#define PAD_GPIO33_FUNC_SEL_SHIFT		0x9
+#define PAD_GPIO33_FUNC_SEL_MASK		0xE00
+#define PAD_GPIO34_FUNC_SEL_SHIFT		0xC
+#define PAD_GPIO34_FUNC_SEL_MASK		0x7000
+#define PAD_GPIO35_FUNC_SEL_SHIFT		0xF
+#define PAD_GPIO35_FUNC_SEL_MASK		0x18000
+#define PAD_GPIO36_FUNC_SEL_SHIFT		0x11
+#define PAD_GPIO36_FUNC_SEL_MASK		0xE0000
+#define PAD_GPIO37_FUNC_SEL_SHIFT		0x14
+#define PAD_GPIO37_FUNC_SEL_MASK		0x700000
+#define PAD_GPIO38_FUNC_SEL_SHIFT		0x17
+#define PAD_GPIO38_FUNC_SEL_MASK		0x3800000
+#define PAD_GPIO39_FUNC_SEL_SHIFT		0x1A
+#define PAD_GPIO39_FUNC_SEL_MASK		0x1C000000
+#define PAD_GPIO40_FUNC_SEL_SHIFT		0x1D
+#define PAD_GPIO40_FUNC_SEL_MASK		0xE0000000
+#define SYS_IOMUX_CFGSAIF_680_ADDR		0x2a8
+#define PAD_GPIO41_FUNC_SEL_SHIFT		0x0
+#define PAD_GPIO41_FUNC_SEL_MASK		0x7
+#define PAD_GPIO42_FUNC_SEL_SHIFT		0x3
+#define PAD_GPIO42_FUNC_SEL_MASK		0x38
+#define PAD_GPIO43_FUNC_SEL_SHIFT		0x6
+#define PAD_GPIO43_FUNC_SEL_MASK		0x1C0
+#define PAD_GPIO44_FUNC_SEL_SHIFT		0x9
+#define PAD_GPIO44_FUNC_SEL_MASK		0xE00
+#define PAD_GPIO45_FUNC_SEL_SHIFT		0xC
+#define PAD_GPIO45_FUNC_SEL_MASK		0x7000
+#define PAD_GPIO46_FUNC_SEL_SHIFT		0xF
+#define PAD_GPIO46_FUNC_SEL_MASK		0x38000
+#define PAD_GPIO47_FUNC_SEL_SHIFT		0x12
+#define PAD_GPIO47_FUNC_SEL_MASK		0x1C0000
+#define PAD_GPIO48_FUNC_SEL_SHIFT		0x15
+#define PAD_GPIO48_FUNC_SEL_MASK		0xE00000
+#define PAD_GPIO49_FUNC_SEL_SHIFT		0x18
+#define PAD_GPIO49_FUNC_SEL_MASK		0x7000000
+#define PAD_GPIO50_FUNC_SEL_SHIFT		0x1B
+#define PAD_GPIO50_FUNC_SEL_MASK		0x38000000
+#define PAD_GPIO51_FUNC_SEL_SHIFT		0x1E
+#define PAD_GPIO51_FUNC_SEL_MASK		0xC0000000
+#define SYS_IOMUX_CFGSAIF_684_ADDR		0x2ac
+#define PAD_GPIO52_FUNC_SEL_SHIFT		0x0
+#define PAD_GPIO52_FUNC_SEL_MASK		0x3
+#define PAD_GPIO53_FUNC_SEL_SHIFT		0x2
+#define PAD_GPIO53_FUNC_SEL_MASK		0xC
+#define PAD_GPIO54_FUNC_SEL_SHIFT		0x4
+#define PAD_GPIO54_FUNC_SEL_MASK		0x30
+#define PAD_GPIO55_FUNC_SEL_SHIFT		0x6
+#define PAD_GPIO55_FUNC_SEL_MASK		0x1C0
+#define PAD_GPIO56_FUNC_SEL_SHIFT		0x9
+#define PAD_GPIO56_FUNC_SEL_MASK		0xE00
+#define PAD_GPIO57_FUNC_SEL_SHIFT		0xC
+#define PAD_GPIO57_FUNC_SEL_MASK		0x7000
+#define PAD_GPIO58_FUNC_SEL_SHIFT		0xF
+#define PAD_GPIO58_FUNC_SEL_MASK		0x38000
+#define PAD_GPIO59_FUNC_SEL_SHIFT		0x12
+#define PAD_GPIO59_FUNC_SEL_MASK		0x1C0000
+#define PAD_GPIO60_FUNC_SEL_SHIFT		0x15
+#define PAD_GPIO60_FUNC_SEL_MASK		0xE00000
+#define PAD_GPIO61_FUNC_SEL_SHIFT		0x18
+#define PAD_GPIO61_FUNC_SEL_MASK		0x7000000
+#define PAD_GPIO62_FUNC_SEL_SHIFT		0x1B
+#define PAD_GPIO62_FUNC_SEL_MASK		0x38000000
+#define PAD_GPIO63_FUNC_SEL_SHIFT		0x1E
+#define PAD_GPIO63_FUNC_SEL_MASK		0xC0000000
+#define SYS_IOMUX_CFGSAIF_688_ADDR		0x2b0
+#define PAD_GPIO6_FUNC_SEL_SHIFT		0x0
+#define PAD_GPIO6_FUNC_SEL_MASK			0x3
+#define PAD_GPIO7_FUNC_SEL_SHIFT		0x2
+#define PAD_GPIO7_FUNC_SEL_MASK			0x1C
+#define PAD_GPIO8_FUNC_SEL_SHIFT		0x5
+#define PAD_GPIO8_FUNC_SEL_MASK			0xE0
+#define PAD_GPIO9_FUNC_SEL_SHIFT		0x8
+#define PAD_GPIO9_FUNC_SEL_MASK			0x700
+#define ISP_VIN_DVP_DATA0_FUNC_SEL_SHIFT	0xB
+#define ISP_VIN_DVP_DATA0_FUNC_SEL_MASK		0x3800
+#define ISP_VIN_DVP_DATA10_FUNC_SEL_SHIFT	0xE
+#define ISP_VIN_DVP_DATA10_FUNC_SEL_MASK	0x1C000
+#define ISP_VIN_DVP_DATA11_FUNC_SEL_SHIFT	0x11
+#define ISP_VIN_DVP_DATA11_FUNC_SEL_MASK	0xE0000
+#define ISP_VIN_DVP_DATA1_FUNC_SEL_SHIFT	0x14
+#define ISP_VIN_DVP_DATA1_FUNC_SEL_MASK		0x700000
+#define ISP_VIN_DVP_DATA2_FUNC_SEL_SHIFT	0x17
+#define ISP_VIN_DVP_DATA2_FUNC_SEL_MASK		0x3800000
+#define ISP_VIN_DVP_DATA3_FUNC_SEL_SHIFT	0x1A
+#define ISP_VIN_DVP_DATA3_FUNC_SEL_MASK		0x1C000000
+#define ISP_VIN_DVP_DATA4_FUNC_SEL_SHIFT	0x1D
+#define ISP_VIN_DVP_DATA4_FUNC_SEL_MASK		0xE0000000
+#define SYS_IOMUX_CFGSAIF_692_ADDR		0x2b4
+#define ISP_VIN_DVP_DATA5_FUNC_SEL_SHIFT	0x0
+#define ISP_VIN_DVP_DATA5_FUNC_SEL_MASK		0x7
+#define ISP_VIN_DVP_DATA6_FUNC_SEL_SHIFT	0x3
+#define ISP_VIN_DVP_DATA6_FUNC_SEL_MASK		0x38
+#define ISP_VIN_DVP_DATA7_FUNC_SEL_SHIFT	0x6
+#define ISP_VIN_DVP_DATA7_FUNC_SEL_MASK		0x1C0
+#define ISP_VIN_DVP_DATA8_FUNC_SEL_SHIFT	0x9
+#define ISP_VIN_DVP_DATA8_FUNC_SEL_MASK		0xE00
+#define ISP_VIN_DVP_DATA9_FUNC_SEL_SHIFT	0xC
+#define ISP_VIN_DVP_DATA9_FUNC_SEL_MASK		0x7000
+#define ISP_VIN_DVP_HVALID_FUNC_SEL_SHIFT	0xF
+#define ISP_VIN_DVP_HVALID_FUNC_SEL_MASK	0x38000
+#define ISP_VIN_DVP_VVALID_FUNC_SEL_SHIFT	0x12
+#define ISP_VIN_DVP_VVALID_FUNC_SEL_MASK	0x1C0000
+#define DVP_CLK_FUNC_SEL_SHIFT			0x15
+#define DVP_CLK_FUNC_SEL_MASK			0xE00000
+
+#define PAD_GMAC1_RXC_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GMAC1_RXC_FUNC_SEL_SHIFT		\
+	PAD_GMAC1_RXC_FUNC_SEL_MASK
+#define PAD_GPIO10_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO10_FUNC_SEL_SHIFT		\
+	PAD_GPIO10_FUNC_SEL_MASK
+#define PAD_GPIO11_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO11_FUNC_SEL_SHIFT		\
+	PAD_GPIO11_FUNC_SEL_MASK
+#define PAD_GPIO12_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO12_FUNC_SEL_SHIFT		\
+	PAD_GPIO12_FUNC_SEL_MASK
+#define PAD_GPIO13_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO13_FUNC_SEL_SHIFT		\
+	PAD_GPIO13_FUNC_SEL_MASK
+#define PAD_GPIO14_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO14_FUNC_SEL_SHIFT		\
+	PAD_GPIO14_FUNC_SEL_MASK
+#define PAD_GPIO15_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO15_FUNC_SEL_SHIFT		\
+	PAD_GPIO15_FUNC_SEL_MASK
+#define PAD_GPIO16_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO16_FUNC_SEL_SHIFT		\
+	PAD_GPIO16_FUNC_SEL_MASK
+#define PAD_GPIO17_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO17_FUNC_SEL_SHIFT		\
+	PAD_GPIO17_FUNC_SEL_MASK
+#define PAD_GPIO18_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO18_FUNC_SEL_SHIFT		\
+	PAD_GPIO18_FUNC_SEL_MASK
+#define PAD_GPIO19_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_668_ADDR		\
+	PAD_GPIO19_FUNC_SEL_SHIFT		\
+	PAD_GPIO19_FUNC_SEL_MASK
+#define PAD_GPIO20_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO20_FUNC_SEL_SHIFT		\
+	PAD_GPIO20_FUNC_SEL_MASK
+#define PAD_GPIO21_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO21_FUNC_SEL_SHIFT		\
+	PAD_GPIO21_FUNC_SEL_MASK
+#define PAD_GPIO22_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO22_FUNC_SEL_SHIFT		\
+	PAD_GPIO22_FUNC_SEL_MASK
+#define PAD_GPIO23_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO23_FUNC_SEL_SHIFT		\
+	PAD_GPIO23_FUNC_SEL_MASK
+#define PAD_GPIO24_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO24_FUNC_SEL_SHIFT		\
+	PAD_GPIO24_FUNC_SEL_MASK
+#define PAD_GPIO25_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO25_FUNC_SEL_SHIFT		\
+	PAD_GPIO25_FUNC_SEL_MASK
+#define PAD_GPIO26_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO26_FUNC_SEL_SHIFT		\
+	PAD_GPIO26_FUNC_SEL_MASK
+#define PAD_GPIO27_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO27_FUNC_SEL_SHIFT		\
+	PAD_GPIO27_FUNC_SEL_MASK
+#define PAD_GPIO28_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO28_FUNC_SEL_SHIFT		\
+	PAD_GPIO28_FUNC_SEL_MASK
+#define PAD_GPIO29_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_672_ADDR		\
+	PAD_GPIO29_FUNC_SEL_SHIFT		\
+	PAD_GPIO29_FUNC_SEL_MASK
+#define PAD_GPIO30_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO30_FUNC_SEL_SHIFT		\
+	PAD_GPIO30_FUNC_SEL_MASK
+#define PAD_GPIO31_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO31_FUNC_SEL_SHIFT		\
+	PAD_GPIO31_FUNC_SEL_MASK
+#define PAD_GPIO32_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO32_FUNC_SEL_SHIFT		\
+	PAD_GPIO32_FUNC_SEL_MASK
+#define PAD_GPIO33_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO33_FUNC_SEL_SHIFT		\
+	PAD_GPIO33_FUNC_SEL_MASK
+#define PAD_GPIO34_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO34_FUNC_SEL_SHIFT		\
+	PAD_GPIO34_FUNC_SEL_MASK
+#define PAD_GPIO35_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO35_FUNC_SEL_SHIFT		\
+	PAD_GPIO35_FUNC_SEL_MASK
+#define PAD_GPIO36_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO36_FUNC_SEL_SHIFT		\
+	PAD_GPIO36_FUNC_SEL_MASK
+#define PAD_GPIO37_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO37_FUNC_SEL_SHIFT		\
+	PAD_GPIO37_FUNC_SEL_MASK
+#define PAD_GPIO38_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO38_FUNC_SEL_SHIFT		\
+	PAD_GPIO38_FUNC_SEL_MASK
+#define PAD_GPIO39_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO39_FUNC_SEL_SHIFT		\
+	PAD_GPIO39_FUNC_SEL_MASK
+#define PAD_GPIO40_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_676_ADDR		\
+	PAD_GPIO40_FUNC_SEL_SHIFT		\
+	PAD_GPIO40_FUNC_SEL_MASK
+#define PAD_GPIO41_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO41_FUNC_SEL_SHIFT		\
+	PAD_GPIO41_FUNC_SEL_MASK
+#define PAD_GPIO42_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO42_FUNC_SEL_SHIFT		\
+	PAD_GPIO42_FUNC_SEL_MASK
+#define PAD_GPIO43_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO43_FUNC_SEL_SHIFT		\
+	PAD_GPIO43_FUNC_SEL_MASK
+#define PAD_GPIO44_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO44_FUNC_SEL_SHIFT		\
+	PAD_GPIO44_FUNC_SEL_MASK
+#define PAD_GPIO45_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO45_FUNC_SEL_SHIFT		\
+	PAD_GPIO45_FUNC_SEL_MASK
+#define PAD_GPIO46_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO46_FUNC_SEL_SHIFT		\
+	PAD_GPIO46_FUNC_SEL_MASK
+#define PAD_GPIO47_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO47_FUNC_SEL_SHIFT		\
+	PAD_GPIO47_FUNC_SEL_MASK
+#define PAD_GPIO48_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO48_FUNC_SEL_SHIFT		\
+	PAD_GPIO48_FUNC_SEL_MASK
+#define PAD_GPIO49_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO49_FUNC_SEL_SHIFT		\
+	PAD_GPIO49_FUNC_SEL_MASK
+#define PAD_GPIO50_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO50_FUNC_SEL_SHIFT		\
+	PAD_GPIO50_FUNC_SEL_MASK
+#define PAD_GPIO51_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_680_ADDR		\
+	PAD_GPIO51_FUNC_SEL_SHIFT		\
+	PAD_GPIO51_FUNC_SEL_MASK
+#define PAD_GPIO52_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO52_FUNC_SEL_SHIFT		\
+	PAD_GPIO52_FUNC_SEL_MASK
+#define PAD_GPIO53_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO53_FUNC_SEL_SHIFT		\
+	PAD_GPIO53_FUNC_SEL_MASK
+#define PAD_GPIO54_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO54_FUNC_SEL_SHIFT		\
+	PAD_GPIO54_FUNC_SEL_MASK
+#define PAD_GPIO55_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO55_FUNC_SEL_SHIFT		\
+	PAD_GPIO55_FUNC_SEL_MASK
+#define PAD_GPIO56_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO56_FUNC_SEL_SHIFT		\
+	PAD_GPIO56_FUNC_SEL_MASK
+#define PAD_GPIO57_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO57_FUNC_SEL_SHIFT		\
+	PAD_GPIO57_FUNC_SEL_MASK
+#define PAD_GPIO58_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO58_FUNC_SEL_SHIFT		\
+	PAD_GPIO58_FUNC_SEL_MASK
+#define PAD_GPIO59_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO59_FUNC_SEL_SHIFT		\
+	PAD_GPIO59_FUNC_SEL_MASK
+#define PAD_GPIO60_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO60_FUNC_SEL_SHIFT		\
+	PAD_GPIO60_FUNC_SEL_MASK
+#define PAD_GPIO61_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO61_FUNC_SEL_SHIFT		\
+	PAD_GPIO61_FUNC_SEL_MASK
+#define PAD_GPIO62_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO62_FUNC_SEL_SHIFT		\
+	PAD_GPIO62_FUNC_SEL_MASK
+#define PAD_GPIO63_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_684_ADDR		\
+	PAD_GPIO63_FUNC_SEL_SHIFT		\
+	PAD_GPIO63_FUNC_SEL_MASK
+#define PAD_GPIO6_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	PAD_GPIO6_FUNC_SEL_SHIFT		\
+	PAD_GPIO6_FUNC_SEL_MASK
+#define PAD_GPIO7_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	PAD_GPIO7_FUNC_SEL_SHIFT		\
+	PAD_GPIO7_FUNC_SEL_MASK
+#define PAD_GPIO8_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	PAD_GPIO8_FUNC_SEL_SHIFT		\
+	PAD_GPIO8_FUNC_SEL_MASK
+#define PAD_GPIO9_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	PAD_GPIO9_FUNC_SEL_SHIFT		\
+	PAD_GPIO9_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA0_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	ISP_VIN_DVP_DATA0_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA0_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA10_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	ISP_VIN_DVP_DATA10_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA10_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA11_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	ISP_VIN_DVP_DATA11_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA11_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA1_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	ISP_VIN_DVP_DATA1_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA1_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA2_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	ISP_VIN_DVP_DATA2_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA2_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA3_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	ISP_VIN_DVP_DATA3_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA3_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA4_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_688_ADDR		\
+	ISP_VIN_DVP_DATA4_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA4_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA5_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	ISP_VIN_DVP_DATA5_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA5_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA6_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	ISP_VIN_DVP_DATA6_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA6_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA7_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	ISP_VIN_DVP_DATA7_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA7_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA8_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	ISP_VIN_DVP_DATA8_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA8_FUNC_SEL_MASK
+#define ISP_VIN_DVP_DATA9_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	ISP_VIN_DVP_DATA9_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_DATA9_FUNC_SEL_MASK
+#define ISP_VIN_DVP_HVALID_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	ISP_VIN_DVP_HVALID_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_HVALID_FUNC_SEL_MASK
+#define ISP_VIN_DVP_VVALID_FUNC_SEL		\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	ISP_VIN_DVP_VVALID_FUNC_SEL_SHIFT	\
+	ISP_VIN_DVP_VVALID_FUNC_SEL_MASK
+#define DVP_CLK_FUNC_SEL			\
+	SYS_IOMUX_CFGSAIF_692_ADDR		\
+	DVP_CLK_FUNC_SEL_SHIFT			\
+	DVP_CLK_FUNC_SEL_MASK
+
+/* POS[0] */
+#define TESTEN_POS(data)	(((data) << 0x0) & 0x1)
+
+/* SMT[0] POS[1] */
+#define RSTN_SMT(data)		(((data) << 0x0) & 0x1)
+#define RSTN_POS(data)		(((data) << 0x1) & 0x2)
+
+/* DS[1:0] */
+#define OSC_DS(data)		(((data) << 0x0) & 0x3)
+
+/* sys ioconfig */
+/* IE[0] DS[2:1] PU[3] PD[4] SLEW[5] SMT[6] POS[7] */
+#define GPIO_IE(data)		(((data) << 0x0) & 0x1)
+#define GPIO_DS(data)		(((data) << 0x1) & 0x6)
+#define GPIO_PU(data)		(((data) << 0x3) & 0x8)
+#define GPIO_PD(data)		(((data) << 0x4) & 0x7)
+#define GPIO_SLEW(data)		(((data) << 0x5) & 0x20)
+#define GPIO_SMT(data)		(((data) << 0x6) & 0x40)
+#define GPIO_POS(data)		(((data) << 0x7) & 0x80)
+
+#define IO(config)		((config) & 0xFF)
+#define DOUT(dout)		((dout) & 0xFF)
+#define DOEN(doen)		((doen) & 0xFF)
+#define DIN(din_reg)		((din_reg) & 0xFF)
+
+/* syscon value */
+#define IO_3_3V			0 /* 00: 3.3v */
+#define IO_2_5V			1 /* 01: 2.5v */
+#define IO_1_8V			2 /* 10: 1.8v */
+
+#endif
-- 
2.17.1

Re: [PATCH v1 24/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions

[Krzysztof Kozlowski]

On 30/09/2022 09:33, Hal Feng wrote:
> From: Jianlong Huang <jianlong.huang@starfivetech.com>
> 
> Add pinctrl definitions for StarFive JH7110 SoC.
> 
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../pinctrl/pinctrl-starfive-jh7110.h         | 931 ++++++++++++++++++
>  1 file changed, 931 insertions(+)
>  create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
> 
> diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
> new file mode 100644
> index 000000000000..159cfcf6b915
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
> @@ -0,0 +1,931 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
> +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
> +
> +/* aon_iomux pin */
> +#define	PAD_TESTEN	0
> +#define	PAD_RGPIO0	1
> +#define	PAD_RGPIO1	2
> +#define	PAD_RGPIO2	3
> +#define	PAD_RGPIO3	4
> +#define	PAD_RSTN	5
> +#define	PAD_GMAC0_MDC	6
> +#define	PAD_GMAC0_MDIO	7
> +#define	PAD_GMAC0_RXD0	8
> +#define	PAD_GMAC0_RXD1	9
> +#define	PAD_GMAC0_RXD2	10
> +#define	PAD_GMAC0_RXD3	11
> +#define	PAD_GMAC0_RXDV	12
> +#define	PAD_GMAC0_RXC	13
> +#define	PAD_GMAC0_TXD0	14
> +#define	PAD_GMAC0_TXD1	15
> +#define	PAD_GMAC0_TXD2	16
> +#define	PAD_GMAC0_TXD3	17
> +#define	PAD_GMAC0_TXEN	18
> +#define	PAD_GMAC0_TXC	19
> +
> +/* aon_iomux dout */
> +#define GPO_AON_CLK_32K_OUT		2
> +#define GPO_AON_PTC0_PWM4		3
> +#define GPO_AON_PTC0_PWM5		4
> +#define GPO_AON_PTC0_PWM6		5
> +#define GPO_AON_PTC0_PWM7		6
> +#define GPO_AON_CLK_GCLK0		7
> +#define GPO_AON_CLK_GCLK1		8
> +#define GPO_AON_CLK_GCLK2		9
> +
> +/* aon_iomux doen */
> +#define OEN_AON_PTC0_OE_N_4		2
> +#define OEN_AON_PTC0_OE_N_5		3
> +#define OEN_AON_PTC0_OE_N_6		4
> +#define OEN_AON_PTC0_OE_N_7		5
> +
> +/* aon_iomux gin */
> +#define GPI_AON_PMU_GPIO_WAKEUP_0	0
> +#define GPI_AON_PMU_GPIO_WAKEUP_1	1
> +#define GPI_AON_PMU_GPIO_WAKEUP_2	2
> +#define GPI_AON_PMU_GPIO_WAKEUP_3	3
> +
> +/* aon_iomux gmac0 syscon */
> +#define PADCFG_PAD_GMAC0_MDC_SYSCON	0x58
> +#define PADCFG_PAD_GMAC0_MDIO_SYSCON	0x5c
> +#define PADCFG_PAD_GMAC0_RXD0_SYSCON	0x60
> +#define PADCFG_PAD_GMAC0_RXD1_SYSCON	0x64
> +#define PADCFG_PAD_GMAC0_RXD2_SYSCON	0x68
> +#define PADCFG_PAD_GMAC0_RXD3_SYSCON	0x6c
> +#define PADCFG_PAD_GMAC0_RXDV_SYSCON	0x70
> +#define PADCFG_PAD_GMAC0_RXC_SYSCON	0x74
> +#define PADCFG_PAD_GMAC0_TXD0_SYSCON	0x78
> +#define PADCFG_PAD_GMAC0_TXD1_SYSCON	0x7c
> +#define PADCFG_PAD_GMAC0_TXD2_SYSCON	0x80
> +#define PADCFG_PAD_GMAC0_TXD3_SYSCON	0x84
> +#define PADCFG_PAD_GMAC0_TXEN_SYSCON	0x88
> +#define PADCFG_PAD_GMAC0_TXC_SYSCON	0x8c

Register values do not belong to bindings. D

> +
> +/* aon_iomux func sel */
> +#define AON_IOMUX_CFGSAIF_144_ADDR	0x90
> +#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT	0x0
> +#define PAD_GMAC0_RXC_FUNC_SEL_MASK	0x3

Register values do not belong to bindings. D

> +
> +#define PAD_GMAC0_RXC_FUNC_SEL		\
> +	AON_IOMUX_CFGSAIF_144_ADDR	\
> +	PAD_GMAC0_RXC_FUNC_SEL_SHIFT	\
> +	PAD_GMAC0_RXC_FUNC_SEL_MASK
> +
> +/* sys_iomux pin */
> +#define	PAD_GPIO0	0
> +#define	PAD_GPIO1	1
> +#define	PAD_GPIO2	2
> +#define	PAD_GPIO3	3
> +#define	PAD_GPIO4	4
> +#define	PAD_GPIO5	5
> +#define	PAD_GPIO6	6
> +#define	PAD_GPIO7	7
> +#define	PAD_GPIO8	8
> +#define	PAD_GPIO9	9
> +#define	PAD_GPIO10	10
> +#define	PAD_GPIO11	11
> +#define	PAD_GPIO12	12
> +#define	PAD_GPIO13	13
> +#define	PAD_GPIO14	14
> +#define	PAD_GPIO15	15
> +#define	PAD_GPIO16	16
> +#define	PAD_GPIO17	17
> +#define	PAD_GPIO18	18
> +#define	PAD_GPIO19	19
> +#define	PAD_GPIO20	20
> +#define	PAD_GPIO21	21
> +#define	PAD_GPIO22	22
> +#define	PAD_GPIO23	23
> +#define	PAD_GPIO24	24
> +#define	PAD_GPIO25	25
> +#define	PAD_GPIO26	26
> +#define	PAD_GPIO27	27
> +#define	PAD_GPIO28	28
> +#define	PAD_GPIO29	29
> +#define	PAD_GPIO30	30
> +#define	PAD_GPIO31	31
> +#define	PAD_GPIO32	32
> +#define	PAD_GPIO33	33
> +#define	PAD_GPIO34	34
> +#define	PAD_GPIO35	35
> +#define	PAD_GPIO36	36
> +#define	PAD_GPIO37	37
> +#define	PAD_GPIO38	38
> +#define	PAD_GPIO39	39
> +#define	PAD_GPIO40	40
> +#define	PAD_GPIO41	41
> +#define	PAD_GPIO42	42
> +#define	PAD_GPIO43	43
> +#define	PAD_GPIO44	44
> +#define	PAD_GPIO45	45
> +#define	PAD_GPIO46	46
> +#define	PAD_GPIO47	47
> +#define	PAD_GPIO48	48
> +#define	PAD_GPIO49	49
> +#define	PAD_GPIO50	50
> +#define	PAD_GPIO51	51
> +#define	PAD_GPIO52	52
> +#define	PAD_GPIO53	53
> +#define	PAD_GPIO54	54
> +#define	PAD_GPIO55	55
> +#define	PAD_GPIO56	56
> +#define	PAD_GPIO57	57
> +#define	PAD_GPIO58	58
> +#define	PAD_GPIO59	59
> +#define	PAD_GPIO60	60
> +#define	PAD_GPIO61	61
> +#define	PAD_GPIO62	62
> +#define	PAD_GPIO63	63
> +#define	PAD_SD0_CLK	64
> +#define	PAD_SD0_CMD	65
> +#define	PAD_SD0_DATA0	66
> +#define	PAD_SD0_DATA1	67
> +#define	PAD_SD0_DATA2	68
> +#define	PAD_SD0_DATA3	69
> +#define	PAD_SD0_DATA4	70
> +#define	PAD_SD0_DATA5	71
> +#define	PAD_SD0_DATA6	72
> +#define	PAD_SD0_DATA7	73
> +#define	PAD_SD0_STRB	74
> +#define	PAD_GMAC1_MDC	75
> +#define	PAD_GMAC1_MDIO	76
> +#define	PAD_GMAC1_RXD0	77
> +#define	PAD_GMAC1_RXD1	78
> +#define	PAD_GMAC1_RXD2	79
> +#define	PAD_GMAC1_RXD3	80
> +#define	PAD_GMAC1_RXDV	81
> +#define	PAD_GMAC1_RXC	82
> +#define	PAD_GMAC1_TXD0	83
> +#define	PAD_GMAC1_TXD1	84
> +#define	PAD_GMAC1_TXD2	85
> +#define	PAD_GMAC1_TXD3	86
> +#define	PAD_GMAC1_TXEN	87
> +#define	PAD_GMAC1_TXC	88
> +#define	PAD_QSPI_SCLK	89
> +#define	PAD_QSPI_CSn0	90
> +#define	PAD_QSPI_DATA0	91
> +#define	PAD_QSPI_DATA1	92
> +#define	PAD_QSPI_DATA2	93
> +#define	PAD_QSPI_DATA3	94
> +
> +#define GPO_LOW					0
> +#define GPO_HIGH				1
> +#define GPO_WAVE511_0_O_UART_TXSOUT		2
> +#define GPO_CAN0_CTRL_STBY			3
> +#define GPO_CAN0_CTRL_TST_NEXT_BIT		4
> +#define GPO_CAN0_CTRL_TST_SAMPLE_POINT		5
> +#define GPO_CAN0_CTRL_TXD			6
> +#define GPO_USB0_DRIVE_VBUS_IO			7
> +#define GPO_QSPI0_CSN1				8
> +#define GPO_SPDIF0_SPDIFO			9
> +#define GPO_HDMI0_CEC_SDA_OUT			10
> +#define GPO_HDMI0_DDC_SCL_OUT			11
> +#define GPO_HDMI0_DDC_SDA_OUT			12
> +#define GPO_WDT0_WDOGRES			13
> +#define GPO_I2C0_IC_CLK_OUT_A			14
> +#define GPO_I2C0_IC_DATA_OUT_A			15
> +#define GPO_SDIO0_BACK_END_POWER		16
> +#define GPO_SDIO0_CARD_POWER_EN			17
> +#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N		18
> +#define GPO_SDIO0_RST_N				19
> +#define GPO_UART0_SOUT				20
> +#define GPO_JTAG_DSP_TDO			21
> +#define GPO_JTAG_CPU_CERTIFICATION_TDO		22
> +#define GPO_PDM_4MIC0_DMIC_MCLK			23
> +#define GPO_PTC0_PWM_0				24
> +#define GPO_PTC0_PWM_1				25
> +#define GPO_PTC0_PWM_2				26
> +#define GPO_PTC0_PWM_3				27
> +#define GPO_PWMDAC0_LEFT_OUTPUT			28
> +#define GPO_PWMDAC0_RIGHT_OUTPUT		29
> +#define GPO_SPI0_SSPCLKOUT			30
> +#define GPO_SPI0_SSPFSSOUT			31
> +#define GPO_SPI0_SSPTXD				32
> +#define GPO_GMAC0_CLK_PHY			33
> +#define GPO_I2SRX0_BCLK_MST			34
> +#define GPO_I2SRX0_LRCK_MST			35
> +#define GPO_I2STX0_BCLK_MST			36
> +#define GPO_I2STX0_LRCK_MST			37
> +#define GPO_CRG0_MCLK_OUT			38
> +#define GPO_TDM0_CLK_MST			39
> +#define GPO_TDM0_PCM_SYNCOUT			40
> +#define GPO_TDM0_PCM_TXD			41
> +#define GPO_U7MC_TRACE0_TDATA_0			42
> +#define GPO_U7MC_TRACE0_TDATA_1			43
> +#define GPO_U7MC_TRACE0_TDATA_2			44
> +#define GPO_U7MC_TRACE0_TDATA_3			45
> +#define GPO_U7MC_TRACE0_TREF			46
> +#define GPO_CAN1_CTRL_STBY			47
> +#define GPO_CAN1_CTRL_TST_NEXT_BIT		48
> +#define GPO_CAN1_CTRL_TST_SAMPLE_POINT		49
> +#define GPO_CAN1_CTRL_TXD			50
> +#define GPO_I2C1_IC_CLK_OUT_A			51
> +#define GPO_I2C1_IC_DATA_OUT_A			52
> +#define GPO_SDIO1_BACK_END_POWER		53
> +#define GPO_SDIO1_CARD_POWER_EN			54
> +#define GPO_SDIO1_CCLK_OUT			55
> +#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N		56
> +#define GPO_SDIO1_CCMD_OUT			57
> +#define GPO_SDIO1_CDATA_OUT_0			58
> +#define GPO_SDIO1_CDATA_OUT_1			59
> +#define GPO_SDIO1_CDATA_OUT_2			60
> +#define GPO_SDIO1_CDATA_OUT_3			61
> +#define GPO_SDIO1_CDATA_OUT_4			62
> +#define GPO_SDIO1_CDATA_OUT_5			63
> +#define GPO_SDIO1_CDATA_OUT_6			64
> +#define GPO_SDIO1_CDATA_OUT_7			65
> +#define GPO_SDIO1_RST_N				66
> +#define GPO_UART1_RTS_N				67
> +#define GPO_UART1_SOUT				68
> +#define GPO_I2STX_4CH1_SDO0			69
> +#define GPO_I2STX_4CH1_SDO1			70
> +#define GPO_I2STX_4CH1_SDO2			71
> +#define GPO_I2STX_4CH1_SDO3			72
> +#define GPO_SPI1_SSPCLKOUT			73
> +#define GPO_SPI1_SSPFSSOUT			74
> +#define GPO_SPI1_SSPTXD				75
> +#define GPO_I2C2_IC_CLK_OUT_A			76
> +#define GPO_I2C2_IC_DATA_OUT_A			77
> +#define GPO_UART2_RTS_N				78
> +#define GPO_UART2_SOUT				79
> +#define GPO_SPI2_SSPCLKOUT			80
> +#define GPO_SPI2_SSPFSSOUT			81
> +#define GPO_SPI2_SSPTXD				82
> +#define GPO_I2C3_IC_CLK_OUT_A			83
> +#define GPO_I2C3_IC_DATA_OUT_A			84
> +#define GPO_UART3_SOUT				85
> +#define GPO_SPI3_SSPCLKOUT			86
> +#define GPO_SPI3_SSPFSSOUT			87
> +#define GPO_SPI3_SSPTXD				88
> +#define GPO_I2C4_IC_CLK_OUT_A			89
> +#define GPO_I2C4_IC_DATA_OUT_A			90
> +#define GPO_UART4_RTS_N				91
> +#define GPO_UART4_SOUT				92
> +#define GPO_SPI4_SSPCLKOUT			93
> +#define GPO_SPI4_SSPFSSOUT			94
> +#define GPO_SPI4_SSPTXD				95
> +#define GPO_I2C5_IC_CLK_OUT_A			96
> +#define GPO_I2C5_IC_DATA_OUT_A			97
> +#define GPO_UART5_RTS_N				98
> +#define GPO_UART5_SOUT				99
> +#define GPO_SPI5_SSPCLKOUT			100
> +#define GPO_SPI5_SSPFSSOUT			101
> +#define GPO_SPI5_SSPTXD				102
> +#define GPO_I2C6_IC_CLK_OUT_A			103
> +#define GPO_I2C6_IC_DATA_OUT_A			104
> +#define GPO_SPI6_SSPCLKOUT			105
> +#define GPO_SPI6_SSPFSSOUT			106
> +#define GPO_SPI6_SSPTXD				107
> +#define GPO_NONE				108
> +
> +#define OEN_LOW					0
> +#define OEN_HIGH				1
> +#define OEN_HDMI0_CEC_SDA_OEN			2
> +#define OEN_HDMI0_DDC_SCL_OEN			3
> +#define OEN_HDMI0_DDC_SDA_OEN			4
> +#define OEN_I2C0_IC_CLK_OE			5
> +#define OEN_I2C0_IC_DATA_OE			6
> +#define OEN_JTAG_DSP_TDO_OEN			7
> +#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE	8
> +#define OEN_PTC0_PWM_0_OE_N			9
> +#define OEN_PTC0_PWM_1_OE_N			10
> +#define OEN_PTC0_PWM_2_OE_N			11
> +#define OEN_PTC0_PWM_3_OE_N			12
> +#define OEN_SPI0_NSSPCTLOE			13
> +#define OEN_SPI0_NSSPOE				14
> +#define OEN_TDM0_NPCM_SYNCOE			15
> +#define OEN_TDM0_NPCM_TXDOE			16
> +#define OEN_I2C1_IC_CLK_OE			17
> +#define OEN_I2C1_IC_DATA_OE			18
> +#define OEN_SDIO1_CCMD_OUT_EN			19
> +#define OEN_SDIO1_CDATA_OUT_EN_0		20
> +#define OEN_SDIO1_CDATA_OUT_EN_1		21
> +#define OEN_SDIO1_CDATA_OUT_EN_2		22
> +#define OEN_SDIO1_CDATA_OUT_EN_3		23
> +#define OEN_SDIO1_CDATA_OUT_EN_4		24
> +#define OEN_SDIO1_CDATA_OUT_EN_5		25
> +#define OEN_SDIO1_CDATA_OUT_EN_6		26
> +#define OEN_SDIO1_CDATA_OUT_EN_7		27
> +#define OEN_SPI1_NSSPCTLOE			28
> +#define OEN_SPI1_NSSPOE				29
> +#define OEN_I2C2_IC_CLK_OE			30
> +#define OEN_I2C2_IC_DATA_OE			31
> +#define OEN_SPI2_NSSPCTLOE			32
> +#define OEN_SPI2_NSSPOE				33
> +#define OEN_I2C3_IC_CLK_OE			34
> +#define OEN_I2C3_IC_DATA_OE			35
> +#define OEN_SPI3_NSSPCTLOE			36
> +#define OEN_SPI3_NSSPOE				37
> +#define OEN_I2C4_IC_CLK_OE			38
> +#define OEN_I2C4_IC_DATA_OE			39
> +#define OEN_SPI4_NSSPCTLOE			40
> +#define OEN_SPI4_NSSPOE				41
> +#define OEN_I2C5_IC_CLK_OE			42
> +#define OEN_I2C5_IC_DATA_OE			43
> +#define OEN_SPI5_NSSPCTLOE			44
> +#define OEN_SPI5_NSSPOE				45
> +#define OEN_I2C6_IC_CLK_OE			46
> +#define OEN_I2C6_IC_DATA_OE			47
> +#define OEN_SPI6_NSSPCTLOE			48
> +#define OEN_SPI6_NSSPOE				49
> +#define OEN_NONE				50
> +
> +#define GPI_WAVE511_0_I_UART_RXSIN		0
> +#define GPI_CAN0_CTRL_RXD			1
> +#define GPI_USB0_OVERCURRENT_N_IO		2
> +#define GPI_SPDIF0_SPDIFI			3
> +#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN	4
> +#define GPI_HDMI0_CEC_SDA_IN			5
> +#define GPI_HDMI0_DDC_SCL_IN			6
> +#define GPI_HDMI0_DDC_SDA_IN			7
> +#define GPI_HDMI0_HPD				8
> +#define GPI_I2C0_IC_CLK_IN_A			9
> +#define GPI_I2C0_IC_DATA_IN_A			10
> +#define GPI_SDIO0_CARD_DETECT_N			11
> +#define GPI_SDIO0_CARD_INT_N			12
> +#define GPI_SDIO0_CARD_WRITE_PRT		13
> +#define GPI_UART0_SIN				14
> +#define GPI_JTAG_DSP_TCK			15
> +#define GPI_JTAG_DSP_TDI			16
> +#define GPI_JTAG_DSP_TMS			17
> +#define GPI_JTAG_DSP_TRST_N			18
> +#define GPI_JTAG_CPU_CERTIFICATION_TDI		19
> +#define GPI_JTAG_CPU_CERTIFICATION_TMS		20
> +#define GPI_PDM_4MIC0_DMIC0_DIN			21
> +#define GPI_PDM_4MIC0_DMIC1_DIN			22
> +#define GPI_I2SRX0_EXT_SDIN0			23
> +#define GPI_I2SRX0_EXT_SDIN1			24
> +#define GPI_I2SRX0_EXT_SDIN2			25
> +#define GPI_SPI0_SSPCLKIN			26
> +#define GPI_SPI0_SSPFSSIN			27
> +#define GPI_SPI0_SSPRXD				28
> +#define GPI_JTAG_CPU_CERTIFICATION_TCK		29
> +#define GPI_CRG0_EXT_MCLK			30
> +#define GPI_I2SRX0_BCLK_SLV			31
> +#define GPI_I2SRX0_LRCK_SLV			32
> +#define GPI_I2STX0_BCLK_SLV			33
> +#define GPI_I2STX0_LRCK_SLV			34
> +#define GPI_TDM0_CLK_SLV			35
> +#define GPI_TDM0_PCM_RXD			36
> +#define GPI_TDM0_PCM_SYNCIN			37
> +#define GPI_CAN1_CTRL_RXD			38
> +#define GPI_I2C1_IC_CLK_IN_A			39
> +#define GPI_I2C1_IC_DATA_IN_A			40
> +#define GPI_SDIO1_CARD_DETECT_N			41
> +#define GPI_SDIO1_CARD_INT_N			42
> +#define GPI_SDIO1_CARD_WRITE_PRT		43
> +#define GPI_SDIO1_CCMD_IN			44
> +#define GPI_SDIO1_CDATA_IN_0			45
> +#define GPI_SDIO1_CDATA_IN_1			46
> +#define GPI_SDIO1_CDATA_IN_2			47
> +#define GPI_SDIO1_CDATA_IN_3			48
> +#define GPI_SDIO1_CDATA_IN_4			49
> +#define GPI_SDIO1_CDATA_IN_5			50
> +#define GPI_SDIO1_CDATA_IN_6			51
> +#define GPI_SDIO1_CDATA_IN_7			52
> +#define GPI_SDIO1_DATA_STROBE			53
> +#define GPI_UART1_CTS_N				54
> +#define GPI_UART1_SIN				55
> +#define GPI_SPI1_SSPCLKIN			56
> +#define GPI_SPI1_SSPFSSIN			57
> +#define GPI_SPI1_SSPRXD				58
> +#define GPI_I2C2_IC_CLK_IN_A			59
> +#define GPI_I2C2_IC_DATA_IN_A			60
> +#define GPI_UART2_CTS_N				61
> +#define GPI_UART2_SIN				62
> +#define GPI_SPI2_SSPCLKIN			63
> +#define GPI_SPI2_SSPFSSIN			64
> +#define GPI_SPI2_SSPRXD				65
> +#define GPI_I2C3_IC_CLK_IN_A			66
> +#define GPI_I2C3_IC_DATA_IN_A			67
> +#define GPI_UART3_SIN				68
> +#define GPI_SPI3_SSPCLKIN			69
> +#define GPI_SPI3_SSPFSSIN			70
> +#define GPI_SPI3_SSPRXD				71
> +#define GPI_I2C4_IC_CLK_IN_A			72
> +#define GPI_I2C4_IC_DATA_IN_A			73
> +#define GPI_UART4_CTS_N				74
> +#define GPI_UART4_SIN				75
> +#define GPI_SPI4_SSPCLKIN			76
> +#define GPI_SPI4_SSPFSSIN			77
> +#define GPI_SPI4_SSPRXD				78
> +#define GPI_I2C5_IC_CLK_IN_A			79
> +#define GPI_I2C5_IC_DATA_IN_A			80
> +#define GPI_UART5_CTS_N				81
> +#define GPI_UART5_SIN				82
> +#define GPI_SPI5_SSPCLKIN			83
> +#define GPI_SPI5_SSPFSSIN			84
> +#define GPI_SPI5_SSPRXD				85
> +#define GPI_I2C6_IC_CLK_IN_A			86
> +#define GPI_I2C6_IC_DATA_IN_A			87
> +#define GPI_SPI6_SSPCLKIN			88
> +#define GPI_SPI6_SSPFSSIN			89
> +#define GPI_SPI6_SSPRXD				90
> +#define	GPI_NONE				91
> +
> +/* sys_iomux syscon */
> +#define PADCFG_PAD_GMAC1_MDC_SYSCON		0x24c
> +#define PADCFG_PAD_GMAC1_MDIO_SYSCON		0x250
> +#define PADCFG_PAD_GMAC1_RXD0_SYSCON		0x254

Register values do not belong to bindings. Drop everything also below.

> +#define PADCFG_PAD_GMAC1_RXD1_SYSCON		0x258
> +#define PADCFG_PAD_GMAC1_RXD2_SYSCON		0x25c
> +#define PADCFG_PAD_GMAC1_RXD3_SYSCON		0x260
> +#define PADCFG_PAD_GMAC1_RXDV_SYSCON		0x264
> +#define PADCFG_PAD_GMAC1_RXC_SYSCON		0x268
> +#define PADCFG_PAD_GMAC1_TXD0_SYSCON		0x26c


Best regards,
Krzysztof

[PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings

[Hal Feng]

From: Jianlong Huang <jianlong.huang@starfivetech.com>

Add pinctrl bindings for StarFive JH7110 SoC.

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 .../pinctrl/starfive,jh7110-pinctrl.yaml      | 202 ++++++++++++++++++
 1 file changed, 202 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
new file mode 100644
index 000000000000..482012ad8a14
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
@@ -0,0 +1,202 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Pin Controller Device Tree Bindings
+
+description: |
+  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
+
+maintainers:
+  - Jianlong Huang <jianlong.huang@starfivetech.com>
+
+properties:
+  compatible:
+    enum:
+    - starfive,jh7110-sys-pinctrl
+    - starfive,jh7110-aon-pinctrl
+
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: control
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  "#gpio-cells":
+    const: 2
+
+  interrupts:
+    maxItems: 1
+    description: The GPIO parent interrupt.
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+  ngpios:
+    enum:
+    - 64
+    - 4
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - "#gpio-cells"
+  - interrupts
+  - interrupt-controller
+  - "#interrupt-cells"
+
+patternProperties:
+  '-[0-9]+$':
+    type: object
+    patternProperties:
+      '-pins$':
+        type: object
+        description: |
+          A pinctrl node should contain at least one subnode representing the
+          pinctrl groups available on the machine. Each subnode will list the
+          pins it needs, and how they should be configured, with regard to
+          muxer configuration, system signal configuration, pin groups for
+          vin/vout module, pin voltage, mux functions for output, mux functions
+          for output enable, mux functions for input.
+
+        properties:
+          starfive,pins:
+            description: |
+              The list of pin identifiers that properties in the node apply to.
+              This should be set using the PAD_GPIOX macros.
+              This has to be specified.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 63
+
+          starfive,pinmux:
+            description: |
+              The list of GPIOs and their mux functions that properties in the
+              node apply to. This should be set using the PAD_GPIOX_FUNC_SEL
+              macro with its value.
+              This is optional for some pins.
+              The value of PAD_GPIOX_FUNC_SEL macro can selects:
+                0: GPIOX mux function 0,
+                1: GPIOX mux function 1,
+                2: GPIOX mux function 2.
+
+          starfive,pin-ioconfig:
+            description: |
+              This is used to configure the core settings of system signals.
+              The combination of GPIO_IE or GPIO_DS or GPIO_PU or GPIO_PD or
+              GPIO_SLEW or GPIO_SMT or GPIO_POS.
+            $ref: /schemas/types.yaml#/definitions/uint32
+
+          starfive,padmux:
+            description: |
+              The padmux is for vin/vout module to select pin groups.
+              0: vout will be set at pins from PAD_GPIO7 to PAD_GPIO34,
+                 when PAD_GPIOX_FUNC_SEL is set as 1.
+                 vin will be set at pins from PAD_GPIO6 to PAD_GPIO20.
+                 when PAD_GPIOX_FUNC_SEL is set as 2.
+              1: vout will be set at pins from PAD_GPIO36 to PAD_GPIO63,
+                 when PAD_GPIOX_FUNC_SEL is set as 1.
+                 vin will be set at pins from PAD_GPIO21 to PAD_GPIO35.
+                 when PAD_GPIOX_FUNC_SEL is set as 2.
+              2: vin will be set at pins from PAD_GPIO36 to PAD_GPIO50,
+                 when PAD_GPIOX_FUNC_SEL is set as 2
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2]
+
+          starfive,pin-syscon:
+            description: |
+              This is used to set pin voltage,
+              0: 3.3V, 1: 2.5V, 2: 1.8V.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2]
+
+          starfive,pin-gpio-dout:
+            description: |
+              This is used to set their mux functions for output.
+              This should be set using the GPO_XXX macro,
+              such as GPO_LOW, GPO_UART0_SOUT.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 107
+
+          starfive,pin-gpio-doen:
+            description: |
+              This is used to set their mux functions for output enable.
+              This should be set using the OEN_XXX macro,
+              such as OEN_LOW, OEN_I2C0_IC_CLK_OE.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 49
+
+          starfive,pin-gpio-din:
+            description: |
+              This is used to set their mux functions for input.
+              This should be set using the GPI_XXX macro,
+              such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 90
+
+        additionalProperties: false
+
+    additionalProperties: false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-sys.h>
+    #include <dt-bindings/reset/starfive-jh7110.h>
+    #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+
+    gpio: gpio@13040000 {
+      compatible = "starfive,jh7110-sys-pinctrl";
+      reg = <0x0 0x13040000 0x0 0x10000>;
+      reg-names = "control";
+      clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
+      resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
+      interrupts = <86>;
+      interrupt-controller;
+      #gpio-cells = <2>;
+      ngpios = <64>;
+      status = "okay";
+
+      uart0_pins: uart0-pins {
+        uart0-pins-tx {
+          starfive,pins = <PAD_GPIO5>;
+          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+          starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+          starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+
+        uart0-pins-rx {
+          starfive,pins = <PAD_GPIO6>;
+          starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
+          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+          starfive,pin-gpio-doen = <OEN_HIGH>;
+          starfive,pin-gpio-din =  <GPI_UART0_SIN>;
+        };
+      };
+    };
+
+    &uart0 {
+      pinctrl-names = "default";
+      pinctrl-0 = <&uart0_pins>;
+      status = "okay";
+    };
+
+...
-- 
2.17.1

Re: [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings

[Krzysztof Kozlowski]

On 30/09/2022 09:38, Hal Feng wrote:
> From: Jianlong Huang <jianlong.huang@starfivetech.com>
> 
> Add pinctrl bindings for StarFive JH7110 SoC.
> 
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../pinctrl/starfive,jh7110-pinctrl.yaml      | 202 ++++++++++++++++++
>  1 file changed, 202 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
> new file mode 100644
> index 000000000000..482012ad8a14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Pin Controller Device Tree Bindings
> +
> +description: |
> +  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
> +
> +maintainers:
> +  - Jianlong Huang <jianlong.huang@starfivetech.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +    - starfive,jh7110-sys-pinctrl
> +    - starfive,jh7110-aon-pinctrl

Wrong indentation.

Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).

> +
> +  reg:
> +    minItems: 2

No need.

> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: control

This does not match reg at all. Again - not tested.


> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  "#gpio-cells":
> +    const: 2
> +
> +  interrupts:
> +    maxItems: 1
> +    description: The GPIO parent interrupt.
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2
> +
> +  ngpios:
> +    enum:
> +    - 64
> +    - 4

Wrong indentation. Increasing order.

> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - "#gpio-cells"
> +  - interrupts
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +patternProperties:

This goes before required block

> +  '-[0-9]+$':

Too loose pattern. Need some more specific pattern. What do you exactly
match here?

Missing description.

> +    type: object
> +    patternProperties:
> +      '-pins$':
> +        type: object
> +        description: |
> +          A pinctrl node should contain at least one subnode representing the
> +          pinctrl groups available on the machine. Each subnode will list the
> +          pins it needs, and how they should be configured, with regard to
> +          muxer configuration, system signal configuration, pin groups for
> +          vin/vout module, pin voltage, mux functions for output, mux functions
> +          for output enable, mux functions for input.
> +
> +        properties:
> +          starfive,pins:

No, use generic pinctrl bindings.

> +            description: |
> +              The list of pin identifiers that properties in the node apply to.
> +              This should be set using the PAD_GPIOX macros.
> +              This has to be specified.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 63
> +
> +          starfive,pinmux:

No, use generic pinctrl bindings.


> +            description: |
> +              The list of GPIOs and their mux functions that properties in the
> +              node apply to. This should be set using the PAD_GPIOX_FUNC_SEL
> +              macro with its value.
> +              This is optional for some pins.
> +              The value of PAD_GPIOX_FUNC_SEL macro can selects:
> +                0: GPIOX mux function 0,
> +                1: GPIOX mux function 1,
> +                2: GPIOX mux function 2.
> +
> +          starfive,pin-ioconfig:
> +            description: |
> +              This is used to configure the core settings of system signals.
> +              The combination of GPIO_IE or GPIO_DS or GPIO_PU or GPIO_PD or
> +              GPIO_SLEW or GPIO_SMT or GPIO_POS.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +
> +          starfive,padmux:
> +            description: |
> +              The padmux is for vin/vout module to select pin groups.
> +              0: vout will be set at pins from PAD_GPIO7 to PAD_GPIO34,
> +                 when PAD_GPIOX_FUNC_SEL is set as 1.
> +                 vin will be set at pins from PAD_GPIO6 to PAD_GPIO20.
> +                 when PAD_GPIOX_FUNC_SEL is set as 2.
> +              1: vout will be set at pins from PAD_GPIO36 to PAD_GPIO63,
> +                 when PAD_GPIOX_FUNC_SEL is set as 1.
> +                 vin will be set at pins from PAD_GPIO21 to PAD_GPIO35.
> +                 when PAD_GPIOX_FUNC_SEL is set as 2.
> +              2: vin will be set at pins from PAD_GPIO36 to PAD_GPIO50,
> +                 when PAD_GPIOX_FUNC_SEL is set as 2
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +          starfive,pin-syscon:
> +            description: |
> +              This is used to set pin voltage,
> +              0: 3.3V, 1: 2.5V, 2: 1.8V.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +          starfive,pin-gpio-dout:

No, use generic pinctrl bindings.


> +            description: |
> +              This is used to set their mux functions for output.
> +              This should be set using the GPO_XXX macro,
> +              such as GPO_LOW, GPO_UART0_SOUT.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 107
> +
> +          starfive,pin-gpio-doen:

No, use generic pinctrl bindings.


> +            description: |
> +              This is used to set their mux functions for output enable.
> +              This should be set using the OEN_XXX macro,
> +              such as OEN_LOW, OEN_I2C0_IC_CLK_OE.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 49
> +
> +          starfive,pin-gpio-din:

No, use generic pinctrl bindings.

> +            description: |
> +              This is used to set their mux functions for input.
> +              This should be set using the GPI_XXX macro,
> +              such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 90
> +
> +        additionalProperties: false
> +
> +    additionalProperties: false
> +
> +additionalProperties: false

Missing allof to generic pinctrl bindings.

> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive-jh7110-sys.h>
> +    #include <dt-bindings/reset/starfive-jh7110.h>
> +    #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> +    gpio: gpio@13040000 {
> +      compatible = "starfive,jh7110-sys-pinctrl";
> +      reg = <0x0 0x13040000 0x0 0x10000>;
> +      reg-names = "control";
> +      clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
> +      resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
> +      interrupts = <86>;
> +      interrupt-controller;
> +      #gpio-cells = <2>;
> +      ngpios = <64>;
> +      status = "okay";
> +
> +      uart0_pins: uart0-pins {

Explain me please how it can possible match your pattern: '-[0-9]+$':

You really wrote something which was not tested and cannot work.
> +        uart0-pins-tx {
> +          starfive,pins = <PAD_GPIO5>;
> +          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
> +          starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
> +          starfive,pin-gpio-doen = <OEN_LOW>;
> +        };
> +
> +        uart0-pins-rx {
> +          starfive,pins = <PAD_GPIO6>;
> +          starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
> +          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
> +          starfive,pin-gpio-doen = <OEN_HIGH>;
> +          starfive,pin-gpio-din =  <GPI_UART0_SIN>;
> +        };
> +      };
> +    };
> +
> +    &uart0 {
> +      pinctrl-names = "default";
> +      pinctrl-0 = <&uart0_pins>;
> +      status = "okay";

Drop, obvious.

> +    };
> +
> +...

Best regards,
Krzysztof

Re: [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings

[Rob Herring]

On Fri, 30 Sep 2022 15:38:45 +0800, Hal Feng wrote:
> From: Jianlong Huang <jianlong.huang@starfivetech.com>
> 
> Add pinctrl bindings for StarFive JH7110 SoC.
> 
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../pinctrl/starfive,jh7110-pinctrl.yaml      | 202 ++++++++++++++++++
>  1 file changed, 202 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml:18:5: [warning] wrong indentation: expected 6 but found 4 (indentation)
./Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml:49:5: [warning] wrong indentation: expected 6 but found 4 (indentation)

dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml: error checking schema file
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml: ignoring, error in schema: patternProperties: -[0-9]+$: patternProperties: -pins$: properties: starfive,pinmux
Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.example.dts:21:18: fatal error: dt-bindings/clock/starfive-jh7110-sys.h: No such file or directory
   21 |         #include <dt-bindings/clock/starfive-jh7110-sys.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1420: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings

[Icenowy Zheng]

在 2022-09-30星期五的 15:38 +0800，Hal Feng写道：
> From: Jianlong Huang <jianlong.huang@starfivetech.com>
> 
> Add pinctrl bindings for StarFive JH7110 SoC.
> 
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../pinctrl/starfive,jh7110-pinctrl.yaml      | 202
> ++++++++++++++++++
>  1 file changed, 202 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> 
> diff --git
> a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> new file mode 100644
> index 000000000000..482012ad8a14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id:
> http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Pin Controller Device Tree Bindings
> +
> +description: |
> +  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
> +
> +maintainers:
> +  - Jianlong Huang <jianlong.huang@starfivetech.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +    - starfive,jh7110-sys-pinctrl
> +    - starfive,jh7110-aon-pinctrl
> +
> +  reg:
> +    minItems: 2
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: control
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  "#gpio-cells":
> +    const: 2
> +
> +  interrupts:
> +    maxItems: 1
> +    description: The GPIO parent interrupt.
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2
> +
> +  ngpios:
> +    enum:
> +    - 64
> +    - 4
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - "#gpio-cells"
> +  - interrupts
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +patternProperties:
> +  '-[0-9]+$':
> +    type: object
> +    patternProperties:
> +      '-pins$':
> +        type: object
> +        description: |
> +          A pinctrl node should contain at least one subnode
> representing the
> +          pinctrl groups available on the machine. Each subnode will
> list the
> +          pins it needs, and how they should be configured, with
> regard to
> +          muxer configuration, system signal configuration, pin
> groups for
> +          vin/vout module, pin voltage, mux functions for output,
> mux functions
> +          for output enable, mux functions for input.
> +
> +        properties:
> +          starfive,pins:
> +            description: |
> +              The list of pin identifiers that properties in the
> node apply to.
> +              This should be set using the PAD_GPIOX macros.
> +              This has to be specified.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 63

Hi,

I am adapting for Pine64's Star64 board, which utilizes a JH7110 SoC.

It does not features a USB overcurrent pin as GPIO, thus this pin needs
to be routed in PIO controller to fixed 1 (by writing 1 to
SYS_IOMUX_CFGSAIF__SYSCFG_FMUX_32[22:16]).

I think this kind of situation needs to be considered as part of DT
binding.

BTW if you have any difficulty refactoring the DT binding to standard
pinconf one, I am free to provide help.

Thanks,
Icenowy Zheng

> +
> +          starfive,pinmux:
> +            description: |
> +              The list of GPIOs and their mux functions that
> properties in the
> +              node apply to. This should be set using the
> PAD_GPIOX_FUNC_SEL
> +              macro with its value.
> +              This is optional for some pins.
> +              The value of PAD_GPIOX_FUNC_SEL macro can selects:
> +                0: GPIOX mux function 0,
> +                1: GPIOX mux function 1,
> +                2: GPIOX mux function 2.
> +
> +          starfive,pin-ioconfig:
> +            description: |
> +              This is used to configure the core settings of system
> signals.
> +              The combination of GPIO_IE or GPIO_DS or GPIO_PU or
> GPIO_PD or
> +              GPIO_SLEW or GPIO_SMT or GPIO_POS.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +
> +          starfive,padmux:
> +            description: |
> +              The padmux is for vin/vout module to select pin
> groups.
> +              0: vout will be set at pins from PAD_GPIO7 to
> PAD_GPIO34,
> +                 when PAD_GPIOX_FUNC_SEL is set as 1.
> +                 vin will be set at pins from PAD_GPIO6 to
> PAD_GPIO20.
> +                 when PAD_GPIOX_FUNC_SEL is set as 2.
> +              1: vout will be set at pins from PAD_GPIO36 to
> PAD_GPIO63,
> +                 when PAD_GPIOX_FUNC_SEL is set as 1.
> +                 vin will be set at pins from PAD_GPIO21 to
> PAD_GPIO35.
> +                 when PAD_GPIOX_FUNC_SEL is set as 2.
> +              2: vin will be set at pins from PAD_GPIO36 to
> PAD_GPIO50,
> +                 when PAD_GPIOX_FUNC_SEL is set as 2
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +          starfive,pin-syscon:
> +            description: |
> +              This is used to set pin voltage,
> +              0: 3.3V, 1: 2.5V, 2: 1.8V.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +          starfive,pin-gpio-dout:
> +            description: |
> +              This is used to set their mux functions for output.
> +              This should be set using the GPO_XXX macro,
> +              such as GPO_LOW, GPO_UART0_SOUT.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 107
> +
> +          starfive,pin-gpio-doen:
> +            description: |
> +              This is used to set their mux functions for output
> enable.
> +              This should be set using the OEN_XXX macro,
> +              such as OEN_LOW, OEN_I2C0_IC_CLK_OE.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 49
> +
> +          starfive,pin-gpio-din:
> +            description: |
> +              This is used to set their mux functions for input.
> +              This should be set using the GPI_XXX macro,
> +              such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 90
> +
> +        additionalProperties: false
> +
> +    additionalProperties: false
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive-jh7110-sys.h>
> +    #include <dt-bindings/reset/starfive-jh7110.h>
> +    #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> +    gpio: gpio@13040000 {
> +      compatible = "starfive,jh7110-sys-pinctrl";
> +      reg = <0x0 0x13040000 0x0 0x10000>;
> +      reg-names = "control";
> +      clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
> +      resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
> +      interrupts = <86>;
> +      interrupt-controller;
> +      #gpio-cells = <2>;
> +      ngpios = <64>;
> +      status = "okay";
> +
> +      uart0_pins: uart0-pins {
> +        uart0-pins-tx {
> +          starfive,pins = <PAD_GPIO5>;
> +          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
> +          starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
> +          starfive,pin-gpio-doen = <OEN_LOW>;
> +        };
> +
> +        uart0-pins-rx {
> +          starfive,pins = <PAD_GPIO6>;
> +          starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
> +          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
> +          starfive,pin-gpio-doen = <OEN_HIGH>;
> +          starfive,pin-gpio-din =  <GPI_UART0_SIN>;
> +        };
> +      };
> +    };
> +
> +    &uart0 {
> +      pinctrl-names = "default";
> +      pinctrl-0 = <&uart0_pins>;
> +      status = "okay";
> +    };
> +
> +...

[PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver

[Hal Feng]

From: Jianlong Huang <jianlong.huang@starfivetech.com>

Add pinctrl driver for StarFive JH7110 SoC.

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 MAINTAINERS                                   |   9 +-
 drivers/pinctrl/starfive/Kconfig              |  20 +
 drivers/pinctrl/starfive/Makefile             |   5 +
 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 718 ++++++++++++++
 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 925 ++++++++++++++++++
 drivers/pinctrl/starfive/pinctrl-starfive.c   | 539 ++++++++++
 drivers/pinctrl/starfive/pinctrl-starfive.h   | 131 +++
 7 files changed, 2343 insertions(+), 4 deletions(-)
 create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
 create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 70d64d2afb0c..6847dee99603 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19404,13 +19404,14 @@ F:	Documentation/devicetree/bindings/clock/starfive*
 F:	drivers/clk/starfive/
 F:	include/dt-bindings/clock/starfive*
 
-STARFIVE JH7100 PINCTRL DRIVER
+STARFIVE PINCTRL DRIVER
 M:	Emil Renner Berthing <kernel@esmil.dk>
+M:	Jianlong Huang <jianlong.huang@starfivetech.com>
 L:	linux-gpio@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
-F:	drivers/pinctrl/pinctrl-starfive.c
-F:	include/dt-bindings/pinctrl/pinctrl-starfive.h
+F:	Documentation/devicetree/bindings/pinctrl/starfive*
+F:	drivers/pinctrl/starfive/
+F:	include/dt-bindings/pinctrl/pinctrl-starfive*
 
 STARFIVE RESET CONTROLLER DRIVER
 M:	Emil Renner Berthing <kernel@esmil.dk>
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 5cedb546f93d..fde39f4a7922 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -17,3 +17,23 @@ config PINCTRL_STARFIVE_JH7100
 	  peripherals supporting inputs, outputs, configuring pull-up/pull-down
 	  and interrupts on input changes.
 
+config PINCTRL_STARFIVE
+	bool
+	select GENERIC_PINCTRL_GROUPS
+	select GENERIC_PINMUX_FUNCTIONS
+	select GENERIC_PINCONF
+	select GPIOLIB
+	select GPIOLIB_IRQCHIP
+	select OF_GPIO
+
+config PINCTRL_STARFIVE_JH7110
+	bool "Pinctrl and GPIO driver for the StarFive JH7110 SoC"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on OF
+	select PINCTRL_STARFIVE
+	default SOC_STARFIVE
+	help
+	  Say yes here to support pin control on the StarFive JH7110 SoC.
+	  This also provides an interface to the GPIO pins not used by other
+	  peripherals supporting inputs, outputs, configuring pull-up/pull-down
+	  and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 0293f26a0a99..17cdd1b0e650 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -1,3 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 
+# Core
+obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
+
+# SoC Drivers
 obj-$(CONFIG_PINCTRL_STARFIVE_JH7100)	+= pinctrl-starfive-jh7100.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JH7110)	+= pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
new file mode 100644
index 000000000000..058acd3ff305
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
@@ -0,0 +1,718 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+/* aon_iomux */
+#define AON_GPO_DOEN_CFG		0x0
+#define AON_GPO_DOEN_MASK		GENMASK(2, 0)
+#define AON_GPO_DOUT_CFG		0x4
+#define AON_GPO_DOUT_MASK		GENMASK(3, 0)
+#define AON_GPI_DIN_CFG			0x8
+#define AON_GPI_DIN_MASK		GENMASK(3, 0)
+#define AON_GPIO_DIN_REG		0x2c
+
+/* aon_iomux GPIO CTRL */
+#define AON_GPIO_EN_REG			0xc
+#define AON_GPIO_IS_REG			0x10
+#define AON_GPIO_IC_REG			0x14
+#define AON_GPIO_IBE_REG		0x18
+#define AON_GPIO_IEV_REG		0x1c
+#define AON_GPIO_IE_REG			0x20
+#define AON_GPIO_MIS_REG		0x28
+
+/* aon_iomux PIN ioconfig reg */
+#define AON_GPO_PDA_0_5_CFG		0x30
+#define PADCFG_PAD_GMAC_SYSCON_SHIFT	0x0
+#define PADCFG_PAD_GMAC_SYSCON_MASK	GENMASK(1, 0)
+#define A0N_GPO_PDA_CFG_OFFSET		0x4
+#define AON_GPIO_INPUT_ENABLE_REG	0x34
+
+#define AON_GPIO_NUM			4
+
+enum starfive_jh7110_aon_pads {
+	PAD_TESTEN	= 0,
+	PAD_RGPIO0	= 1,
+	PAD_RGPIO1	= 2,
+	PAD_RGPIO2	= 3,
+	PAD_RGPIO3	= 4,
+	PAD_RSTN	= 5,
+	PAD_GMAC0_MDC	= 6,
+	PAD_GMAC0_MDIO	= 7,
+	PAD_GMAC0_RXD0	= 8,
+	PAD_GMAC0_RXD1	= 9,
+	PAD_GMAC0_RXD2	= 10,
+	PAD_GMAC0_RXD3	= 11,
+	PAD_GMAC0_RXDV	= 12,
+	PAD_GMAC0_RXC	= 13,
+	PAD_GMAC0_TXD0	= 14,
+	PAD_GMAC0_TXD1	= 15,
+	PAD_GMAC0_TXD2	= 16,
+	PAD_GMAC0_TXD3	= 17,
+	PAD_GMAC0_TXEN	= 18,
+	PAD_GMAC0_TXC	= 19,
+};
+
+static const struct pinctrl_pin_desc starfive_jh7110_aon_pinctrl_pads[] = {
+	STARFIVE_PINCTRL_PIN(PAD_TESTEN),
+	STARFIVE_PINCTRL_PIN(PAD_RGPIO0),
+	STARFIVE_PINCTRL_PIN(PAD_RGPIO1),
+	STARFIVE_PINCTRL_PIN(PAD_RGPIO2),
+	STARFIVE_PINCTRL_PIN(PAD_RGPIO3),
+	STARFIVE_PINCTRL_PIN(PAD_RSTN),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDC),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDIO),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD0),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD1),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD2),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD3),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXDV),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXC),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD0),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD1),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD2),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD3),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXEN),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXC),
+};
+
+static int jh7110_aon_pmx_set_one_pin_mux(struct starfive_pinctrl *pctl,
+					  struct starfive_pin *pin)
+{
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	struct starfive_pin_config *pin_config = &pin->pin_config;
+	const struct starfive_pin_reg *pin_reg;
+	unsigned int gpio, pin_id;
+	int i;
+	unsigned long flags;
+	int n, shift;
+
+	gpio = pin->pin_config.gpio_num;
+	pin_id = pin->pin;
+	pin_reg = &pctl->pin_regs[pin_id];
+
+	raw_spin_lock_irqsave(&pctl->lock, flags);
+	if (pin_reg->func_sel_reg != -1) {
+		pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
+				pin_config->pinmux_func,
+				pin_reg->func_sel_shift,
+				pin_reg->func_sel_mask);
+	}
+
+	shift = GET_GPO_CFG_SHIFT(gpio);
+	if (pin_reg->gpo_dout_reg != -1) {
+		pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
+				  AON_GPO_DOUT_MASK << shift,
+				  pin_config->gpio_dout << shift);
+	}
+
+	if (pin_reg->gpo_doen_reg != -1) {
+		pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
+				  AON_GPO_DOEN_MASK << shift,
+				  pin_config->gpio_doen << shift);
+	}
+
+	for (i = 0; i < pin_config->gpio_din_num; i++) {
+		n = pin_config->gpio_din_reg[i] >> 2;
+		shift = (pin_config->gpio_din_reg[i] & 3) << 3;
+		pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
+				  AON_GPI_DIN_MASK << shift,
+				  (gpio + 2) << shift);
+	}
+
+	if (pin_reg->syscon_reg != -1) {
+		pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
+				pin_config->syscon,
+				PADCFG_PAD_GMAC_SYSCON_SHIFT,
+				PADCFG_PAD_GMAC_SYSCON_MASK);
+	}
+
+	raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+	return 0;
+}
+
+static void jh7110_aon_parse_pin_config(struct starfive_pinctrl *pctl,
+					unsigned int *pins_id,
+					struct starfive_pin *pin_data,
+					const __be32 *list_p,
+					struct device_node *np)
+{
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	struct starfive_pin_reg *pin_reg;
+	const __be32 *list = list_p;
+	const __be32 *list_din;
+	int size;
+	int size_din;
+	int pin_size;
+	u32 value;
+	int i;
+
+	pin_size = sizeof(u32);
+	*pins_id = be32_to_cpu(*list);
+	pin_reg = &pctl->pin_regs[*pins_id];
+	pin_data->pin = *pins_id;
+
+	if (pin_data->pin > PAD_GMAC0_TXC) {
+		dev_err(pctl->dev, "err pin num = %d\n", pin_data->pin);
+		return;
+	}
+
+	if (pin_data->pin < PAD_GMAC0_MDC) {
+		pin_reg->io_conf_reg = (pin_data->pin * A0N_GPO_PDA_CFG_OFFSET) +
+					AON_GPO_PDA_0_5_CFG;
+	}
+
+	if (!of_property_read_u32(np, "starfive,pin-ioconfig", &value))
+		pin_data->pin_config.io_config = value;
+
+	list = of_get_property(np, "starfive,pinmux", &size);
+	if (list) {
+		pin_reg->func_sel_reg = be32_to_cpu(*list++);
+		pin_reg->func_sel_shift = be32_to_cpu(*list++);
+		pin_reg->func_sel_mask = be32_to_cpu(*list++);
+		pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
+	}
+
+	list = of_get_property(np, "starfive,pin-syscon", &size);
+	if (list) {
+		pin_reg->syscon_reg = be32_to_cpu(*list++);
+		pin_data->pin_config.syscon = be32_to_cpu(*list++);
+	}
+
+	if (pin_data->pin >= PAD_RGPIO0 && pin_data->pin <= PAD_RGPIO3) {
+		pin_data->pin_config.gpio_num = pin_data->pin - 1;
+		pin_reg->gpo_dout_reg = info->dout_reg_base;
+		pin_reg->gpo_doen_reg = info->doen_reg_base;
+
+		if (!of_property_read_u32(np, "starfive,pin-gpio-dout", &value))
+			pin_data->pin_config.gpio_dout = value;
+
+		if (!of_property_read_u32(np, "starfive,pin-gpio-doen", &value))
+			pin_data->pin_config.gpio_doen = value;
+
+		list_din = of_get_property(np, "starfive,pin-gpio-din", &size_din);
+		if (list_din) {
+			if (!size_din || size_din % pin_size) {
+				dev_err(pctl->dev,
+					"Invalid starfive,pin-gpio-din property in node\n");
+				return;
+			}
+			pin_data->pin_config.gpio_din_num = size_din / pin_size;
+			pin_data->pin_config.gpio_din_reg =
+				devm_kcalloc(pctl->dev,
+					     pin_data->pin_config.gpio_din_num,
+					     sizeof(s32),
+					     GFP_KERNEL);
+			for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
+				value = be32_to_cpu(*list_din++);
+				pin_data->pin_config.gpio_din_reg[i] = value;
+			}
+		}
+	}
+}
+
+static int jh7110_aon_direction_input(struct gpio_chip *gc,
+				      unsigned int gpio)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int shift;
+	void __iomem *reg_doen;
+	u32 mask;
+
+	if (gpio < 0 || gpio >= gc->ngpio)
+		return -EINVAL;
+
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask = AON_GPO_DOEN_MASK << shift;
+	reg_doen = chip->padctl_base + AON_GPO_DOEN_CFG;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	pinctrl_set_reg(reg_doen, 1, shift, mask);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+static int jh7110_aon_direction_output(struct gpio_chip *gc,
+				       unsigned int gpio,
+				       int value)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int shift;
+	void __iomem *reg_doen, *reg_dout;
+	u32 mask_doen, mask_dout;
+
+	if (gpio < 0 || gpio >= gc->ngpio)
+		return -EINVAL;
+
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask_doen = AON_GPO_DOEN_MASK << shift;
+	mask_dout = AON_GPO_DOUT_MASK << shift;
+	reg_doen = chip->padctl_base + AON_GPO_DOEN_CFG;
+	reg_dout = chip->padctl_base + AON_GPO_DOUT_CFG;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	pinctrl_set_reg(reg_doen, 0, shift, mask_doen);
+
+	pinctrl_set_reg(reg_dout, value, shift, mask_dout);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+static int jh7110_aon_get_direction(struct gpio_chip *gc,
+				    unsigned int gpio)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int doen;
+	unsigned int shift;
+	void __iomem *reg_doen;
+	u32 mask;
+
+	if (gpio < 0 || gpio >= gc->ngpio)
+		return -EINVAL;
+
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask = AON_GPO_DOEN_MASK << shift;
+	reg_doen = chip->padctl_base + AON_GPO_DOEN_CFG;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	doen = readl_relaxed(reg_doen);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+	return !!(doen & mask);
+}
+
+static int jh7110_aon_get_value(struct gpio_chip *gc,
+				unsigned int gpio)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	int value;
+
+	if (gpio < 0 || gpio >= gc->ngpio)
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	value = readl_relaxed(chip->padctl_base + AON_GPIO_DIN_REG);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+	return (value >> gpio) & 0x1;
+}
+
+static void jh7110_aon_set_value(struct gpio_chip *gc,
+				 unsigned int gpio, int value)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int shift;
+	void __iomem *reg_dout;
+	u32 mask;
+
+	if (gpio < 0 || gpio >= gc->ngpio)
+		return;
+
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask = AON_GPO_DOUT_MASK << shift;
+	reg_dout = chip->padctl_base + AON_GPO_DOUT_CFG;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	pinctrl_set_reg(reg_dout, value, shift, mask);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static void jh7110_aon_irq_handler(struct irq_desc *desc)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	unsigned long mis;
+	unsigned int pin;
+
+	chained_irq_enter(chip, desc);
+
+	mis = readl_relaxed(sfp->padctl_base + AON_GPIO_MIS_REG);
+	for_each_set_bit(pin, &mis, AON_GPIO_NUM)
+		generic_handle_domain_irq(sfp->gc.irq.domain, pin);
+
+	chained_irq_exit(chip, desc);
+}
+
+static int jh7110_aon_init_hw(struct gpio_chip *gc)
+{
+	struct starfive_pinctrl *sfp = container_of(gc,
+			struct starfive_pinctrl, gc);
+
+	/* mask all GPIO interrupts */
+	writel_relaxed(0, sfp->padctl_base + AON_GPIO_IE_REG);
+	/* clear edge interrupt flags */
+	writel_relaxed(0, sfp->padctl_base + AON_GPIO_IC_REG);
+	writel_relaxed(0x0f, sfp->padctl_base + AON_GPIO_IC_REG);
+	/* enable GPIO interrupts */
+	writel_relaxed(1, sfp->padctl_base + AON_GPIO_EN_REG);
+	return 0;
+}
+
+static int jh7110_aon_irq_set_type(struct irq_data *d,
+				   unsigned int trigger)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *base = sfp->padctl_base;
+	u32 mask = BIT(gpio);
+	u32 irq_type, edge_both, polarity;
+	unsigned long flags;
+
+	switch (trigger) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		irq_type  = 0;    /* 0: level triggered */
+		edge_both = 0;    /* 0: ignored */
+		polarity  = 0;    /* 0: high level */
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		irq_type  = 0;    /* 0: level triggered */
+		edge_both = 0;    /* 0: ignored */
+		polarity  = 1;    /* 1: low level */
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		irq_type  = mask; /* 1: edge triggered */
+		edge_both = mask; /* 1: both edges */
+		polarity  = 0;    /* 0: ignored */
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		irq_type  = mask; /* 1: edge triggered */
+		edge_both = 0;    /* 0: single edge */
+		polarity  = mask; /* 1: rising edge */
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		irq_type  = mask; /* 1: edge triggered */
+		edge_both = 0;    /* 0: single edge */
+		polarity  = 0;    /* 0: falling edge */
+		break;
+	}
+	if (trigger & IRQ_TYPE_EDGE_BOTH)
+		irq_set_handler_locked(d, handle_edge_irq);
+	else
+		irq_set_handler_locked(d, handle_level_irq);
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	irq_type |= readl_relaxed(base + AON_GPIO_IS_REG) & ~mask;
+	writel_relaxed(irq_type, base + AON_GPIO_IS_REG);
+
+	edge_both |= readl_relaxed(base + AON_GPIO_IBE_REG) & ~mask;
+	writel_relaxed(edge_both, base + AON_GPIO_IBE_REG);
+
+	polarity |= readl_relaxed(base + AON_GPIO_IEV_REG) & ~mask;
+	writel_relaxed(polarity, base + AON_GPIO_IEV_REG);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+	sfp->trigger[gpio] = trigger;
+	return 0;
+}
+
+static void jh7110_aon_irq_mask(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
+	u32 mask = BIT(gpio);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ie) & ~mask;
+	writel_relaxed(value, ie);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_aon_irq_unmask(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
+	u32 mask = BIT(gpio);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ie) | mask;
+	writel_relaxed(value, ie);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_aon_irq_ack(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ic = sfp->padctl_base + AON_GPIO_IC_REG;
+	u32 mask = BIT(gpio);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ic) & ~mask;
+	writel_relaxed(value, ic);
+	writel_relaxed(value | mask, ic);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_aon_irq_mask_ack(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ie = sfp->padctl_base + AON_GPIO_IE_REG;
+	void __iomem *ic = sfp->padctl_base + AON_GPIO_IC_REG;
+	u32 mask = BIT(gpio);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ie) & ~mask;
+	writel_relaxed(value, ie);
+
+	value = readl_relaxed(ic) & ~mask;
+	writel_relaxed(value, ic);
+	writel_relaxed(value | mask, ic);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static struct irq_chip jh7110_aon_irqchip = {
+	.name		= "starfive-jh7110-aon-gpio",
+	.irq_ack	= jh7110_aon_irq_ack,
+	.irq_mask_ack	= jh7110_aon_irq_mask_ack,
+	.irq_set_type	= jh7110_aon_irq_set_type,
+	.irq_mask	= jh7110_aon_irq_mask,
+	.irq_unmask	= jh7110_aon_irq_unmask,
+	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static int jh7110_aon_add_pin_ranges(struct gpio_chip *gc)
+{
+	struct starfive_pinctrl *sfp = container_of(gc,
+			struct starfive_pinctrl, gc);
+
+	sfp->gpios.name = sfp->gc.label;
+	sfp->gpios.base = sfp->gc.base;
+	/*
+	 * sfp->gpios.pin_base depends on the chosen signal group
+	 * and is set in starfive_probe()
+	 */
+	sfp->gpios.npins = AON_GPIO_NUM;
+	sfp->gpios.gc = &sfp->gc;
+	pinctrl_add_gpio_range(sfp->pctl_dev, &sfp->gpios);
+	return 0;
+}
+
+static int jh7110_aon_gpio_register(struct platform_device *pdev,
+				    struct starfive_pinctrl *pctl)
+{
+	struct device *dev = &pdev->dev;
+	int ret, ngpio;
+	int loop;
+
+	ngpio = AON_GPIO_NUM;
+
+	pctl->gc.direction_input = jh7110_aon_direction_input;
+	pctl->gc.direction_output = jh7110_aon_direction_output;
+	pctl->gc.get_direction = jh7110_aon_get_direction;
+	pctl->gc.get = jh7110_aon_get_value;
+	pctl->gc.set = jh7110_aon_set_value;
+	pctl->gc.add_pin_ranges = jh7110_aon_add_pin_ranges;
+	pctl->gc.base = MAX_GPIO;
+	pctl->gc.ngpio = ngpio;
+	pctl->gc.label = dev_name(dev);
+	pctl->gc.parent = dev;
+	pctl->gc.owner = THIS_MODULE;
+
+	pctl->enabled = 0;
+
+	platform_set_drvdata(pdev, pctl);
+
+	jh7110_aon_irqchip.name = pctl->gc.label;
+
+	pctl->gc.irq.chip = &jh7110_aon_irqchip;
+	pctl->gc.irq.parent_handler = jh7110_aon_irq_handler;
+	pctl->gc.irq.num_parents = 1;
+	pctl->gc.irq.parents =
+		devm_kcalloc(dev, pctl->gc.irq.num_parents,
+			     sizeof(*pctl->gc.irq.parents), GFP_KERNEL);
+	if (!pctl->gc.irq.parents)
+		return -ENOMEM;
+	pctl->gc.irq.default_type = IRQ_TYPE_NONE;
+	pctl->gc.irq.handler = handle_bad_irq;
+	pctl->gc.irq.init_hw = jh7110_aon_init_hw;
+
+	ret = platform_get_irq(pdev, 0);
+	if (ret < 0)
+		return ret;
+	pctl->gc.irq.parents[0] = ret;
+
+	ret = devm_gpiochip_add_data(dev, &pctl->gc, pctl);
+	if (ret)
+		return dev_err_probe(dev, ret, "could not register gpiochip\n");
+
+	for (loop = 0; loop < ngpio; loop++) {
+		unsigned int v;
+		void __iomem *ie_reg = pctl->padctl_base +
+				AON_GPIO_INPUT_ENABLE_REG + (loop << 2);
+
+		v = readl_relaxed(ie_reg);
+		v |= 0x1;
+		writel_relaxed(v, ie_reg);
+	}
+
+	dev_info(dev, "StarFive AON GPIO chip registered %d GPIOs\n", ngpio);
+
+	return 0;
+}
+
+static int jh7110_aon_pinconf_get(struct pinctrl_dev *pctldev,
+				  unsigned int pin_id,
+				  unsigned long *config)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+	unsigned long flags;
+	u32 value;
+
+	if (pin_reg->io_conf_reg == -1) {
+		dev_err(pctl->dev,
+			"Pin(%s) does not support config function\n",
+			info->pins[pin_id].name);
+		return -EINVAL;
+	}
+
+	raw_spin_lock_irqsave(&pctl->lock, flags);
+	value = readl_relaxed(pctl->padctl_base + pin_reg->io_conf_reg);
+	*config = value & 0xff;
+	raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+	return 0;
+}
+
+static int jh7110_aon_pinconf_set(struct pinctrl_dev *pctldev,
+				  unsigned int pin_id,
+				  unsigned long *configs,
+				  unsigned int num_configs)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+	int i;
+	u32 value;
+	unsigned long flags;
+
+	if (pin_reg->io_conf_reg == -1) {
+		dev_err(pctl->dev,
+			"Pin(%s) does not support config function\n",
+			info->pins[pin_id].name);
+		return -EINVAL;
+	}
+
+	raw_spin_lock_irqsave(&pctl->lock, flags);
+	for (i = 0; i < num_configs; i++) {
+		value = readl_relaxed(pctl->padctl_base +
+				      pin_reg->io_conf_reg);
+		value = value | (configs[i] & 0xFF);
+		writel_relaxed(value, pctl->padctl_base +
+				pin_reg->io_conf_reg);
+	}
+	raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+	return 0;
+}
+
+static const struct starfive_pinctrl_soc_info jh7110_aon_pinctrl_info = {
+	.pins = starfive_jh7110_aon_pinctrl_pads,
+	.npins = ARRAY_SIZE(starfive_jh7110_aon_pinctrl_pads),
+	.flags = 1,
+	.dout_reg_base = AON_GPO_DOUT_CFG,
+	.doen_reg_base = AON_GPO_DOEN_CFG,
+	.din_reg_base = AON_GPI_DIN_CFG,
+	.starfive_pinconf_get = jh7110_aon_pinconf_get,
+	.starfive_pinconf_set = jh7110_aon_pinconf_set,
+	.starfive_pmx_set_one_pin_mux = jh7110_aon_pmx_set_one_pin_mux,
+	.starfive_gpio_register = jh7110_aon_gpio_register,
+	.starfive_pinctrl_parse_pin = jh7110_aon_parse_pin_config,
+};
+
+static const struct of_device_id jh7110_aon_pinctrl_of_match[] = {
+	{
+		.compatible = "starfive,jh7110-aon-pinctrl",
+		.data = &jh7110_aon_pinctrl_info,
+	},
+	{ /* sentinel */ }
+};
+
+static int jh7110_aon_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct starfive_pinctrl_soc_info *pinctrl_info;
+
+	pinctrl_info = of_device_get_match_data(&pdev->dev);
+	if (!pinctrl_info)
+		return -ENODEV;
+
+	return starfive_pinctrl_probe(pdev, pinctrl_info);
+}
+
+static struct platform_driver jh7110_aon_pinctrl_driver = {
+	.driver = {
+		.name = "starfive-jh7110-aon-pinctrl",
+		.of_match_table = of_match_ptr(jh7110_aon_pinctrl_of_match),
+	},
+	.probe = jh7110_aon_pinctrl_probe,
+};
+
+static int __init jh7110_aon_pinctrl_init(void)
+{
+	return platform_driver_register(&jh7110_aon_pinctrl_driver);
+}
+arch_initcall(jh7110_aon_pinctrl_init);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC aon controller");
+MODULE_AUTHOR("Jenny Zhang <jenny.zhang@starfivetech.com>");
+MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
new file mode 100644
index 000000000000..882d45c63497
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
@@ -0,0 +1,925 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+#define SYS_GPO_DOEN_CFG		0x0
+#define SYS_GPO_DOEN_MASK		GENMASK(5, 0)
+#define SYS_GPO_DOUT_CFG		0x40
+#define SYS_GPO_DOUT_MASK		GENMASK(6, 0)
+#define SYS_GPI_DIN_CFG			0x80
+#define SYS_GPI_DIN_MASK		GENMASK(6, 0)
+#define SYS_GPIO_INPUT_ENABLE_REG	0x120
+
+/* sys_iomux PIN 0-74 ioconfig reg */
+#define SYS_GPO_PDA_0_74_CFG		0x120
+/* sys_iomux PIN 89-94 ioconfig reg */
+#define SYS_GPO_PDA_89_94_CFG		0x284
+#define SYS_GPO_PDA_CFG_OFFSET		0x4
+
+/* sys_iomux GPIO CTRL */
+#define GPIO_EN				0xdc
+#define GPIO_IS_LOW			0xe0
+#define GPIO_IS_HIGH			0xe4
+#define GPIO_IC_LOW			0xe8
+#define GPIO_IC_HIGH			0xec
+#define GPIO_IBE_LOW			0xf0
+#define GPIO_IBE_HIGH			0xf4
+#define GPIO_IEV_LOW			0xf8
+#define GPIO_IEV_HIGH			0xfc
+#define GPIO_IE_LOW			0x100
+#define GPIO_IE_HIGH			0x104
+
+/* read only */
+#define GPIO_MIS_LOW			0x110
+#define GPIO_MIS_HIGH			0x114
+#define GPIO_DIN_LOW			0x118
+#define GPIO_DIN_HIGH			0x11c
+
+#define PADCFG_PAD_GMAC_SYSCON_SHIFT	0x0
+#define PADCFG_PAD_GMAC_SYSCON_MASK	GENMASK(1, 0)
+
+/* one dword include 4 gpios */
+#define GPIO_NUM_SHIFT			2
+#define GPIO_NUM_PER_REG		32
+#define OFFSET_PER_REG			4
+#define SYS_GPIO_NUM			64
+
+enum starfive_jh7110_sys_pads {
+	PAD_GPIO0	= 0,
+	PAD_GPIO1	= 1,
+	PAD_GPIO2	= 2,
+	PAD_GPIO3	= 3,
+	PAD_GPIO4	= 4,
+	PAD_GPIO5	= 5,
+	PAD_GPIO6	= 6,
+	PAD_GPIO7	= 7,
+	PAD_GPIO8	= 8,
+	PAD_GPIO9	= 9,
+	PAD_GPIO10	= 10,
+	PAD_GPIO11	= 11,
+	PAD_GPIO12	= 12,
+	PAD_GPIO13	= 13,
+	PAD_GPIO14	= 14,
+	PAD_GPIO15	= 15,
+	PAD_GPIO16	= 16,
+	PAD_GPIO17	= 17,
+	PAD_GPIO18	= 18,
+	PAD_GPIO19	= 19,
+	PAD_GPIO20	= 20,
+	PAD_GPIO21	= 21,
+	PAD_GPIO22	= 22,
+	PAD_GPIO23	= 23,
+	PAD_GPIO24	= 24,
+	PAD_GPIO25	= 25,
+	PAD_GPIO26	= 26,
+	PAD_GPIO27	= 27,
+	PAD_GPIO28	= 28,
+	PAD_GPIO29	= 29,
+	PAD_GPIO30	= 30,
+	PAD_GPIO31	= 31,
+	PAD_GPIO32	= 32,
+	PAD_GPIO33	= 33,
+	PAD_GPIO34	= 34,
+	PAD_GPIO35	= 35,
+	PAD_GPIO36	= 36,
+	PAD_GPIO37	= 37,
+	PAD_GPIO38	= 38,
+	PAD_GPIO39	= 39,
+	PAD_GPIO40	= 40,
+	PAD_GPIO41	= 41,
+	PAD_GPIO42	= 42,
+	PAD_GPIO43	= 43,
+	PAD_GPIO44	= 44,
+	PAD_GPIO45	= 45,
+	PAD_GPIO46	= 46,
+	PAD_GPIO47	= 47,
+	PAD_GPIO48	= 48,
+	PAD_GPIO49	= 49,
+	PAD_GPIO50	= 50,
+	PAD_GPIO51	= 51,
+	PAD_GPIO52	= 52,
+	PAD_GPIO53	= 53,
+	PAD_GPIO54	= 54,
+	PAD_GPIO55	= 55,
+	PAD_GPIO56	= 56,
+	PAD_GPIO57	= 57,
+	PAD_GPIO58	= 58,
+	PAD_GPIO59	= 59,
+	PAD_GPIO60	= 60,
+	PAD_GPIO61	= 61,
+	PAD_GPIO62	= 62,
+	PAD_GPIO63	= 63,
+	PAD_SD0_CLK	= 64,
+	PAD_SD0_CMD	= 65,
+	PAD_SD0_DATA0	= 66,
+	PAD_SD0_DATA1	= 67,
+	PAD_SD0_DATA2	= 68,
+	PAD_SD0_DATA3	= 69,
+	PAD_SD0_DATA4	= 70,
+	PAD_SD0_DATA5	= 71,
+	PAD_SD0_DATA6	= 72,
+	PAD_SD0_DATA7	= 73,
+	PAD_SD0_STRB	= 74,
+	PAD_GMAC1_MDC	= 75,
+	PAD_GMAC1_MDIO	= 76,
+	PAD_GMAC1_RXD0	= 77,
+	PAD_GMAC1_RXD1	= 78,
+	PAD_GMAC1_RXD2	= 79,
+	PAD_GMAC1_RXD3	= 80,
+	PAD_GMAC1_RXDV	= 81,
+	PAD_GMAC1_RXC	= 82,
+	PAD_GMAC1_TXD0	= 83,
+	PAD_GMAC1_TXD1	= 84,
+	PAD_GMAC1_TXD2	= 85,
+	PAD_GMAC1_TXD3	= 86,
+	PAD_GMAC1_TXEN	= 87,
+	PAD_GMAC1_TXC	= 88,
+	PAD_QSPI_SCLK	= 89,
+	PAD_QSPI_CSn0	= 90,
+	PAD_QSPI_DATA0	= 91,
+	PAD_QSPI_DATA1	= 92,
+	PAD_QSPI_DATA2	= 93,
+	PAD_QSPI_DATA3	= 94,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc starfive_jh7110_sys_pinctrl_pads[] = {
+	STARFIVE_PINCTRL_PIN(PAD_GPIO0),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO1),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO2),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO3),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO4),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO5),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO6),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO7),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO8),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO9),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO10),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO11),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO12),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO13),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO14),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO15),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO16),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO17),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO18),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO19),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO20),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO21),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO22),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO23),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO24),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO25),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO26),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO27),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO28),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO29),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO30),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO31),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO32),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO33),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO34),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO35),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO36),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO37),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO38),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO39),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO40),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO41),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO42),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO43),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO44),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO45),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO46),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO47),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO48),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO49),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO50),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO51),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO52),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO53),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO54),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO55),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO56),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO57),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO58),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO59),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO60),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO61),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO62),
+	STARFIVE_PINCTRL_PIN(PAD_GPIO63),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_CLK),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_CMD),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA0),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA1),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA2),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA3),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA4),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA5),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA6),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_DATA7),
+	STARFIVE_PINCTRL_PIN(PAD_SD0_STRB),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDC),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDIO),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD0),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD1),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD2),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD3),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXDV),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXC),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD0),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD1),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD2),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD3),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXEN),
+	STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXC),
+	STARFIVE_PINCTRL_PIN(PAD_QSPI_SCLK),
+	STARFIVE_PINCTRL_PIN(PAD_QSPI_CSn0),
+	STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA0),
+	STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA1),
+	STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA2),
+	STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA3),
+};
+
+static int jh7110_sys_direction_input(struct gpio_chip *gc,
+				      unsigned int gpio)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int offset, shift;
+	void __iomem *reg_doen;
+	u32 mask;
+
+	if (gpio >= gc->ngpio)
+		return -EINVAL;
+
+	offset = GET_GPO_REG_OFFSET(gpio);
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask = SYS_GPO_DOEN_MASK << shift;
+	reg_doen = chip->padctl_base + SYS_GPO_DOEN_CFG + offset;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	pinctrl_set_reg(reg_doen, 1, shift, mask);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+static int jh7110_sys_direction_output(struct gpio_chip *gc,
+				       unsigned int gpio,
+				       int value)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int offset, shift;
+	void __iomem *reg_doen, *reg_dout;
+	u32 mask_doen, mask_dout;
+
+	if (gpio >= gc->ngpio)
+		return -EINVAL;
+
+	offset = GET_GPO_REG_OFFSET(gpio);
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask_doen = SYS_GPO_DOEN_MASK << shift;
+	mask_dout = SYS_GPO_DOUT_MASK << shift;
+	reg_doen = chip->padctl_base + SYS_GPO_DOEN_CFG + offset;
+	reg_dout = chip->padctl_base + SYS_GPO_DOUT_CFG + offset;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	pinctrl_set_reg(reg_doen, 0, shift, mask_doen);
+
+	pinctrl_set_reg(reg_dout, value, shift, mask_dout);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+	return 0;
+}
+
+static int jh7110_sys_get_direction(struct gpio_chip *gc,
+				    unsigned int gpio)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int doen;
+	unsigned int offset, shift;
+	void __iomem *reg_doen;
+	u32 mask;
+
+	if (gpio >= gc->ngpio)
+		return -EINVAL;
+
+	offset = GET_GPO_REG_OFFSET(gpio);
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask = SYS_GPO_DOEN_MASK << shift;
+	reg_doen = chip->padctl_base + SYS_GPO_DOEN_CFG + offset;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	doen = readl_relaxed(reg_doen);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+	return !!(doen & mask);
+}
+
+static int jh7110_sys_get_value(struct gpio_chip *gc,
+				unsigned int gpio)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	int value;
+	int tmp;
+
+	if (gpio >= gc->ngpio)
+		return -EINVAL;
+
+	if (gpio < GPIO_NUM_PER_REG) {
+		value = readl_relaxed(chip->padctl_base + GPIO_DIN_LOW);
+		tmp = 0;
+	} else {
+		value = readl_relaxed(chip->padctl_base + GPIO_DIN_HIGH);
+		tmp = GPIO_NUM_PER_REG;
+	}
+	return (value >> (gpio - tmp)) & 0x1;
+}
+
+static void jh7110_sys_set_value(struct gpio_chip *gc,
+				 unsigned int gpio,
+				 int value)
+{
+	struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+	unsigned long flags;
+	unsigned int offset, shift;
+	void __iomem *reg_dout;
+	u32 mask;
+
+	if (gpio >= gc->ngpio)
+		return;
+
+	offset = GET_GPO_REG_OFFSET(gpio);
+	shift  = GET_GPO_CFG_SHIFT(gpio);
+	mask = SYS_GPO_DOUT_MASK << shift;
+	reg_dout = chip->padctl_base + SYS_GPO_DOUT_CFG + offset;
+
+	raw_spin_lock_irqsave(&chip->lock, flags);
+	pinctrl_set_reg(reg_dout, value, shift, mask);
+	raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static int jh7110_sys_irq_set_type(struct irq_data *d,
+				   unsigned int trigger)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *base = sfp->padctl_base +
+			OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+	u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+	u32 irq_type, edge_both, polarity;
+	unsigned long flags;
+
+	switch (trigger) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		irq_type  = 0;    /* 0: level triggered */
+		edge_both = 0;    /* 0: ignored */
+		polarity  = 0;    /* 0: high level */
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		irq_type  = 0;    /* 0: level triggered */
+		edge_both = 0;    /* 0: ignored */
+		polarity  = 1;    /* 1: low level */
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		irq_type  = mask; /* 1: edge triggered */
+		edge_both = mask; /* 1: both edges */
+		polarity  = 0;    /* 0: ignored */
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		irq_type  = mask; /* 1: edge triggered */
+		edge_both = 0;    /* 0: single edge */
+		polarity  = mask; /* 1: rising edge */
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		irq_type  = mask; /* 1: edge triggered */
+		edge_both = 0;    /* 0: single edge */
+		polarity  = 0;    /* 0: falling edge */
+		break;
+	}
+	if (trigger & IRQ_TYPE_EDGE_BOTH)
+		irq_set_handler_locked(d, handle_edge_irq);
+	else
+		irq_set_handler_locked(d, handle_level_irq);
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	irq_type |= readl_relaxed(base + GPIO_IS_LOW) & ~mask;
+	writel_relaxed(irq_type, base + GPIO_IS_LOW);
+
+	edge_both |= readl_relaxed(base + GPIO_IBE_LOW) & ~mask;
+	writel_relaxed(edge_both, base + GPIO_IBE_LOW);
+
+	polarity |= readl_relaxed(base + GPIO_IEV_LOW) & ~mask;
+	writel_relaxed(polarity, base + GPIO_IEV_LOW);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+	sfp->trigger[gpio] = trigger;
+	return 0;
+}
+
+/* chained_irq_{enter,exit} already mask the parent */
+static void jh7110_sys_irq_mask(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
+			OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+	u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ie) & ~mask;
+	writel_relaxed(value, ie);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_sys_irq_unmask(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
+			OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+	u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ie) | mask;
+	writel_relaxed(value, ie);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_sys_irq_ack(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ic = sfp->padctl_base + GPIO_IC_LOW +
+			OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+	u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ic) & ~mask;
+	writel_relaxed(value, ic);
+	writel_relaxed(value | mask, ic);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jh7110_sys_irq_mask_ack(struct irq_data *d)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
+	irq_hw_number_t gpio = irqd_to_hwirq(d);
+	void __iomem *ie = sfp->padctl_base + GPIO_IE_LOW +
+			OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+	void __iomem *ic = sfp->padctl_base + GPIO_IC_LOW +
+			OFFSET_PER_REG * (gpio / GPIO_NUM_PER_REG);
+	u32 mask = BIT(gpio % GPIO_NUM_PER_REG);
+	unsigned long flags;
+	u32 value;
+
+	if (gpio < 0 || gpio >= sfp->gc.ngpio)
+		return;
+
+	raw_spin_lock_irqsave(&sfp->lock, flags);
+	value = readl_relaxed(ie) & ~mask;
+	writel_relaxed(value, ie);
+
+	value = readl_relaxed(ic) & ~mask;
+	writel_relaxed(value, ic);
+	writel_relaxed(value | mask, ic);
+	raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static struct irq_chip jh7110_sys_irqchip = {
+	.name		= "starfive-jh7110-sys-gpio",
+	.irq_ack	= jh7110_sys_irq_ack,
+	.irq_mask_ack	= jh7110_sys_irq_mask_ack,
+	.irq_set_type	= jh7110_sys_irq_set_type,
+	.irq_mask	= jh7110_sys_irq_mask,
+	.irq_unmask	= jh7110_sys_irq_unmask,
+	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void jh7110_sys_irq_handler(struct irq_desc *desc)
+{
+	struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	unsigned long mis;
+	unsigned int pin;
+
+	chained_irq_enter(chip, desc);
+
+	mis = readl_relaxed(sfp->padctl_base + GPIO_MIS_LOW);
+	for_each_set_bit(pin, &mis, GPIO_NUM_PER_REG)
+		generic_handle_domain_irq(sfp->gc.irq.domain, pin);
+
+	mis = readl_relaxed(sfp->padctl_base + GPIO_MIS_HIGH);
+	for_each_set_bit(pin, &mis, GPIO_NUM_PER_REG)
+		generic_handle_domain_irq(sfp->gc.irq.domain,
+					  pin + GPIO_NUM_PER_REG);
+
+	chained_irq_exit(chip, desc);
+}
+
+static int jh7110_sys_init_hw(struct gpio_chip *gc)
+{
+	struct starfive_pinctrl *sfp = container_of(gc,
+			struct starfive_pinctrl, gc);
+
+	/* mask all GPIO interrupts */
+	writel_relaxed(0, sfp->padctl_base + GPIO_IE_LOW);
+	writel_relaxed(0, sfp->padctl_base + GPIO_IE_HIGH);
+	/* clear edge interrupt flags */
+	writel_relaxed(0, sfp->padctl_base + GPIO_IC_LOW);
+	writel_relaxed(0, sfp->padctl_base + GPIO_IC_HIGH);
+	writel_relaxed(~0U, sfp->padctl_base + GPIO_IC_LOW);
+	writel_relaxed(~0U, sfp->padctl_base + GPIO_IC_HIGH);
+	/* enable GPIO interrupts */
+	writel_relaxed(1, sfp->padctl_base + GPIO_EN);
+	return 0;
+}
+
+static int jh7110_sys_add_pin_ranges(struct gpio_chip *gc)
+{
+	struct starfive_pinctrl *sfp = container_of(gc,
+			struct starfive_pinctrl, gc);
+
+	sfp->gpios.name = sfp->gc.label;
+	sfp->gpios.base = sfp->gc.base;
+	/*
+	 * sfp->gpios.pin_base depends on the chosen signal group
+	 * and is set in starfive_probe()
+	 */
+	sfp->gpios.npins = SYS_GPIO_NUM;
+	sfp->gpios.gc = &sfp->gc;
+	pinctrl_add_gpio_range(sfp->pctl_dev, &sfp->gpios);
+	return 0;
+}
+
+static int jh7110_sys_gpio_register(struct platform_device *pdev,
+				    struct starfive_pinctrl *pctl)
+{
+	struct device *dev = &pdev->dev;
+	int ret, ngpio;
+	int loop;
+
+	ngpio = SYS_GPIO_NUM;
+
+	pctl->gc.direction_input = jh7110_sys_direction_input;
+	pctl->gc.direction_output = jh7110_sys_direction_output;
+	pctl->gc.get_direction = jh7110_sys_get_direction;
+	pctl->gc.get = jh7110_sys_get_value;
+	pctl->gc.set = jh7110_sys_set_value;
+	pctl->gc.add_pin_ranges = jh7110_sys_add_pin_ranges;
+	pctl->gc.base = 0;
+	pctl->gc.ngpio = ngpio;
+	pctl->gc.label = dev_name(dev);
+	pctl->gc.parent = dev;
+	pctl->gc.owner = THIS_MODULE;
+	pctl->enabled = 0;
+
+	platform_set_drvdata(pdev, pctl);
+
+	jh7110_sys_irqchip.name = pctl->gc.label;
+
+	pctl->gc.irq.chip = &jh7110_sys_irqchip;
+	pctl->gc.irq.parent_handler = jh7110_sys_irq_handler;
+	pctl->gc.irq.num_parents = 1;
+	pctl->gc.irq.parents = devm_kcalloc(dev, pctl->gc.irq.num_parents,
+					    sizeof(*pctl->gc.irq.parents),
+					    GFP_KERNEL);
+	if (!pctl->gc.irq.parents)
+		return -ENOMEM;
+	pctl->gc.irq.default_type = IRQ_TYPE_NONE;
+	pctl->gc.irq.handler = handle_bad_irq;
+	pctl->gc.irq.init_hw = jh7110_sys_init_hw;
+
+	if (IS_ENABLED(CONFIG_PM))
+		pm_runtime_enable(dev);
+
+	ret = platform_get_irq(pdev, 0);
+	if (ret < 0)
+		return ret;
+	pctl->gc.irq.parents[0] = ret;
+
+	ret = devm_gpiochip_add_data(dev, &pctl->gc, pctl);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				"could not register gpiochip\n");
+
+	for (loop = 0; loop < SYS_GPIO_NUM; loop++) {
+		unsigned int v;
+		void __iomem *reg_ie = pctl->padctl_base +
+			SYS_GPIO_INPUT_ENABLE_REG + (loop << 2);
+
+		v = readl_relaxed(reg_ie);
+		v |= 0x1;
+		writel_relaxed(v, reg_ie);
+	}
+
+	dev_info(dev, "StarFive SYS GPIO chip registered %d GPIOs\n", ngpio);
+
+	return 0;
+}
+
+static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,
+			      unsigned int pin_id,
+			      unsigned long *config)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+	u32 value;
+
+	if (pin_reg->io_conf_reg == -1) {
+		dev_err(pctl->dev,
+			"Pin(%s) does not support config function\n",
+			info->pins[pin_id].name);
+		return -EINVAL;
+	}
+
+	value = readl_relaxed(pctl->padctl_base + pin_reg->io_conf_reg);
+	*config = value & 0xff;
+	return 0;
+}
+
+static int jh7110_pinconf_set(struct pinctrl_dev *pctldev,
+			      unsigned int pin_id,
+			      unsigned long *configs,
+			      unsigned int num_configs)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	const struct starfive_pin_reg *pin_reg = &pctl->pin_regs[pin_id];
+	int i;
+	u32 value;
+	unsigned long flags;
+
+	if (pin_reg->io_conf_reg == -1) {
+		dev_err(pctl->dev,
+			"Pin(%s) does not support config function\n",
+			info->pins[pin_id].name);
+		return -EINVAL;
+	}
+
+	raw_spin_lock_irqsave(&pctl->lock, flags);
+	for (i = 0; i < num_configs; i++) {
+		value = readl_relaxed(pctl->padctl_base +
+				pin_reg->io_conf_reg);
+		value = value | (configs[i] & 0xFF);
+		writel_relaxed(value, pctl->padctl_base +
+				pin_reg->io_conf_reg);
+	}
+	raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+	return 0;
+}
+
+static int jh7110_sys_pmx_set_one_pin_mux(struct starfive_pinctrl *pctl,
+					  struct starfive_pin *pin)
+{
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	struct starfive_pin_config *pin_config = &pin->pin_config;
+	const struct starfive_pin_reg *pin_reg;
+	unsigned int gpio, pin_id;
+	int i;
+	unsigned long flags;
+	int n, shift;
+
+	gpio = pin->pin_config.gpio_num;
+	pin_id = pin->pin;
+	pin_reg = &pctl->pin_regs[pin_id];
+
+	raw_spin_lock_irqsave(&pctl->lock, flags);
+	if (pin_reg->func_sel_reg != -1) {
+		pinctrl_set_reg(pctl->padctl_base + pin_reg->func_sel_reg,
+				pin_config->pinmux_func,
+				pin_reg->func_sel_shift,
+				pin_reg->func_sel_mask);
+	}
+
+	shift = GET_GPO_CFG_SHIFT(gpio);
+	if (pin_reg->gpo_dout_reg != -1) {
+		pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_dout_reg,
+				  SYS_GPO_DOUT_MASK << shift, pin_config->gpio_dout << shift);
+	}
+
+	if (pin_reg->gpo_doen_reg != -1) {
+		pinctrl_write_reg(pctl->padctl_base + pin_reg->gpo_doen_reg,
+				  SYS_GPO_DOEN_MASK << shift, pin_config->gpio_doen << shift);
+	}
+
+	for (i = 0; i < pin_config->gpio_din_num; i++) {
+		n = pin_config->gpio_din_reg[i] >> 2;
+		shift = (pin_config->gpio_din_reg[i] & 3) << 3;
+		pinctrl_write_reg(pctl->padctl_base + info->din_reg_base + n * 4,
+				  SYS_GPI_DIN_MASK << shift, (gpio + 2) << shift);
+	}
+
+	if (pin_reg->syscon_reg != -1) {
+		pinctrl_set_reg(pctl->padctl_base + pin_reg->syscon_reg,
+				pin_config->syscon, PADCFG_PAD_GMAC_SYSCON_SHIFT,
+				PADCFG_PAD_GMAC_SYSCON_MASK);
+	}
+
+	if (pin_reg->pad_sel_reg != -1) {
+		pinctrl_set_reg(pctl->padctl_base + pin_reg->pad_sel_reg,
+				pin_config->padmux_func,
+				pin_reg->pad_sel_shift,
+				pin_reg->pad_sel_mask);
+	}
+	raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+	return 0;
+}
+
+static void jh7110_sys_parse_pin_config(struct starfive_pinctrl *pctl,
+					unsigned int *pins_id,
+					struct starfive_pin *pin_data,
+					const __be32 *list_p,
+					struct device_node *np)
+{
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	struct starfive_pin_reg *pin_reg;
+	const __be32 *list = list_p;
+	const __be32 *list_din;
+	int size;
+	int size_din;
+	int pin_size;
+	u32 value;
+	int i;
+	int n;
+
+	pin_size = sizeof(u32);
+	*pins_id = be32_to_cpu(*list);
+	pin_reg = &pctl->pin_regs[*pins_id];
+	pin_data->pin = *pins_id;
+
+	if (pin_data->pin > PAD_QSPI_DATA3) {
+		dev_err(pctl->dev, "err pin num = %d\n", pin_data->pin);
+		return;
+	}
+
+	if (pin_data->pin < PAD_GMAC1_MDC) {
+		pin_reg->io_conf_reg = (pin_data->pin * SYS_GPO_PDA_CFG_OFFSET)
+			+ SYS_GPO_PDA_0_74_CFG;
+	} else if (pin_data->pin > PAD_GMAC1_TXC) {
+		pin_reg->io_conf_reg = (pin_data->pin * SYS_GPO_PDA_CFG_OFFSET)
+			+ SYS_GPO_PDA_89_94_CFG;
+	}
+
+	if (!of_property_read_u32(np, "starfive,pin-ioconfig", &value))
+		pin_data->pin_config.io_config = value;
+
+	list = of_get_property(np, "starfive,pinmux", &size);
+	if (list) {
+		pin_reg->func_sel_reg = be32_to_cpu(*list++);
+		pin_reg->func_sel_shift = be32_to_cpu(*list++);
+		pin_reg->func_sel_mask = be32_to_cpu(*list++);
+		pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
+	}
+
+	list = of_get_property(np, "starfive,padmux", &size);
+	if (list) {
+		pin_reg->pad_sel_reg = be32_to_cpu(*list++);
+		pin_reg->pad_sel_shift = be32_to_cpu(*list++);
+		pin_reg->pad_sel_mask = be32_to_cpu(*list++);
+		pin_data->pin_config.padmux_func = be32_to_cpu(*list++);
+	}
+
+	list = of_get_property(np, "starfive,pin-syscon", &size);
+	if (list) {
+		pin_reg->syscon_reg = be32_to_cpu(*list++);
+		pin_data->pin_config.syscon = be32_to_cpu(*list++);
+	}
+
+	if (pin_data->pin < PAD_SD0_CLK) {
+		pin_data->pin_config.gpio_num = pin_data->pin;
+		n = pin_data->pin_config.gpio_num >> GPIO_NUM_SHIFT;
+
+		if (!of_property_read_u32(np, "starfive,pin-gpio-dout", &value)) {
+			pin_data->pin_config.gpio_dout = value;
+			pin_reg->gpo_dout_reg = info->dout_reg_base + n * 4;
+		}
+
+		if (!of_property_read_u32(np, "starfive,pin-gpio-doen", &value)) {
+			pin_data->pin_config.gpio_doen = value;
+			pin_reg->gpo_doen_reg = info->doen_reg_base + n * 4;
+		}
+
+		list_din = of_get_property(np, "starfive,pin-gpio-din", &size_din);
+		if (list_din) {
+			if (!size_din || size_din % pin_size) {
+				dev_err(pctl->dev,
+					"Invalid starfive,pin-gpio-din property in node\n");
+				return;
+			}
+
+			pin_data->pin_config.gpio_din_num = size_din / pin_size;
+			pin_data->pin_config.gpio_din_reg =
+				devm_kcalloc(pctl->dev,
+					     pin_data->pin_config.gpio_din_num,
+					     sizeof(s32),
+					     GFP_KERNEL);
+
+			for (i = 0; i < pin_data->pin_config.gpio_din_num; i++) {
+				value = be32_to_cpu(*list_din++);
+				pin_data->pin_config.gpio_din_reg[i] = value;
+			}
+		}
+	}
+}
+
+static const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = {
+	.pins = starfive_jh7110_sys_pinctrl_pads,
+	.npins = ARRAY_SIZE(starfive_jh7110_sys_pinctrl_pads),
+	.flags = 1,
+	.dout_reg_base = SYS_GPO_DOUT_CFG,
+	.doen_reg_base = SYS_GPO_DOEN_CFG,
+	.din_reg_base = SYS_GPI_DIN_CFG,
+	.starfive_pinconf_get = jh7110_pinconf_get,
+	.starfive_pinconf_set = jh7110_pinconf_set,
+	.starfive_pmx_set_one_pin_mux = jh7110_sys_pmx_set_one_pin_mux,
+	.starfive_gpio_register = jh7110_sys_gpio_register,
+	.starfive_pinctrl_parse_pin = jh7110_sys_parse_pin_config,
+};
+
+static const struct of_device_id jh7110_sys_pinctrl_of_match[] = {
+	{
+		.compatible = "starfive,jh7110-sys-pinctrl",
+		.data = &jh7110_sys_pinctrl_info,
+	},
+	{ /* sentinel */ }
+};
+
+static int jh7110_sys_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct starfive_pinctrl_soc_info *pinctrl_info;
+
+	pinctrl_info = of_device_get_match_data(&pdev->dev);
+	if (!pinctrl_info)
+		return -ENODEV;
+
+	return starfive_pinctrl_probe(pdev, pinctrl_info);
+}
+
+static struct platform_driver jh7110_sys_pinctrl_driver = {
+	.driver = {
+		.name = "starfive-jh7110-sys-pinctrl",
+		.of_match_table = of_match_ptr(jh7110_sys_pinctrl_of_match),
+	},
+	.probe = jh7110_sys_pinctrl_probe,
+};
+
+static int __init jh7110_sys_pinctrl_init(void)
+{
+	return platform_driver_register(&jh7110_sys_pinctrl_driver);
+}
+arch_initcall(jh7110_sys_pinctrl_init);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC sys controller");
+MODULE_AUTHOR("Jenny Zhang <jenny.zhang@starfivetech.com>");
+MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c
new file mode 100644
index 000000000000..80cf74ebc0e2
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.c
@@ -0,0 +1,539 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+static inline const struct group_desc *
+starfive_pinctrl_find_group_by_name(struct pinctrl_dev *pctldev,
+				    const char *name)
+{
+	const struct group_desc *grp = NULL;
+	int i;
+
+	for (i = 0; i < pctldev->num_groups; i++) {
+		grp = pinctrl_generic_get_group(pctldev, i);
+		if (grp && !strcmp(grp->name, name))
+			break;
+	}
+
+	return grp;
+}
+
+static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
+				  struct seq_file *s,
+				  unsigned int offset)
+{
+	seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
+				   struct device_node *np,
+				   struct pinctrl_map **maps,
+				   unsigned int *num_maps)
+{
+	struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+	struct device *dev = sfp->gc.parent;
+	const struct starfive_pinctrl_soc_info *info = sfp->info;
+	struct starfive_pin *pin_data;
+	struct device_node *child;
+	struct pinctrl_map *map;
+	struct group_desc *grp;
+	const char **pgnames;
+	const char *grpname;
+	int ngroups;
+	int nmaps;
+	int ret;
+	int *pins_id;
+	int psize, pin_size;
+	int size = 0;
+	int offset = 0;
+	const __be32 *list;
+	int i, child_num_pins;
+
+	nmaps = 0;
+	ngroups = 0;
+	pin_size = STARFIVE_PINS_SIZE;
+
+	for_each_child_of_node(np, child) {
+		list = of_get_property(child, "starfive,pins", &psize);
+		if (!list) {
+			dev_err(sfp->dev,
+				"no starfive,pins and pins property in node %pOF\n", np);
+			return -EINVAL;
+		}
+		size += psize;
+	}
+
+	if (!size || size % pin_size) {
+		dev_err(sfp->dev,
+			"Invalid starfive,pins or pins property in node %pOF\n", np);
+		return -EINVAL;
+	}
+
+	nmaps = size / pin_size * 2;
+	ngroups = size / pin_size;
+
+	pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
+	if (!pgnames)
+		return -ENOMEM;
+
+	map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
+	if (!map)
+		return -ENOMEM;
+
+	grp = devm_kzalloc(sfp->dev, sizeof(struct group_desc), GFP_KERNEL);
+	if (!grp) {
+		of_node_put(child);
+		return -ENOMEM;
+	}
+
+	grp->data = devm_kcalloc(sfp->dev,
+				 ngroups, sizeof(struct starfive_pin),
+				 GFP_KERNEL);
+	grp->pins = devm_kcalloc(sfp->dev,
+				 ngroups, sizeof(int),
+				 GFP_KERNEL);
+	if (!grp->pins || !grp->data)
+		return -ENOMEM;
+
+	nmaps = 0;
+	ngroups = 0;
+	mutex_lock(&sfp->mutex);
+
+	for_each_child_of_node(np, child) {
+		grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
+		if (!grpname) {
+			ret = -ENOMEM;
+			goto put_child;
+		}
+
+		pgnames[ngroups++] = grpname;
+		map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+		map[nmaps].data.mux.function = np->name;
+		map[nmaps].data.mux.group = grpname;
+		nmaps += 1;
+
+		list = of_get_property(child, "starfive,pins", &psize);
+		if (!list) {
+			dev_err(sfp->dev,
+				"no starfive,pins and pins property in node %pOF\n", np);
+			goto put_child;
+		}
+		child_num_pins = psize / pin_size;
+		grp->name = grpname;
+		grp->num_pins = child_num_pins;
+		for (i = 0; i < child_num_pins; i++) {
+			pin_data = &((struct starfive_pin *)(grp->data))[i + offset];
+			pins_id =  &grp->pins[i + offset];
+
+			if (!info->starfive_pinctrl_parse_pin) {
+				dev_err(sfp->dev,
+					"pinmux ops lacks necessary functions\n");
+				goto put_child;
+			}
+
+			info->starfive_pinctrl_parse_pin(sfp,
+					pins_id, pin_data, list, child);
+			map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN;
+			map[nmaps].data.configs.group_or_pin =
+						pin_get_name(pctldev, pin_data->pin);
+			map[nmaps].data.configs.configs =
+						&pin_data->pin_config.io_config;
+			map[nmaps].data.configs.num_configs = 1;
+			nmaps += 1;
+
+			list++;
+		}
+		offset += i;
+
+		ret = pinctrl_generic_add_group(pctldev, grpname, pins_id,
+						child_num_pins, pin_data);
+		if (ret < 0) {
+			dev_err(dev, "error adding group %s: %d\n", grpname, ret);
+			goto put_child;
+		}
+	}
+
+	ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
+	if (ret < 0) {
+		dev_err(dev, "error adding function %s: %d\n", np->name, ret);
+		goto free_map;
+	}
+
+	*maps = map;
+	*num_maps = nmaps;
+	mutex_unlock(&sfp->mutex);
+	return 0;
+
+put_child:
+	of_node_put(child);
+free_map:
+	pinctrl_utils_free_map(pctldev, map, nmaps);
+	mutex_unlock(&sfp->mutex);
+	return ret;
+}
+
+static void starfive_dt_free_map(struct pinctrl_dev *pctldev,
+				 struct pinctrl_map *map,
+				 unsigned int num_maps)
+{
+	kfree(map);
+}
+
+static const struct pinctrl_ops starfive_pctrl_ops = {
+	.get_groups_count = pinctrl_generic_get_group_count,
+	.get_group_name = pinctrl_generic_get_group_name,
+	.get_group_pins = pinctrl_generic_get_group_pins,
+	.pin_dbg_show = starfive_pin_dbg_show,
+	.dt_node_to_map = starfive_dt_node_to_map,
+	.dt_free_map = starfive_dt_free_map,
+};
+
+static int starfive_pmx_set(struct pinctrl_dev *pctldev,
+			    unsigned int selector, unsigned int group)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+	struct function_desc *func;
+	struct group_desc *grp;
+	struct starfive_pin *pin;
+	unsigned int npins;
+	int i, err;
+
+	grp = pinctrl_generic_get_group(pctldev, group);
+	if (!grp)
+		return -EINVAL;
+
+	func = pinmux_generic_get_function(pctldev, selector);
+	if (!func)
+		return -EINVAL;
+
+	npins = grp->num_pins;
+
+	dev_dbg(pctl->dev, "enable function %s group %s\n",
+		func->name, grp->name);
+
+	for (i = 0; i < npins; i++) {
+		pin = &((struct starfive_pin *)(grp->data))[i];
+		if (info->starfive_pmx_set_one_pin_mux) {
+			err = info->starfive_pmx_set_one_pin_mux(pctl, pin);
+			if (err)
+				return err;
+		}
+	}
+
+	return 0;
+}
+
+const struct pinmux_ops starfive_pmx_ops = {
+	.get_functions_count = pinmux_generic_get_function_count,
+	.get_function_name = pinmux_generic_get_function_name,
+	.get_function_groups = pinmux_generic_get_function_groups,
+	.set_mux = starfive_pmx_set,
+};
+
+static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
+				unsigned int pin_id, unsigned long *config)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+
+	if (info->starfive_pinconf_get)
+		return info->starfive_pinconf_get(pctldev, pin_id, config);
+
+	return 0;
+}
+
+static int starfive_pinconf_set(struct pinctrl_dev *pctldev,
+				unsigned int pin_id, unsigned long *configs,
+				unsigned int num_configs)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pinctrl_soc_info *info = pctl->info;
+
+	if (info->starfive_pinconf_set)
+		return info->starfive_pinconf_set(pctldev, pin_id,
+				configs, num_configs);
+	return 0;
+}
+
+static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+				      struct seq_file *s, unsigned int pin_id)
+{
+	struct starfive_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	const struct starfive_pin_reg *pin_reg;
+	unsigned long config;
+	int ret;
+
+	pin_reg = &pctl->pin_regs[pin_id];
+	if (pin_reg->io_conf_reg == -1) {
+		seq_puts(s, "N/A");
+		return;
+	}
+
+	ret = starfive_pinconf_get(pctldev, pin_id, &config);
+	if (ret)
+		return;
+	seq_printf(s, "0x%lx", config);
+}
+
+static void starfive_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+					    struct seq_file *s, unsigned int group)
+{
+	struct group_desc *grp;
+	unsigned long config;
+	const char *name;
+	int i, ret;
+
+	if (group >= pctldev->num_groups)
+		return;
+
+	seq_puts(s, "\n");
+	grp = pinctrl_generic_get_group(pctldev, group);
+	if (!grp)
+		return;
+
+	for (i = 0; i < grp->num_pins; i++) {
+		struct starfive_pin *pin = &((struct starfive_pin *)(grp->data))[i];
+
+		name = pin_get_name(pctldev, pin->pin);
+		ret = starfive_pinconf_get(pctldev, pin->pin, &config);
+		if (ret)
+			return;
+		seq_printf(s, "  %s: 0x%lx\n", name, config);
+	}
+}
+
+static const struct pinconf_ops starfive_pinconf_ops = {
+	.pin_config_get = starfive_pinconf_get,
+	.pin_config_set = starfive_pinconf_set,
+	.pin_config_dbg_show = starfive_pinconf_dbg_show,
+	.pin_config_group_dbg_show = starfive_pinconf_group_dbg_show,
+};
+
+static void starfive_disable_clock(void *data)
+{
+	clk_disable_unprepare(data);
+}
+
+void pinctrl_write_reg(void __iomem *addr, u32 mask, u32 val)
+{
+	u32 value;
+
+	value = readl_relaxed(addr);
+	value &= ~mask;
+	value |= (val & mask);
+	writel_relaxed(value, addr);
+}
+
+uint32_t pinctrl_get_reg(void __iomem *addr, u32 shift, u32 mask)
+{
+	u32 tmp;
+
+	tmp = readl_relaxed(addr);
+	tmp = (tmp & mask) >> shift;
+	return tmp;
+}
+
+void pinctrl_set_reg(void __iomem *addr, u32 data, u32 shift, u32 mask)
+{
+	u32 tmp;
+
+	tmp = readl_relaxed(addr);
+	tmp &= ~mask;
+	tmp |= (data << shift) & mask;
+	writel_relaxed(tmp, addr);
+}
+
+struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
+{
+	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+
+	return container_of(gc, struct starfive_pinctrl, gc);
+}
+
+struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+
+	return container_of(gc, struct starfive_pinctrl, gc);
+}
+
+int starfive_pinctrl_probe(struct platform_device *pdev,
+			   const struct starfive_pinctrl_soc_info *info)
+{
+	struct device *dev = &pdev->dev;
+	struct pinctrl_desc *starfive_pinctrl_desc;
+	struct starfive_pinctrl *pctl;
+	struct resource *res;
+	struct reset_control *rst;
+	struct clk *clk;
+	int ret, i;
+	u32 value;
+
+	if (!info || !info->pins || !info->npins) {
+		dev_err(&pdev->dev, "wrong pinctrl info\n");
+		return -EINVAL;
+	}
+
+	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+	if (!pctl)
+		return -ENOMEM;
+
+	pctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
+					    sizeof(*pctl->pin_regs),
+					    GFP_KERNEL);
+	if (!pctl->pin_regs)
+		return -ENOMEM;
+
+	for (i = 0; i < info->npins; i++) {
+		pctl->pin_regs[i].io_conf_reg = -1;
+		pctl->pin_regs[i].gpo_dout_reg = -1;
+		pctl->pin_regs[i].gpo_doen_reg = -1;
+		pctl->pin_regs[i].func_sel_reg = -1;
+		pctl->pin_regs[i].syscon_reg = -1;
+		pctl->pin_regs[i].pad_sel_reg = -1;
+	}
+
+	pctl->padctl_base = devm_platform_ioremap_resource_byname(pdev, "control");
+	if (IS_ERR(pctl->padctl_base))
+		return PTR_ERR(pctl->padctl_base);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
+	if (res) {
+		pctl->gpio_base = devm_ioremap_resource(dev, res);
+		if (IS_ERR(pctl->gpio_base))
+			return PTR_ERR(pctl->gpio_base);
+	}
+
+	clk = devm_clk_get_optional(dev, NULL);
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
+
+	rst = devm_reset_control_get_exclusive(dev, NULL);
+	if (IS_ERR(rst))
+		return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
+
+	if (clk) {
+		ret = clk_prepare_enable(clk);
+		if (ret)
+			return dev_err_probe(dev, ret, "could not enable clock\n");
+
+		ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
+		if (ret)
+			return ret;
+	}
+
+	/*
+	 * We don't want to assert reset and risk undoing pin muxing for the
+	 * early boot serial console, but let's make sure the reset line is
+	 * deasserted in case someone runs a really minimal bootloader.
+	 */
+	ret = reset_control_deassert(rst);
+	if (ret)
+		return dev_err_probe(dev, ret, "could not deassert reset\n");
+
+	if (info->starfive_iopad_sel_func) {
+		ret = info->starfive_iopad_sel_func(pdev, pctl, value);
+		if (ret)
+			return ret;
+	}
+
+	starfive_pinctrl_desc = devm_kzalloc(&pdev->dev,
+					     sizeof(*starfive_pinctrl_desc),
+					     GFP_KERNEL);
+	if (!starfive_pinctrl_desc)
+		return -ENOMEM;
+
+	raw_spin_lock_init(&pctl->lock);
+
+	starfive_pinctrl_desc->name = dev_name(&pdev->dev);
+	starfive_pinctrl_desc->pins = info->pins;
+	starfive_pinctrl_desc->npins = info->npins;
+	starfive_pinctrl_desc->pctlops = &starfive_pctrl_ops;
+	starfive_pinctrl_desc->pmxops = &starfive_pmx_ops;
+	starfive_pinctrl_desc->confops = &starfive_pinconf_ops;
+	starfive_pinctrl_desc->owner = THIS_MODULE;
+
+	mutex_init(&pctl->mutex);
+
+	pctl->info = info;
+	pctl->dev = &pdev->dev;
+	platform_set_drvdata(pdev, pctl);
+	pctl->gc.parent = dev;
+	ret = devm_pinctrl_register_and_init(&pdev->dev,
+					     starfive_pinctrl_desc, pctl,
+					     &pctl->pctl_dev);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"could not register starfive pinctrl driver\n");
+		return ret;
+	}
+
+	ret = pinctrl_enable(pctl->pctl_dev);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"pin controller failed to start\n");
+		return ret;
+	}
+
+	if (info->starfive_gpio_register) {
+		ret = info->starfive_gpio_register(pdev, pctl);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"starfive_gpio_register failed to register\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(starfive_pinctrl_probe);
+
+static int __maybe_unused starfive_pinctrl_suspend(struct device *dev)
+{
+	struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
+
+	return pinctrl_force_sleep(pctl->pctl_dev);
+}
+
+static int __maybe_unused starfive_pinctrl_resume(struct device *dev)
+{
+	struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
+
+	return pinctrl_force_default(pctl->pctl_dev);
+}
+
+const struct dev_pm_ops starfive_pinctrl_pm_ops = {
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(starfive_pinctrl_suspend,
+				     starfive_pinctrl_resume)
+};
+EXPORT_SYMBOL_GPL(starfive_pinctrl_pm_ops);
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JH7110 SoC");
+MODULE_AUTHOR("Jenny Zhang <jenny.zhang@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.h b/drivers/pinctrl/starfive/pinctrl-starfive.h
new file mode 100644
index 000000000000..8b956d07baae
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DRIVERS_PINCTRL_STARFIVE_H__
+#define __DRIVERS_PINCTRL_STARFIVE_H__
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+
+#define MAX_GPIO				64
+#define STARFIVE_PINS_SIZE		4
+
+/* 8 bits for each gpio */
+#define GPIO_BYTE_SHIFT			3
+#define GET_GPO_CFG_SHIFT(gpio)		(((gpio) & 0x3) << GPIO_BYTE_SHIFT)
+#define GET_GPO_REG_OFFSET(gpio)	((gpio) & ~0x3)
+
+struct platform_device;
+
+extern const struct pinmux_ops starfive_pmx_ops;
+extern const struct dev_pm_ops starfive_pinctrl_pm_ops;
+
+struct starfive_pin_config {
+	unsigned long io_config;
+	u32 pinmux_func;
+	u32 gpio_num;
+	u32 gpio_dout;
+	u32 gpio_doen;
+	u32 gpio_din_num;
+	s32 *gpio_din_reg;
+	s32 syscon;
+	s32 padmux_func;
+};
+
+struct starfive_pin {
+	unsigned int pin;
+	struct starfive_pin_config pin_config;
+};
+
+struct starfive_pin_reg {
+	s32 io_conf_reg;
+	s32 gpo_dout_reg;
+	s32 gpo_doen_reg;
+	s32 func_sel_reg;
+	s32 func_sel_shift;
+	s32 func_sel_mask;
+	s32 syscon_reg;
+	s32 pad_sel_reg;
+	s32 pad_sel_shift;
+	s32 pad_sel_mask;
+};
+
+struct starfive_iopad_sel_func_inf {
+	unsigned int padctl_gpio_base;
+	unsigned int padctl_gpio0;
+};
+
+struct starfive_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pctl_dev;
+	void __iomem *padctl_base;
+	void __iomem *gpio_base;
+	unsigned int padctl_gpio_base;
+	unsigned int padctl_gpio0;
+	const struct starfive_pinctrl_soc_info *info;
+	struct starfive_pin_reg *pin_regs;
+	unsigned int group_index;
+
+	struct mutex mutex;
+	raw_spinlock_t lock;
+
+	struct gpio_chip gc;
+	struct pinctrl_gpio_range gpios;
+	unsigned long enabled;
+	unsigned int trigger[MAX_GPIO];
+};
+
+struct starfive_pinctrl_soc_info {
+	const struct pinctrl_pin_desc *pins;
+	unsigned int npins;
+	unsigned int flags;
+
+	/*gpio dout/doen/din register*/
+	unsigned int dout_reg_base;
+	unsigned int dout_reg_offset;
+	unsigned int doen_reg_base;
+	unsigned int doen_reg_offset;
+	unsigned int din_reg_base;
+	unsigned int din_reg_offset;
+
+	/* sel-function */
+	int (*starfive_iopad_sel_func)(struct platform_device *pdev,
+				       struct starfive_pinctrl *ipctl,
+				       unsigned int func_id);
+	/* generic pinconf */
+	int (*starfive_pinconf_get)(struct pinctrl_dev *pctldev,
+				    unsigned int pin_id,
+				    unsigned long *config);
+	int (*starfive_pinconf_set)(struct pinctrl_dev *pctldev,
+				    unsigned int pin_id,
+				    unsigned long *configs,
+				    unsigned int num_configs);
+
+	/* generic pinmux */
+	int (*starfive_pmx_set_one_pin_mux)(struct starfive_pinctrl *ipctl,
+					    struct starfive_pin *pin);
+	/* gpio chip */
+	int (*starfive_gpio_register)(struct platform_device *pdev,
+				      struct starfive_pinctrl *ipctl);
+	void (*starfive_pinctrl_parse_pin)(struct starfive_pinctrl *ipctl,
+					   unsigned int *pins_id,
+					   struct starfive_pin *pin_data,
+					   const __be32 *list_p,
+					   struct device_node *np);
+};
+
+#define	STARFIVE_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+int starfive_pinctrl_probe(struct platform_device *pdev,
+			   const struct starfive_pinctrl_soc_info *info);
+void pinctrl_write_reg(void __iomem *addr, u32 mask, u32 val);
+uint32_t pinctrl_get_reg(void __iomem *addr, u32 shift, u32 mask);
+void pinctrl_set_reg(void __iomem *addr, u32 data, u32 shift, u32 mask);
+struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc);
+struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d);
+
+#endif /* __DRIVERS_PINCTRL_STARFIVE_H__ */
-- 
2.17.1

Re: [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 7100 bytes --]

Hi Hal,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v6.0-rc7 next-20220930]
[cannot apply to clk/clk-next linusw-pinctrl/devel pza/reset/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Hal-Feng/Basic-StarFive-JH7110-RISC-V-SoC-support/20220930-202655
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 987a926c1d8a40e4256953b04771fbdb63bc7938
config: riscv-buildonly-randconfig-r006-20220926
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install riscv cross compiling tool for clang build
        # apt-get install binutils-riscv64-linux-gnu
        # https://github.com/intel-lab-lkp/linux/commit/9ef892ebb8b08cc65ab165f4962864e12b5c216d
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Hal-Feng/Basic-StarFive-JH7110-RISC-V-SoC-support/20220930-202655
        git checkout 9ef892ebb8b08cc65ab165f4962864e12b5c216d
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/pinctrl/starfive/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/pinctrl/starfive/pinctrl-starfive.c:462:51: warning: variable 'value' is uninitialized when used here [-Wuninitialized]
                   ret = info->starfive_iopad_sel_func(pdev, pctl, value);
                                                                   ^~~~~
   drivers/pinctrl/starfive/pinctrl-starfive.c:397:11: note: initialize the variable 'value' to silence this warning
           u32 value;
                    ^
                     = 0
   drivers/pinctrl/starfive/pinctrl-starfive.c:32:1: warning: unused function 'starfive_pinctrl_find_group_by_name' [-Wunused-function]
   starfive_pinctrl_find_group_by_name(struct pinctrl_dev *pctldev,
   ^
   2 warnings generated.


vim +/value +462 drivers/pinctrl/starfive/pinctrl-starfive.c

   386	
   387	int starfive_pinctrl_probe(struct platform_device *pdev,
   388				   const struct starfive_pinctrl_soc_info *info)
   389	{
   390		struct device *dev = &pdev->dev;
   391		struct pinctrl_desc *starfive_pinctrl_desc;
   392		struct starfive_pinctrl *pctl;
   393		struct resource *res;
   394		struct reset_control *rst;
   395		struct clk *clk;
   396		int ret, i;
   397		u32 value;
   398	
   399		if (!info || !info->pins || !info->npins) {
   400			dev_err(&pdev->dev, "wrong pinctrl info\n");
   401			return -EINVAL;
   402		}
   403	
   404		pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
   405		if (!pctl)
   406			return -ENOMEM;
   407	
   408		pctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
   409						    sizeof(*pctl->pin_regs),
   410						    GFP_KERNEL);
   411		if (!pctl->pin_regs)
   412			return -ENOMEM;
   413	
   414		for (i = 0; i < info->npins; i++) {
   415			pctl->pin_regs[i].io_conf_reg = -1;
   416			pctl->pin_regs[i].gpo_dout_reg = -1;
   417			pctl->pin_regs[i].gpo_doen_reg = -1;
   418			pctl->pin_regs[i].func_sel_reg = -1;
   419			pctl->pin_regs[i].syscon_reg = -1;
   420			pctl->pin_regs[i].pad_sel_reg = -1;
   421		}
   422	
   423		pctl->padctl_base = devm_platform_ioremap_resource_byname(pdev, "control");
   424		if (IS_ERR(pctl->padctl_base))
   425			return PTR_ERR(pctl->padctl_base);
   426	
   427		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
   428		if (res) {
   429			pctl->gpio_base = devm_ioremap_resource(dev, res);
   430			if (IS_ERR(pctl->gpio_base))
   431				return PTR_ERR(pctl->gpio_base);
   432		}
   433	
   434		clk = devm_clk_get_optional(dev, NULL);
   435		if (IS_ERR(clk))
   436			return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
   437	
   438		rst = devm_reset_control_get_exclusive(dev, NULL);
   439		if (IS_ERR(rst))
   440			return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
   441	
   442		if (clk) {
   443			ret = clk_prepare_enable(clk);
   444			if (ret)
   445				return dev_err_probe(dev, ret, "could not enable clock\n");
   446	
   447			ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
   448			if (ret)
   449				return ret;
   450		}
   451	
   452		/*
   453		 * We don't want to assert reset and risk undoing pin muxing for the
   454		 * early boot serial console, but let's make sure the reset line is
   455		 * deasserted in case someone runs a really minimal bootloader.
   456		 */
   457		ret = reset_control_deassert(rst);
   458		if (ret)
   459			return dev_err_probe(dev, ret, "could not deassert reset\n");
   460	
   461		if (info->starfive_iopad_sel_func) {
 > 462			ret = info->starfive_iopad_sel_func(pdev, pctl, value);
   463			if (ret)
   464				return ret;
   465		}
   466	
   467		starfive_pinctrl_desc = devm_kzalloc(&pdev->dev,
   468						     sizeof(*starfive_pinctrl_desc),
   469						     GFP_KERNEL);
   470		if (!starfive_pinctrl_desc)
   471			return -ENOMEM;
   472	
   473		raw_spin_lock_init(&pctl->lock);
   474	
   475		starfive_pinctrl_desc->name = dev_name(&pdev->dev);
   476		starfive_pinctrl_desc->pins = info->pins;
   477		starfive_pinctrl_desc->npins = info->npins;
   478		starfive_pinctrl_desc->pctlops = &starfive_pctrl_ops;
   479		starfive_pinctrl_desc->pmxops = &starfive_pmx_ops;
   480		starfive_pinctrl_desc->confops = &starfive_pinconf_ops;
   481		starfive_pinctrl_desc->owner = THIS_MODULE;
   482	
   483		mutex_init(&pctl->mutex);
   484	
   485		pctl->info = info;
   486		pctl->dev = &pdev->dev;
   487		platform_set_drvdata(pdev, pctl);
   488		pctl->gc.parent = dev;
   489		ret = devm_pinctrl_register_and_init(&pdev->dev,
   490						     starfive_pinctrl_desc, pctl,
   491						     &pctl->pctl_dev);
   492		if (ret) {
   493			dev_err(&pdev->dev,
   494				"could not register starfive pinctrl driver\n");
   495			return ret;
   496		}
   497	
   498		ret = pinctrl_enable(pctl->pctl_dev);
   499		if (ret) {
   500			dev_err(&pdev->dev,
   501				"pin controller failed to start\n");
   502			return ret;
   503		}
   504	
   505		if (info->starfive_gpio_register) {
   506			ret = info->starfive_gpio_register(pdev, pctl);
   507			if (ret) {
   508				dev_err(&pdev->dev,
   509					"starfive_gpio_register failed to register\n");
   510				return ret;
   511			}
   512		}
   513	
   514		return 0;
   515	}
   516	EXPORT_SYMBOL_GPL(starfive_pinctrl_probe);
   517	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

[-- Attachment #2: config --]
[-- Type: text/plain, Size: 193270 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/riscv 6.0.0-rc7 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="clang version 16.0.0 (git://gitmirror/llvm_project 791a7ae1ba3efd6bca96338e10ffde557ba83920)"
CONFIG_GCC_VERSION=0
CONFIG_CC_IS_CLANG=y
CONFIG_CLANG_VERSION=160000
CONFIG_AS_IS_LLVM=y
CONFIG_AS_VERSION=160000
CONFIG_LD_VERSION=0
CONFIG_LD_IS_LLD=y
CONFIG_LLD_VERSION=160000
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=123
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_COMPILE_TEST=y
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_WATCH_QUEUE=y
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
# CONFIG_AUDIT is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_DEBUGFS=y
# end of IRQ subsystem

CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_TIME_KUNIT_TEST=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
CONFIG_USERMODE_DRIVER=y
# end of BPF subsystem

CONFIG_PREEMPT_BUILD=y
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
CONFIG_PSI=y
# CONFIG_PSI_DEFAULT_DISABLED is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_FORCE_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_FORCE_TASKS_RUDE_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_FORCE_TASKS_TRACE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_FANOUT=64
CONFIG_RCU_FANOUT_LEAF=16
CONFIG_RCU_BOOST=y
CONFIG_RCU_BOOST_DELAY=500
# CONFIG_RCU_EXP_KTHREAD is not set
# CONFIG_RCU_NOCB_CPU is not set
# CONFIG_TASKS_TRACE_RCU_READ_MB is not set
# end of RCU Subsystem

CONFIG_IKCONFIG=y
# CONFIG_IKCONFIG_PROC is not set
CONFIG_IKHEADERS=y
CONFIG_LOG_BUF_SHIFT=17
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_PRINTK_INDEX=y
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# end of Scheduler features

CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough"
CONFIG_GCC12_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_CFS_BANDWIDTH is not set
CONFIG_RT_GROUP_SCHED=y
# CONFIG_CGROUP_PIDS is not set
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
# CONFIG_CGROUP_BPF is not set
CONFIG_CGROUP_MISC=y
CONFIG_CGROUP_DEBUG=y
# CONFIG_NAMESPACES is not set
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
# CONFIG_RD_LZ4 is not set
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_EMBED is not set
# CONFIG_INITRAMFS_PRESERVE_MTIME is not set
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
# CONFIG_BUG is not set
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
# CONFIG_TIMERFD is not set
CONFIG_EVENTFD=y
# CONFIG_SHMEM is not set
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
# CONFIG_PERF_EVENTS is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_64BIT=y
CONFIG_RISCV=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
CONFIG_RISCV_SBI=y
CONFIG_MMU=y
CONFIG_PAGE_OFFSET=0xff60000000000000
CONFIG_KASAN_SHADOW_OFFSET=0xdfffffff00000000
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=5
CONFIG_LOCKDEP_SUPPORT=y

#
# SoC selection
#
# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
# CONFIG_SOC_SIFIVE is not set
CONFIG_SOC_STARFIVE=y
# CONFIG_SOC_VIRT is not set
# end of SoC selection

#
# CPU errata selection
#
CONFIG_ERRATA_SIFIVE=y
# CONFIG_ERRATA_SIFIVE_CIP_453 is not set
# CONFIG_ERRATA_SIFIVE_CIP_1200 is not set
CONFIG_ERRATA_THEAD=y
CONFIG_ERRATA_THEAD_PBMT=y
# CONFIG_ERRATA_THEAD_CMO is not set
# end of CPU errata selection

#
# Platform type
#
CONFIG_NONPORTABLE=y
# CONFIG_ARCH_RV32I is not set
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDLOW=y
# CONFIG_CMODEL_MEDANY is not set
# CONFIG_SMP is not set
CONFIG_TUNE_GENERIC=y
CONFIG_RISCV_ALTERNATIVE=y
CONFIG_RISCV_ALTERNATIVE_EARLY=y
CONFIG_RISCV_ISA_C=y
# CONFIG_RISCV_ISA_SVPBMT is not set
CONFIG_CC_HAS_ZICBOM=y
# CONFIG_RISCV_ISA_ZICBOM is not set
CONFIG_FPU=y
# end of Platform type

#
# Kernel features
#
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
# CONFIG_RISCV_SBI_V01 is not set
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
CONFIG_ARCH_HAS_KEXEC_PURGATORY=y
# CONFIG_CRASH_DUMP is not set
# CONFIG_COMPAT is not set
# end of Kernel features

#
# Boot options
#
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_PHYS_RAM_BASE_FIXED=y
CONFIG_PHYS_RAM_BASE=0x80000000
# end of Boot options

#
# Power management options
#
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
# CONFIG_CPU_IDLE is not set
# end of CPU Idle
# end of CPU Power Management

# CONFIG_VIRTUALIZATION is not set

#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_KEXEC_ELF=y
# CONFIG_JUMP_LABEL is not set
CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
# CONFIG_SECCOMP is not set
CONFIG_HAVE_STACKPROTECTOR=y
# CONFIG_STACKPROTECTOR is not set
CONFIG_LTO_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
# CONFIG_STRICT_KERNEL_RWX is not set
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_LOCK_EVENT_COUNTS=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
# CONFIG_BLOCK is not set
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_MMIOWB=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_ELF_KUNIT_TEST=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_ARCH_HAS_BINFMT_FLAT=y
# CONFIG_BINFMT_FLAT is not set
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#

#
# SLAB allocator options
#
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
# CONFIG_SLAB_FREELIST_HARDENED is not set
# end of SLAB allocator options

# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_COMPACTION=y
# CONFIG_PAGE_REPORTING is not set
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
# CONFIG_TRANSPARENT_HUGEPAGE is not set
CONFIG_NEED_PER_CPU_KM=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_PAGE_IDLE_FLAG=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ZONE_DMA32=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_PERCPU_STATS=y
# CONFIG_GUP_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_ANON_VMA_NAME=y
CONFIG_USERFAULTFD=y

#
# Data Access Monitoring
#
CONFIG_DAMON=y
CONFIG_DAMON_KUNIT_TEST=y
CONFIG_DAMON_VADDR=y
CONFIG_DAMON_PADDR=y
CONFIG_DAMON_VADDR_KUNIT_TEST=y
CONFIG_DAMON_SYSFS=y
# CONFIG_DAMON_DBGFS is not set
# CONFIG_DAMON_RECLAIM is not set
CONFIG_DAMON_LRU_SORT=y
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_NET_EGRESS=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
# CONFIG_UNIX_DIAG is not set
CONFIG_TLS=y
# CONFIG_TLS_DEVICE is not set
# CONFIG_TLS_TOE is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_INTERFACE is not set
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=y
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=y
# CONFIG_NET_IPGRE_BROADCAST is not set
CONFIG_IP_MROUTE_COMMON=y
# CONFIG_IP_MROUTE is not set
# CONFIG_SYN_COOKIES is not set
CONFIG_NET_IPVTI=y
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=y
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=y
# CONFIG_INET6_ESPINTCP is not set
# CONFIG_INET6_IPCOMP is not set
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_ILA=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=y
CONFIG_IPV6_SIT=y
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=y
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
CONFIG_IPV6_RPL_LWTUNNEL=y
CONFIG_IPV6_IOAM6_LWTUNNEL=y
# CONFIG_MPTCP is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=y

#
# Core Netfilter Configuration
#
# CONFIG_NETFILTER_INGRESS is not set
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_NETLINK_HOOK=y
CONFIG_NETFILTER_NETLINK_ACCT=y
CONFIG_NETFILTER_NETLINK_QUEUE=y
CONFIG_NETFILTER_NETLINK_LOG=y
CONFIG_NETFILTER_NETLINK_OSF=y
# CONFIG_NF_CONNTRACK is not set
CONFIG_NF_LOG_SYSLOG=y
CONFIG_NF_TABLES=y
# CONFIG_NF_TABLES_INET is not set
# CONFIG_NF_TABLES_NETDEV is not set
CONFIG_NFT_NUMGEN=y
# CONFIG_NFT_LOG is not set
CONFIG_NFT_LIMIT=y
# CONFIG_NFT_TUNNEL is not set
CONFIG_NFT_OBJREF=y
CONFIG_NFT_QUEUE=y
# CONFIG_NFT_QUOTA is not set
CONFIG_NFT_REJECT=y
# CONFIG_NFT_COMPAT is not set
CONFIG_NFT_HASH=y
# CONFIG_NFT_XFRM is not set
CONFIG_NFT_SOCKET=y
CONFIG_NFT_OSF=y
CONFIG_NFT_TPROXY=y
CONFIG_NETFILTER_XTABLES=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
# CONFIG_NETFILTER_XT_SET is not set

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_HMARK=y
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
CONFIG_NETFILTER_XT_TARGET_LED=y
CONFIG_NETFILTER_XT_TARGET_LOG=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_RATEEST=y
CONFIG_NETFILTER_XT_TARGET_TEE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
CONFIG_NETFILTER_XT_MATCH_BPF=y
# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CPU=y
# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
CONFIG_NETFILTER_XT_MATCH_DSCP=y
CONFIG_NETFILTER_XT_MATCH_ECN=y
CONFIG_NETFILTER_XT_MATCH_ESP=y
# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
CONFIG_NETFILTER_XT_MATCH_HL=y
# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_L2TP=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
# CONFIG_NETFILTER_XT_MATCH_MARK is not set
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
CONFIG_NETFILTER_XT_MATCH_NFACCT=y
CONFIG_NETFILTER_XT_MATCH_OSF=y
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
CONFIG_NETFILTER_XT_MATCH_REALM=y
# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
CONFIG_NETFILTER_XT_MATCH_SCTP=y
# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
# end of Core Netfilter Configuration

CONFIG_IP_SET=y
CONFIG_IP_SET_MAX=256
# CONFIG_IP_SET_BITMAP_IP is not set
CONFIG_IP_SET_BITMAP_IPMAC=y
CONFIG_IP_SET_BITMAP_PORT=y
CONFIG_IP_SET_HASH_IP=y
CONFIG_IP_SET_HASH_IPMARK=y
CONFIG_IP_SET_HASH_IPPORT=y
# CONFIG_IP_SET_HASH_IPPORTIP is not set
# CONFIG_IP_SET_HASH_IPPORTNET is not set
CONFIG_IP_SET_HASH_IPMAC=y
CONFIG_IP_SET_HASH_MAC=y
CONFIG_IP_SET_HASH_NETPORTNET=y
CONFIG_IP_SET_HASH_NET=y
CONFIG_IP_SET_HASH_NETNET=y
# CONFIG_IP_SET_HASH_NETPORT is not set
# CONFIG_IP_SET_HASH_NETIFACE is not set
CONFIG_IP_SET_LIST_SET=y
CONFIG_IP_VS=y
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
# CONFIG_IP_VS_PROTO_SCTP is not set

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=y
CONFIG_IP_VS_WRR=y
# CONFIG_IP_VS_LC is not set
CONFIG_IP_VS_WLC=y
CONFIG_IP_VS_FO=y
CONFIG_IP_VS_OVF=y
# CONFIG_IP_VS_LBLC is not set
# CONFIG_IP_VS_LBLCR is not set
CONFIG_IP_VS_DH=y
CONFIG_IP_VS_SH=y
CONFIG_IP_VS_MH=y
CONFIG_IP_VS_SED=y
CONFIG_IP_VS_NQ=y
CONFIG_IP_VS_TWOS=y

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=y
CONFIG_NF_TPROXY_IPV4=y
# CONFIG_NF_TABLES_IPV4 is not set
# CONFIG_NF_TABLES_ARP is not set
CONFIG_NF_DUP_IPV4=y
# CONFIG_NF_LOG_ARP is not set
# CONFIG_NF_LOG_IPV4 is not set
# CONFIG_NF_REJECT_IPV4 is not set
CONFIG_IP_NF_IPTABLES=y
# CONFIG_IP_NF_MATCH_AH is not set
CONFIG_IP_NF_MATCH_ECN=y
# CONFIG_IP_NF_MATCH_TTL is not set
# CONFIG_IP_NF_FILTER is not set
# CONFIG_IP_NF_MANGLE is not set
# CONFIG_IP_NF_RAW is not set
# CONFIG_IP_NF_ARPTABLES is not set
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=y
# CONFIG_NF_TPROXY_IPV6 is not set
# CONFIG_NF_TABLES_IPV6 is not set
CONFIG_NF_DUP_IPV6=y
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
# CONFIG_IP6_NF_MATCH_AH is not set
CONFIG_IP6_NF_MATCH_EUI64=y
CONFIG_IP6_NF_MATCH_FRAG=y
CONFIG_IP6_NF_MATCH_OPTS=y
CONFIG_IP6_NF_MATCH_HL=y
CONFIG_IP6_NF_MATCH_IPV6HEADER=y
CONFIG_IP6_NF_MATCH_MH=y
# CONFIG_IP6_NF_MATCH_RT is not set
CONFIG_IP6_NF_MATCH_SRH=y
# CONFIG_IP6_NF_FILTER is not set
# CONFIG_IP6_NF_MANGLE is not set
# CONFIG_IP6_NF_RAW is not set
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=y
# CONFIG_NFT_BRIDGE_META is not set
CONFIG_BRIDGE_NF_EBTABLES=y
# CONFIG_BRIDGE_EBT_BROUTE is not set
CONFIG_BRIDGE_EBT_T_FILTER=y
CONFIG_BRIDGE_EBT_T_NAT=y
CONFIG_BRIDGE_EBT_802_3=y
CONFIG_BRIDGE_EBT_AMONG=y
# CONFIG_BRIDGE_EBT_ARP is not set
CONFIG_BRIDGE_EBT_IP=y
CONFIG_BRIDGE_EBT_IP6=y
CONFIG_BRIDGE_EBT_LIMIT=y
CONFIG_BRIDGE_EBT_MARK=y
CONFIG_BRIDGE_EBT_PKTTYPE=y
CONFIG_BRIDGE_EBT_STP=y
CONFIG_BRIDGE_EBT_VLAN=y
CONFIG_BRIDGE_EBT_ARPREPLY=y
CONFIG_BRIDGE_EBT_DNAT=y
CONFIG_BRIDGE_EBT_MARK_T=y
CONFIG_BRIDGE_EBT_REDIRECT=y
CONFIG_BRIDGE_EBT_SNAT=y
CONFIG_BRIDGE_EBT_LOG=y
CONFIG_BRIDGE_EBT_NFLOG=y
CONFIG_BPFILTER=y
CONFIG_IP_DCCP=y

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
# CONFIG_IP_DCCP_CCID3 is not set
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=y
CONFIG_SCTP_DBG_OBJCNT=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
# CONFIG_SCTP_COOKIE_HMAC_MD5 is not set
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_RDS=y
CONFIG_RDS_TCP=y
# CONFIG_RDS_DEBUG is not set
# CONFIG_TIPC is not set
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
# CONFIG_ATM_CLIP_NO_ICMP is not set
# CONFIG_ATM_LANE is not set
CONFIG_ATM_BR2684=y
CONFIG_ATM_BR2684_IPFILTER=y
CONFIG_L2TP=y
CONFIG_L2TP_DEBUGFS=y
# CONFIG_L2TP_V3 is not set
CONFIG_STP=y
CONFIG_BRIDGE=y
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
CONFIG_LLC=y
CONFIG_LLC2=y
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
CONFIG_LAPB=y
CONFIG_PHONET=y
CONFIG_6LOWPAN=y
CONFIG_6LOWPAN_DEBUGFS=y
CONFIG_6LOWPAN_NHC=y
CONFIG_6LOWPAN_NHC_DEST=y
CONFIG_6LOWPAN_NHC_FRAGMENT=y
CONFIG_6LOWPAN_NHC_HOP=y
CONFIG_6LOWPAN_NHC_IPV6=y
CONFIG_6LOWPAN_NHC_MOBILITY=y
CONFIG_6LOWPAN_NHC_ROUTING=y
# CONFIG_6LOWPAN_NHC_UDP is not set
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=y
# CONFIG_6LOWPAN_GHC_UDP is not set
CONFIG_6LOWPAN_GHC_ICMPV6=y
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=y
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=y
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=y
CONFIG_IEEE802154=y
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=y
# CONFIG_IEEE802154_6LOWPAN is not set
# CONFIG_MAC802154 is not set
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_CBQ=y
CONFIG_NET_SCH_HTB=y
# CONFIG_NET_SCH_HFSC is not set
CONFIG_NET_SCH_ATM=y
# CONFIG_NET_SCH_PRIO is not set
CONFIG_NET_SCH_MULTIQ=y
# CONFIG_NET_SCH_RED is not set
CONFIG_NET_SCH_SFB=y
CONFIG_NET_SCH_SFQ=y
# CONFIG_NET_SCH_TEQL is not set
CONFIG_NET_SCH_TBF=y
CONFIG_NET_SCH_CBS=y
CONFIG_NET_SCH_ETF=y
CONFIG_NET_SCH_TAPRIO=y
CONFIG_NET_SCH_GRED=y
CONFIG_NET_SCH_DSMARK=y
# CONFIG_NET_SCH_NETEM is not set
CONFIG_NET_SCH_DRR=y
# CONFIG_NET_SCH_MQPRIO is not set
CONFIG_NET_SCH_SKBPRIO=y
CONFIG_NET_SCH_CHOKE=y
# CONFIG_NET_SCH_QFQ is not set
CONFIG_NET_SCH_CODEL=y
# CONFIG_NET_SCH_FQ_CODEL is not set
# CONFIG_NET_SCH_CAKE is not set
CONFIG_NET_SCH_FQ=y
# CONFIG_NET_SCH_HHF is not set
# CONFIG_NET_SCH_PIE is not set
# CONFIG_NET_SCH_PLUG is not set
# CONFIG_NET_SCH_ETS is not set
CONFIG_NET_SCH_DEFAULT=y
# CONFIG_DEFAULT_FQ is not set
CONFIG_DEFAULT_CODEL=y
# CONFIG_DEFAULT_SFQ is not set
# CONFIG_DEFAULT_PFIFO_FAST is not set
CONFIG_DEFAULT_NET_SCH="pfifo_fast"

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=y
# CONFIG_NET_CLS_TCINDEX is not set
CONFIG_NET_CLS_ROUTE4=y
CONFIG_NET_CLS_FW=y
# CONFIG_NET_CLS_U32 is not set
CONFIG_NET_CLS_RSVP=y
CONFIG_NET_CLS_RSVP6=y
CONFIG_NET_CLS_FLOW=y
# CONFIG_NET_CLS_CGROUP is not set
CONFIG_NET_CLS_BPF=y
CONFIG_NET_CLS_FLOWER=y
# CONFIG_NET_CLS_MATCHALL is not set
# CONFIG_NET_EMATCH is not set
# CONFIG_NET_CLS_ACT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
# CONFIG_BATMAN_ADV is not set
CONFIG_OPENVSWITCH=y
CONFIG_OPENVSWITCH_GRE=y
# CONFIG_VSOCKETS is not set
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=y
CONFIG_NET_NSH=y
CONFIG_HSR=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=y
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
# CONFIG_NET_NCSI is not set
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y

#
# Network testing
#
CONFIG_NET_PKTGEN=y
CONFIG_NET_DROP_MONITOR=y
# end of Network testing
# end of Networking options

CONFIG_HAMRADIO=y

#
# Packet Radio protocols
#
CONFIG_AX25=y
# CONFIG_AX25_DAMA_SLAVE is not set
# CONFIG_NETROM is not set
CONFIG_ROSE=y

#
# AX.25 network device drivers
#
CONFIG_BPQETHER=y
# CONFIG_BAYCOM_SER_FDX is not set
# CONFIG_BAYCOM_SER_HDX is not set
CONFIG_BAYCOM_PAR=y
# CONFIG_YAM is not set
# end of AX.25 network device drivers

# CONFIG_CAN is not set
# CONFIG_BT is not set
CONFIG_AF_RXRPC=y
CONFIG_AF_RXRPC_IPV6=y
CONFIG_AF_RXRPC_INJECT_LOSS=y
CONFIG_AF_RXRPC_DEBUG=y
# CONFIG_RXKAD is not set
CONFIG_AF_KCM=y
CONFIG_STREAM_PARSER=y
CONFIG_MCTP=y
CONFIG_MCTP_TEST=y
CONFIG_FIB_RULES=y
# CONFIG_WIRELESS is not set
# CONFIG_RFKILL is not set
CONFIG_NET_9P=y
# CONFIG_NET_9P_FD is not set
CONFIG_NET_9P_VIRTIO=y
# CONFIG_NET_9P_DEBUG is not set
CONFIG_CAIF=y
# CONFIG_CAIF_DEBUG is not set
CONFIG_CAIF_NETDEV=y
# CONFIG_CAIF_USB is not set
CONFIG_CEPH_LIB=y
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
CONFIG_NFC=y
# CONFIG_NFC_DIGITAL is not set
CONFIG_NFC_NCI=y
# CONFIG_NFC_HCI is not set

#
# Near Field Communication (NFC) devices
#
CONFIG_NFC_VIRTUAL_NCI=y
CONFIG_NFC_FDP=y
# CONFIG_NFC_FDP_I2C is not set
CONFIG_NFC_PN533=y
CONFIG_NFC_PN533_USB=y
CONFIG_NFC_PN533_I2C=y
# CONFIG_NFC_MRVL_USB is not set
CONFIG_NFC_ST_NCI=y
CONFIG_NFC_ST_NCI_I2C=y
CONFIG_NFC_NXP_NCI=y
CONFIG_NFC_NXP_NCI_I2C=y
# CONFIG_NFC_S3FWRN5_I2C is not set
# end of Near Field Communication (NFC) devices

CONFIG_PSAMPLE=y
# CONFIG_NET_IFE is not set
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=y
# CONFIG_ETHTOOL_NETLINK is not set
CONFIG_NETDEV_ADDR_LIST_TEST=y

#
# Device Drivers
#
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=y
# CONFIG_PCIE_ECRC is not set
# CONFIG_PCIEASPM is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_DPC is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
# CONFIG_PCI_QUIRKS is not set
CONFIG_PCI_DEBUG=y
CONFIG_PCI_REALLOC_ENABLE_AUTO=y
CONFIG_PCI_STUB=y
CONFIG_PCI_PF_STUB=y
CONFIG_PCI_ATS=y
CONFIG_PCI_DOE=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
# CONFIG_PCI_PASID is not set
# CONFIG_PCIE_BUS_TUNE_OFF is not set
# CONFIG_PCIE_BUS_DEFAULT is not set
CONFIG_PCIE_BUS_SAFE=y
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_VGA_ARB is not set
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set

#
# PCI controller drivers
#
# CONFIG_PCI_AARDVARK is not set
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCI_FTPCI100=y
# CONFIG_PCI_TEGRA is not set
CONFIG_PCIE_RCAR_HOST=y
CONFIG_PCI_HOST_COMMON=y
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
CONFIG_PCIE_XILINX_CPM=y
# CONFIG_PCI_XGENE is not set
CONFIG_PCI_V3_SEMI=y
# CONFIG_PCI_VERSATILE is not set
CONFIG_PCIE_ALTERA=y
# CONFIG_PCIE_ALTERA_MSI is not set
CONFIG_PCI_HOST_THUNDER_PEM=y
CONFIG_PCI_HOST_THUNDER_ECAM=y
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCIE_MEDIATEK=y
# CONFIG_PCIE_MEDIATEK_GEN3 is not set
# CONFIG_PCIE_BRCMSTB is not set
# CONFIG_PCIE_MICROCHIP_HOST is not set
CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR=0xfffff000
CONFIG_PCIE_APPLE=y
CONFIG_PCIE_MT7621=y

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCI_EXYNOS=y
CONFIG_PCI_IMX6=y
# CONFIG_PCIE_SPEAR13XX is not set
# CONFIG_PCI_KEYSTONE_HOST is not set
# CONFIG_PCI_LAYERSCAPE is not set
CONFIG_PCI_HISI=y
# CONFIG_PCIE_QCOM is not set
CONFIG_PCIE_ARMADA_8K=y
CONFIG_PCIE_ARTPEC6=y
CONFIG_PCIE_ARTPEC6_HOST=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PCIE_INTEL_GW=y
# CONFIG_PCIE_KEEMBAY_HOST is not set
CONFIG_PCIE_KIRIN=y
CONFIG_PCIE_HISI_STB=y
CONFIG_PCI_MESON=y
# CONFIG_PCIE_TEGRA194_HOST is not set
# CONFIG_PCIE_VISCONTI_HOST is not set
CONFIG_PCIE_UNIPHIER=y
CONFIG_PCIE_AL=y
CONFIG_PCIE_FU740=y
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# CONFIG_PCIE_MOBIVEIL_PLAT is not set
# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
CONFIG_PCIE_CADENCE=y
CONFIG_PCIE_CADENCE_HOST=y
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
CONFIG_PCI_J721E=y
CONFIG_PCI_J721E_HOST=y
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=y
# end of PCI switch controller drivers

CONFIG_CXL_BUS=y
CONFIG_CXL_PCI=y
CONFIG_CXL_MEM_RAW_COMMANDS=y
# CONFIG_CXL_MEM is not set
CONFIG_CXL_PORT=y
CONFIG_PCCARD=y
# CONFIG_PCMCIA is not set
CONFIG_CARDBUS=y

#
# PC-card bridges
#
CONFIG_YENTA=y
# CONFIG_YENTA_O2 is not set
CONFIG_YENTA_RICOH=y
# CONFIG_YENTA_TI is not set
# CONFIG_YENTA_TOSHIBA is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
CONFIG_DEVTMPFS_SAFE=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_UPLOAD=y
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_DEBUG_DRIVER=y
CONFIG_DEBUG_DEVRES=y
CONFIG_DEBUG_TEST_DRIVER_REMOVE=y
CONFIG_PM_QOS_KUNIT_TEST=y
CONFIG_DRIVER_PE_KUNIT_TEST=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_AC97=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SLIMBUS=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_W1=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SOUNDWIRE=y
CONFIG_REGMAP_I3C=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
# end of Generic Driver Options

#
# Bus devices
#
# CONFIG_ARM_INTEGRATOR_LM is not set
# CONFIG_BT1_APB is not set
CONFIG_BT1_AXI=y
CONFIG_HISILICON_LPC=y
# CONFIG_INTEL_IXP4XX_EB is not set
CONFIG_QCOM_EBI2=y
# CONFIG_MHI_BUS is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

CONFIG_CONNECTOR=y
# CONFIG_PROC_EVENTS is not set

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_MSG=y
# CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y
# CONFIG_ARM_SCMI_POWER_DOMAIN is not set
CONFIG_ARM_SCMI_POWER_CONTROL=y
# end of ARM System Control and Management Interface Protocol

# CONFIG_ARM_SCPI_PROTOCOL is not set
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_MTK_ADSP_IPC=y
CONFIG_QCOM_SCM=y
CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT=y
CONFIG_SYSFB=y
CONFIG_SYSFB_SIMPLEFB=y
CONFIG_TURRIS_MOX_RWTM=y
# CONFIG_BCM47XX_NVRAM is not set
CONFIG_GOOGLE_FIRMWARE=y
# CONFIG_GOOGLE_COREBOOT_TABLE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
CONFIG_EFI_CAPSULE_LOADER=y
CONFIG_EFI_TEST=y
CONFIG_RESET_ATTACK_MITIGATION=y
# CONFIG_EFI_RCI2_TABLE is not set
CONFIG_EFI_DISABLE_PCI_DMA=y
CONFIG_EFI_DISABLE_RUNTIME=y
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_IMX_DSP=y
CONFIG_IMX_SCU=y
# CONFIG_IMX_SCU_PD is not set

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=y
CONFIG_GNSS_USB=y
CONFIG_MTD=y

#
# Partition parsers
#
CONFIG_MTD_AR7_PARTS=y
CONFIG_MTD_BCM63XX_PARTS=y
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_OF_PARTS_BCM4908 is not set
CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
CONFIG_MTD_PARSER_IMAGETAG=y
CONFIG_MTD_PARSER_TRX=y
CONFIG_MTD_SHARPSL_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
# CONFIG_MTD_OOPS is not set
CONFIG_MTD_PARTITIONED_MASTER=y

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_MTD_ABSENT=y
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_COMPAT=y
CONFIG_MTD_PHYSMAP_START=0x8000000
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_PHYSMAP_OF is not set
CONFIG_MTD_SC520CDP=y
CONFIG_MTD_NETSC520=y
CONFIG_MTD_TS5500=y
CONFIG_MTD_INTEL_VR_NOR=y
CONFIG_MTD_PLATRAM=y
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
CONFIG_MTD_SPEAR_SMI=y
CONFIG_MTD_SLRAM=y
CONFIG_MTD_PHRAM=y
CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_MXIC=y
# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
CONFIG_MTD_LPDDR=y
CONFIG_MTD_QINFO_PROBE=y
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_GLUEBI=y
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
CONFIG_OF_UNITTEST=y
# CONFIG_OF_ALL_DTBS is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_DMA_DEFAULT_COHERENT=y
CONFIG_PARPORT=y
# CONFIG_PARPORT_PC is not set
# CONFIG_PARPORT_AX88796 is not set
# CONFIG_PARPORT_1284 is not set

#
# NVME Support
#
# end of NVME Support

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=y
CONFIG_AD525X_DPOT=y
CONFIG_AD525X_DPOT_I2C=y
# CONFIG_DUMMY_IRQ is not set
CONFIG_PHANTOM=y
CONFIG_TIFM_CORE=y
CONFIG_TIFM_7XX1=y
CONFIG_ICS932S401=y
# CONFIG_ATMEL_SSC is not set
CONFIG_ENCLOSURE_SERVICES=y
CONFIG_HI6421V600_IRQ=y
# CONFIG_HP_ILO is not set
CONFIG_QCOM_COINCELL=y
# CONFIG_QCOM_FASTRPC is not set
CONFIG_APDS9802ALS=y
CONFIG_ISL29003=y
# CONFIG_ISL29020 is not set
CONFIG_SENSORS_TSL2550=y
CONFIG_SENSORS_BH1770=y
CONFIG_SENSORS_APDS990X=y
CONFIG_HMC6352=y
CONFIG_DS1682=y
# CONFIG_PCH_PHUB is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
CONFIG_PCI_ENDPOINT_TEST=y
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=y
CONFIG_HISI_HIKEY_USB=y
CONFIG_OPEN_DICE=y
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_LEGACY=y
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=y
# CONFIG_EEPROM_IDT_89HPESX is not set
CONFIG_EEPROM_EE1004=y
# end of EEPROM support

CONFIG_CB710_CORE=y
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# end of Texas Instruments shared transport line discipline

CONFIG_SENSORS_LIS3_I2C=y
CONFIG_ALTERA_STAPL=y
CONFIG_GENWQE=y
CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0
CONFIG_ECHO=y
CONFIG_BCM_VK=y
CONFIG_MISC_ALCOR_PCI=y
CONFIG_MISC_RTSX_PCI=y
CONFIG_MISC_RTSX_USB=y
CONFIG_HABANA_AI=y
# CONFIG_UACCE is not set
CONFIG_PVPANIC=y
CONFIG_PVPANIC_MMIO=y
# CONFIG_PVPANIC_PCI is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# end of SCSI device support

# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
CONFIG_FIREWIRE_NOSY=y
# end of IEEE 1394 (FireWire) support

# CONFIG_NETDEVICES is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_VIVALDIFMAP=y

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
CONFIG_MOUSE_SERIAL=y
CONFIG_MOUSE_APPLETOUCH=y
# CONFIG_MOUSE_BCM5974 is not set
CONFIG_MOUSE_CYAPA=y
CONFIG_MOUSE_ELAN_I2C=y
# CONFIG_MOUSE_ELAN_I2C_I2C is not set
# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set
CONFIG_MOUSE_VSXXXAA=y
CONFIG_MOUSE_GPIO=y
CONFIG_MOUSE_SYNAPTICS_I2C=y
# CONFIG_MOUSE_SYNAPTICS_USB is not set
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADC is not set
CONFIG_JOYSTICK_ADI=y
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
CONFIG_JOYSTICK_GRIP_MP=y
CONFIG_JOYSTICK_GUILLEMOT=y
CONFIG_JOYSTICK_INTERACT=y
CONFIG_JOYSTICK_SIDEWINDER=y
# CONFIG_JOYSTICK_TMDC is not set
CONFIG_JOYSTICK_IFORCE=y
# CONFIG_JOYSTICK_IFORCE_USB is not set
CONFIG_JOYSTICK_IFORCE_232=y
# CONFIG_JOYSTICK_WARRIOR is not set
CONFIG_JOYSTICK_MAGELLAN=y
CONFIG_JOYSTICK_SPACEORB=y
CONFIG_JOYSTICK_SPACEBALL=y
CONFIG_JOYSTICK_STINGER=y
CONFIG_JOYSTICK_TWIDJOY=y
# CONFIG_JOYSTICK_ZHENHUA is not set
CONFIG_JOYSTICK_DB9=y
# CONFIG_JOYSTICK_GAMECON is not set
CONFIG_JOYSTICK_TURBOGRAFX=y
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
# CONFIG_JOYSTICK_XPAD is not set
CONFIG_JOYSTICK_WALKERA0701=y
CONFIG_JOYSTICK_PXRC=y
# CONFIG_JOYSTICK_QWIIC is not set
CONFIG_JOYSTICK_FSIA6B=y
# CONFIG_JOYSTICK_SENSEHAT is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_AD7879 is not set
CONFIG_TOUCHSCREEN_ADC=y
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
CONFIG_TOUCHSCREEN_AUO_PIXCIR=y
# CONFIG_TOUCHSCREEN_BU21013 is not set
CONFIG_TOUCHSCREEN_BU21029=y
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=y
CONFIG_TOUCHSCREEN_CY8CTMA140=y
CONFIG_TOUCHSCREEN_CY8CTMG110=y
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=y
# CONFIG_TOUCHSCREEN_CYTTSP4_I2C is not set
CONFIG_TOUCHSCREEN_DA9034=y
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
CONFIG_TOUCHSCREEN_HAMPSHIRE=y
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=y
# CONFIG_TOUCHSCREEN_EXC3000 is not set
CONFIG_TOUCHSCREEN_FUJITSU=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_TOUCHSCREEN_HIDEEP=y
CONFIG_TOUCHSCREEN_HYCON_HY46XX=y
CONFIG_TOUCHSCREEN_ILI210X=y
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_IPROC is not set
CONFIG_TOUCHSCREEN_S6SY761=y
# CONFIG_TOUCHSCREEN_GUNZE is not set
CONFIG_TOUCHSCREEN_EKTF2127=y
# CONFIG_TOUCHSCREEN_ELAN is not set
CONFIG_TOUCHSCREEN_ELO=y
CONFIG_TOUCHSCREEN_WACOM_W8001=y
CONFIG_TOUCHSCREEN_WACOM_I2C=y
CONFIG_TOUCHSCREEN_MAX11801=y
# CONFIG_TOUCHSCREEN_MCS5000 is not set
CONFIG_TOUCHSCREEN_MMS114=y
CONFIG_TOUCHSCREEN_MELFAS_MIP4=y
CONFIG_TOUCHSCREEN_MSG2638=y
CONFIG_TOUCHSCREEN_MTOUCH=y
CONFIG_TOUCHSCREEN_IMAGIS=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_INEXIO=y
CONFIG_TOUCHSCREEN_MK712=y
CONFIG_TOUCHSCREEN_PENMOUNT=y
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=y
CONFIG_TOUCHSCREEN_MIGOR=y
CONFIG_TOUCHSCREEN_TOUCHRIGHT=y
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
CONFIG_TOUCHSCREEN_UCB1400=y
CONFIG_TOUCHSCREEN_PIXCIR=y
CONFIG_TOUCHSCREEN_WDT87XX_I2C=y
CONFIG_TOUCHSCREEN_WM831X=y
CONFIG_TOUCHSCREEN_WM97XX=y
# CONFIG_TOUCHSCREEN_WM9705 is not set
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_MXS_LRADC is not set
CONFIG_TOUCHSCREEN_MX25=y
CONFIG_TOUCHSCREEN_MC13783=y
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
CONFIG_TOUCHSCREEN_TS4800=y
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
CONFIG_TOUCHSCREEN_TSC200X_CORE=y
CONFIG_TOUCHSCREEN_TSC2004=y
CONFIG_TOUCHSCREEN_TSC2007=y
# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
CONFIG_TOUCHSCREEN_RM_TS=y
# CONFIG_TOUCHSCREEN_SILEAD is not set
CONFIG_TOUCHSCREEN_SIS_I2C=y
# CONFIG_TOUCHSCREEN_ST1232 is not set
CONFIG_TOUCHSCREEN_STMFTS=y
# CONFIG_TOUCHSCREEN_SUN4I is not set
CONFIG_TOUCHSCREEN_SX8654=y
CONFIG_TOUCHSCREEN_TPS6507X=y
CONFIG_TOUCHSCREEN_ZET6223=y
# CONFIG_TOUCHSCREEN_ZFORCE is not set
CONFIG_TOUCHSCREEN_ROHM_BU21023=y
# CONFIG_TOUCHSCREEN_IQS5XX is not set
CONFIG_TOUCHSCREEN_ZINITIX=y
# CONFIG_INPUT_MISC is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
# CONFIG_RMI4_F3A is not set
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_PARKBD is not set
CONFIG_SERIO_PCIPS2=y
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_RAW is not set
CONFIG_SERIO_ALTERA_PS2=y
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
CONFIG_SERIO_APBPS2=y
CONFIG_SERIO_OLPC_APSP=y
# CONFIG_SERIO_SUN4I_PS2 is not set
CONFIG_SERIO_GPIO_PS2=y
CONFIG_USERIO=y
CONFIG_GAMEPORT=y
CONFIG_GAMEPORT_NS558=y
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
# CONFIG_TTY is not set
# CONFIG_SERIAL_DEV_BUS is not set
CONFIG_PRINTER=y
# CONFIG_LP_CONSOLE is not set
CONFIG_PPDEV=y
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_PLAT_DATA=y
CONFIG_IPMI_PANIC_EVENT=y
CONFIG_IPMI_PANIC_STRING=y
# CONFIG_IPMI_DEVICE_INTERFACE is not set
CONFIG_IPMI_SI=y
CONFIG_IPMI_SSIF=y
# CONFIG_IPMI_IPMB is not set
CONFIG_IPMI_WATCHDOG=y
# CONFIG_IPMI_POWEROFF is not set
CONFIG_IPMI_KCS_BMC=y
CONFIG_ASPEED_KCS_IPMI_BMC=y
CONFIG_NPCM7XX_KCS_IPMI_BMC=y
CONFIG_IPMI_KCS_BMC_CDEV_IPMI=y
CONFIG_IPMI_KCS_BMC_SERIO=y
# CONFIG_ASPEED_BT_IPMI_BMC is not set
CONFIG_IPMB_DEVICE_INTERFACE=y
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
CONFIG_HW_RANDOM_ATMEL=y
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_BCM2835=y
CONFIG_HW_RANDOM_IPROC_RNG200=y
CONFIG_HW_RANDOM_IXP4XX=y
CONFIG_HW_RANDOM_OMAP=y
CONFIG_HW_RANDOM_OMAP3_ROM=y
# CONFIG_HW_RANDOM_VIRTIO is not set
CONFIG_HW_RANDOM_IMX_RNGC=y
CONFIG_HW_RANDOM_NOMADIK=y
CONFIG_HW_RANDOM_STM32=y
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_MTK=y
# CONFIG_HW_RANDOM_EXYNOS is not set
CONFIG_HW_RANDOM_NPCM=y
# CONFIG_HW_RANDOM_KEYSTONE is not set
CONFIG_HW_RANDOM_CCTRNG=y
CONFIG_HW_RANDOM_XIPHERA=y
CONFIG_HW_RANDOM_CN10K=y
CONFIG_APPLICOM=y
# CONFIG_DEVMEM is not set
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
CONFIG_XILLYBUS_CLASS=y
CONFIG_XILLYBUS=y
# CONFIG_XILLYBUS_PCIE is not set
CONFIG_XILLYBUS_OF=y
CONFIG_XILLYUSB=y
CONFIG_RANDOM_TRUST_CPU=y
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
# CONFIG_I2C_MUX_GPMUX is not set
CONFIG_I2C_MUX_LTC4306=y
CONFIG_I2C_MUX_PCA9541=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
# CONFIG_I2C_DEMUX_PINCTRL is not set
CONFIG_I2C_MUX_MLXCPLD=y
# end of Multiplexer I2C Chip support

# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_SMBUS=y

#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
CONFIG_I2C_ALGOPCA=y
# end of I2C Algorithms

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=y
CONFIG_I2C_ALI1535=y
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
CONFIG_I2C_AMD8111=y
CONFIG_I2C_HIX5HD2=y
CONFIG_I2C_I801=y
CONFIG_I2C_ISCH=y
CONFIG_I2C_PIIX4=y
CONFIG_I2C_NFORCE2=y
CONFIG_I2C_NVIDIA_GPU=y
# CONFIG_I2C_SIS5595 is not set
CONFIG_I2C_SIS630=y
CONFIG_I2C_SIS96X=y
CONFIG_I2C_VIA=y
CONFIG_I2C_VIAPRO=y

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_ALTERA=y
# CONFIG_I2C_ASPEED is not set
CONFIG_I2C_AT91=y
# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
CONFIG_I2C_AXXIA=y
CONFIG_I2C_BCM2835=y
# CONFIG_I2C_BCM_IPROC is not set
CONFIG_I2C_BCM_KONA=y
# CONFIG_I2C_BRCMSTB is not set
CONFIG_I2C_CADENCE=y
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DAVINCI=y
CONFIG_I2C_DESIGNWARE_CORE=y
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=y
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_DIGICOLOR is not set
# CONFIG_I2C_EG20T is not set
# CONFIG_I2C_EMEV2 is not set
# CONFIG_I2C_EXYNOS5 is not set
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_HIGHLANDER=y
CONFIG_I2C_HISI=y
CONFIG_I2C_IMG=y
# CONFIG_I2C_IMX is not set
CONFIG_I2C_IMX_LPI2C=y
CONFIG_I2C_IOP3XX=y
# CONFIG_I2C_JZ4780 is not set
CONFIG_I2C_KEMPLD=y
CONFIG_I2C_LPC2K=y
CONFIG_I2C_MESON=y
CONFIG_I2C_MICROCHIP_CORE=y
CONFIG_I2C_MT65XX=y
# CONFIG_I2C_MT7621 is not set
# CONFIG_I2C_MV64XXX is not set
# CONFIG_I2C_MXS is not set
# CONFIG_I2C_NPCM is not set
CONFIG_I2C_OCORES=y
CONFIG_I2C_OMAP=y
CONFIG_I2C_OWL=y
CONFIG_I2C_APPLE=y
CONFIG_I2C_PCA_PLATFORM=y
CONFIG_I2C_PNX=y
CONFIG_I2C_PXA=y
CONFIG_I2C_PXA_SLAVE=y
CONFIG_I2C_QCOM_CCI=y
CONFIG_I2C_QUP=y
CONFIG_I2C_RIIC=y
CONFIG_I2C_RK3X=y
CONFIG_I2C_RZV2M=y
# CONFIG_I2C_S3C2410 is not set
CONFIG_I2C_SH_MOBILE=y
# CONFIG_I2C_SIMTEC is not set
CONFIG_I2C_SPRD=y
CONFIG_I2C_ST=y
CONFIG_I2C_STM32F4=y
CONFIG_I2C_STM32F7=y
# CONFIG_I2C_SUN6I_P2WI is not set
CONFIG_I2C_SYNQUACER=y
CONFIG_I2C_TEGRA=y
# CONFIG_I2C_TEGRA_BPMP is not set
# CONFIG_I2C_UNIPHIER is not set
CONFIG_I2C_UNIPHIER_F=y
# CONFIG_I2C_VERSATILE is not set
CONFIG_I2C_WMT=y
CONFIG_I2C_THUNDERX=y
CONFIG_I2C_XILINX=y
# CONFIG_I2C_XLP9XX is not set
# CONFIG_I2C_RCAR is not set

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=y
# CONFIG_I2C_DLN2 is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PARPORT is not set
CONFIG_I2C_ROBOTFUZZ_OSIF=y
# CONFIG_I2C_TINY_USB is not set
CONFIG_I2C_VIPERBOARD=y

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
CONFIG_I2C_CROS_EC_TUNNEL=y
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support

CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=y
CONFIG_I2C_SLAVE_TESTUNIT=y
CONFIG_I2C_DEBUG_CORE=y
# CONFIG_I2C_DEBUG_ALGO is not set
CONFIG_I2C_DEBUG_BUS=y
# end of I2C support

CONFIG_I3C=y
# CONFIG_CDNS_I3C_MASTER is not set
CONFIG_DW_I3C_MASTER=y
CONFIG_SVC_I3C_MASTER=y
CONFIG_MIPI_I3C_HCI=y
# CONFIG_SPI is not set
CONFIG_SPMI=y
CONFIG_SPMI_HISI3670=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_SPMI_MTK_PMIF=y
CONFIG_HSI=y
CONFIG_HSI_BOARDINFO=y

#
# HSI controllers
#

#
# HSI clients
#
CONFIG_HSI_CHAR=y
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
CONFIG_PPS_CLIENT_PARPORT=y
# CONFIG_PPS_CLIENT_GPIO is not set

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PTP_1588_CLOCK_DTE=y
CONFIG_PTP_1588_CLOCK_QORIQ=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_PCH=y
CONFIG_PTP_1588_CLOCK_IDT82P33=y
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AMD=y
CONFIG_PINCTRL_AS3722=y
# CONFIG_PINCTRL_AT91PIO4 is not set
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_BM1880 is not set
CONFIG_PINCTRL_DA850_PUPD=y
CONFIG_PINCTRL_DA9062=y
CONFIG_PINCTRL_EQUILIBRIUM=y
# CONFIG_PINCTRL_INGENIC is not set
# CONFIG_PINCTRL_LPC18XX is not set
CONFIG_PINCTRL_MCP23S08_I2C=y
CONFIG_PINCTRL_MCP23S08=y
CONFIG_PINCTRL_MICROCHIP_SGPIO=y
# CONFIG_PINCTRL_OCELOT is not set
# CONFIG_PINCTRL_PISTACHIO is not set
# CONFIG_PINCTRL_ROCKCHIP is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=y
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_OWL=y
# CONFIG_PINCTRL_S500 is not set
CONFIG_PINCTRL_S700=y
# CONFIG_PINCTRL_S900 is not set
CONFIG_PINCTRL_ASPEED=y
# CONFIG_PINCTRL_ASPEED_G4 is not set
CONFIG_PINCTRL_ASPEED_G5=y
# CONFIG_PINCTRL_ASPEED_G6 is not set
# CONFIG_PINCTRL_BCM281XX is not set
# CONFIG_PINCTRL_BCM2835 is not set
# CONFIG_PINCTRL_BCM4908 is not set
CONFIG_PINCTRL_BCM63XX=y
CONFIG_PINCTRL_BCM6318=y
CONFIG_PINCTRL_BCM6328=y
CONFIG_PINCTRL_BCM6358=y
# CONFIG_PINCTRL_BCM6362 is not set
# CONFIG_PINCTRL_BCM6368 is not set
CONFIG_PINCTRL_BCM63268=y
# CONFIG_PINCTRL_IPROC_GPIO is not set
CONFIG_PINCTRL_CYGNUS_MUX=y
# CONFIG_PINCTRL_NS is not set
CONFIG_PINCTRL_NSP_GPIO=y
# CONFIG_PINCTRL_NS2_MUX is not set
# CONFIG_PINCTRL_NSP_MUX is not set
CONFIG_PINCTRL_BERLIN=y
CONFIG_PINCTRL_AS370=y
CONFIG_PINCTRL_BERLIN_BG4CT=y
CONFIG_PINCTRL_MADERA=y
CONFIG_PINCTRL_CS47L90=y

#
# Intel pinctrl drivers
#
# end of Intel pinctrl drivers

#
# MediaTek pinctrl drivers
#
CONFIG_EINT_MTK=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_PARIS=y
CONFIG_PINCTRL_MT2701=y
CONFIG_PINCTRL_MT7623=y
CONFIG_PINCTRL_MT7629=y
# CONFIG_PINCTRL_MT8135 is not set
CONFIG_PINCTRL_MT8127=y
# CONFIG_PINCTRL_MT2712 is not set
# CONFIG_PINCTRL_MT6765 is not set
# CONFIG_PINCTRL_MT6779 is not set
# CONFIG_PINCTRL_MT6795 is not set
CONFIG_PINCTRL_MT6797=y
CONFIG_PINCTRL_MT7622=y
# CONFIG_PINCTRL_MT7986 is not set
# CONFIG_PINCTRL_MT8167 is not set
CONFIG_PINCTRL_MT8173=y
CONFIG_PINCTRL_MT8183=y
CONFIG_PINCTRL_MT8186=y
# CONFIG_PINCTRL_MT8192 is not set
CONFIG_PINCTRL_MT8195=y
# CONFIG_PINCTRL_MT8365 is not set
# CONFIG_PINCTRL_MT8516 is not set
# CONFIG_PINCTRL_MT6397 is not set
# end of MediaTek pinctrl drivers

CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_WPCM450=y
CONFIG_PINCTRL_NPCM7XX=y
CONFIG_PINCTRL_PXA=y
CONFIG_PINCTRL_PXA25X=y
# CONFIG_PINCTRL_PXA27X is not set
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_APQ8064=y
CONFIG_PINCTRL_APQ8084=y
CONFIG_PINCTRL_IPQ4019=y
CONFIG_PINCTRL_IPQ8064=y
CONFIG_PINCTRL_IPQ8074=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PINCTRL_MSM8226=y
# CONFIG_PINCTRL_MSM8660 is not set
CONFIG_PINCTRL_MSM8960=y
CONFIG_PINCTRL_MDM9607=y
CONFIG_PINCTRL_MDM9615=y
# CONFIG_PINCTRL_MSM8X74 is not set
CONFIG_PINCTRL_MSM8909=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8953=y
CONFIG_PINCTRL_MSM8976=y
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
CONFIG_PINCTRL_MSM8998=y
CONFIG_PINCTRL_QCM2290=y
CONFIG_PINCTRL_QCS404=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_SC7180 is not set
CONFIG_PINCTRL_SC7280=y
# CONFIG_PINCTRL_SC7280_LPASS_LPI is not set
CONFIG_PINCTRL_SC8180X=y
CONFIG_PINCTRL_SC8280XP=y
# CONFIG_PINCTRL_SDM660 is not set
CONFIG_PINCTRL_SDM845=y
# CONFIG_PINCTRL_SDX55 is not set
CONFIG_PINCTRL_SM6115=y
CONFIG_PINCTRL_SM6125=y
CONFIG_PINCTRL_SM6350=y
CONFIG_PINCTRL_SM6375=y
CONFIG_PINCTRL_SDX65=y
CONFIG_PINCTRL_SM8150=y
# CONFIG_PINCTRL_SM8250 is not set
# CONFIG_PINCTRL_SM8250_LPASS_LPI is not set
# CONFIG_PINCTRL_SM8350 is not set
CONFIG_PINCTRL_SM8450=y
CONFIG_PINCTRL_LPASS_LPI=y

#
# Renesas pinctrl drivers
#
CONFIG_PINCTRL_RENESAS=y
CONFIG_PINCTRL_SH_PFC=y
CONFIG_PINCTRL_SH_PFC_GPIO=y
CONFIG_PINCTRL_SH_FUNC_GPIO=y
CONFIG_PINCTRL_PFC_EMEV2=y
CONFIG_PINCTRL_PFC_R8A77995=y
CONFIG_PINCTRL_PFC_R8A7794=y
CONFIG_PINCTRL_PFC_R8A77990=y
CONFIG_PINCTRL_PFC_R8A7779=y
# CONFIG_PINCTRL_PFC_R8A7790 is not set
CONFIG_PINCTRL_PFC_R8A77950=y
# CONFIG_PINCTRL_PFC_R8A77951 is not set
CONFIG_PINCTRL_PFC_R8A7778=y
CONFIG_PINCTRL_PFC_R8A7793=y
CONFIG_PINCTRL_PFC_R8A7791=y
# CONFIG_PINCTRL_PFC_R8A77965 is not set
CONFIG_PINCTRL_PFC_R8A77960=y
# CONFIG_PINCTRL_PFC_R8A77961 is not set
# CONFIG_PINCTRL_PFC_R8A779F0 is not set
CONFIG_PINCTRL_PFC_R8A7792=y
# CONFIG_PINCTRL_PFC_R8A77980 is not set
CONFIG_PINCTRL_PFC_R8A77970=y
CONFIG_PINCTRL_PFC_R8A779A0=y
# CONFIG_PINCTRL_PFC_R8A779G0 is not set
# CONFIG_PINCTRL_PFC_R8A7740 is not set
# CONFIG_PINCTRL_PFC_R8A73A4 is not set
CONFIG_PINCTRL_RZA1=y
# CONFIG_PINCTRL_RZA2 is not set
CONFIG_PINCTRL_RZG2L=y
CONFIG_PINCTRL_PFC_R8A77470=y
# CONFIG_PINCTRL_PFC_R8A7745 is not set
# CONFIG_PINCTRL_PFC_R8A7742 is not set
# CONFIG_PINCTRL_PFC_R8A7743 is not set
# CONFIG_PINCTRL_PFC_R8A7744 is not set
# CONFIG_PINCTRL_PFC_R8A774C0 is not set
CONFIG_PINCTRL_PFC_R8A774E1=y
# CONFIG_PINCTRL_PFC_R8A774A1 is not set
CONFIG_PINCTRL_PFC_R8A774B1=y
# CONFIG_PINCTRL_RZN1 is not set
# CONFIG_PINCTRL_RZV2M is not set
CONFIG_PINCTRL_PFC_SH7203=y
CONFIG_PINCTRL_PFC_SH7264=y
# CONFIG_PINCTRL_PFC_SH7269 is not set
CONFIG_PINCTRL_PFC_SH7720=y
CONFIG_PINCTRL_PFC_SH7722=y
# CONFIG_PINCTRL_PFC_SH7734 is not set
CONFIG_PINCTRL_PFC_SH7757=y
# CONFIG_PINCTRL_PFC_SH7785 is not set
CONFIG_PINCTRL_PFC_SH7786=y
# CONFIG_PINCTRL_PFC_SH73A0 is not set
CONFIG_PINCTRL_PFC_SH7723=y
CONFIG_PINCTRL_PFC_SH7724=y
CONFIG_PINCTRL_PFC_SHX3=y
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SAMSUNG=y
CONFIG_PINCTRL_EXYNOS=y
CONFIG_PINCTRL_EXYNOS_ARM=y
# CONFIG_PINCTRL_EXYNOS_ARM64 is not set
CONFIG_PINCTRL_S3C24XX=y
CONFIG_PINCTRL_S3C64XX=y
CONFIG_PINCTRL_SPRD=y
CONFIG_PINCTRL_SPRD_SC9860=y
CONFIG_PINCTRL_STARFIVE_JH7100=y
CONFIG_PINCTRL_STARFIVE=y
CONFIG_PINCTRL_STARFIVE_JH7110=y
CONFIG_PINCTRL_STM32=y
CONFIG_PINCTRL_STM32F429=y
CONFIG_PINCTRL_STM32F469=y
CONFIG_PINCTRL_STM32F746=y
# CONFIG_PINCTRL_STM32F769 is not set
CONFIG_PINCTRL_STM32H743=y
CONFIG_PINCTRL_STM32MP135=y
# CONFIG_PINCTRL_STM32MP157 is not set
CONFIG_PINCTRL_TI_IODELAY=y
# CONFIG_PINCTRL_UNIPHIER is not set
# CONFIG_PINCTRL_TMPV7700 is not set
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
# CONFIG_GPIO_CDEV_V1 is not set
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_REGMAP=y
CONFIG_GPIO_MAX730X=y

#
# Memory mapped GPIO drivers
#
CONFIG_GPIO_74XX_MMIO=y
CONFIG_GPIO_ALTERA=y
CONFIG_GPIO_ASPEED=y
# CONFIG_GPIO_ASPEED_SGPIO is not set
# CONFIG_GPIO_ATH79 is not set
# CONFIG_GPIO_RASPBERRYPI_EXP is not set
# CONFIG_GPIO_BCM_KONA is not set
CONFIG_GPIO_BCM_XGS_IPROC=y
# CONFIG_GPIO_BRCMSTB is not set
CONFIG_GPIO_CADENCE=y
CONFIG_GPIO_CLPS711X=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_EIC_SPRD=y
CONFIG_GPIO_EM=y
# CONFIG_GPIO_FTGPIO010 is not set
# CONFIG_GPIO_GENERIC_PLATFORM is not set
CONFIG_GPIO_GRGPIO=y
# CONFIG_GPIO_HISI is not set
CONFIG_GPIO_HLWD=y
CONFIG_GPIO_IOP=y
# CONFIG_GPIO_LOGICVC is not set
CONFIG_GPIO_LPC18XX=y
# CONFIG_GPIO_LPC32XX is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_MENZ127=y
CONFIG_GPIO_MPC8XXX=y
# CONFIG_GPIO_MT7621 is not set
CONFIG_GPIO_MXC=y
CONFIG_GPIO_MXS=y
# CONFIG_GPIO_PMIC_EIC_SPRD is not set
# CONFIG_GPIO_PXA is not set
CONFIG_GPIO_RCAR=y
# CONFIG_GPIO_RDA is not set
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SIOX=y
# CONFIG_GPIO_SNPS_CREG is not set
CONFIG_GPIO_SPRD=y
# CONFIG_GPIO_STP_XWAY is not set
# CONFIG_GPIO_SYSCON is not set
CONFIG_GPIO_TEGRA=y
# CONFIG_GPIO_TEGRA186 is not set
CONFIG_GPIO_TS4800=y
CONFIG_GPIO_THUNDERX=y
# CONFIG_GPIO_UNIPHIER is not set
# CONFIG_GPIO_VISCONTI is not set
CONFIG_GPIO_VX855=y
# CONFIG_GPIO_WCD934X is not set
# CONFIG_GPIO_XGENE_SB is not set
CONFIG_GPIO_XILINX=y
CONFIG_GPIO_XLP=y
CONFIG_GPIO_AMD_FCH=y
CONFIG_GPIO_IDT3243X=y
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADP5588 is not set
# CONFIG_GPIO_ADNP is not set
CONFIG_GPIO_GW_PLD=y
CONFIG_GPIO_MAX7300=y
# CONFIG_GPIO_MAX732X is not set
CONFIG_GPIO_PCA953X=y
# CONFIG_GPIO_PCA953X_IRQ is not set
CONFIG_GPIO_PCA9570=y
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
CONFIG_GPIO_TS4900=y
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
CONFIG_GPIO_ADP5520=y
# CONFIG_GPIO_ARIZONA is not set
CONFIG_GPIO_BD71815=y
CONFIG_GPIO_BD71828=y
# CONFIG_GPIO_BD9571MWV is not set
# CONFIG_GPIO_DLN2 is not set
CONFIG_GPIO_JANZ_TTL=y
CONFIG_GPIO_KEMPLD=y
CONFIG_GPIO_LP3943=y
CONFIG_GPIO_LP87565=y
CONFIG_GPIO_MADERA=y
# CONFIG_GPIO_RC5T583 is not set
CONFIG_GPIO_SL28CPLD=y
CONFIG_GPIO_TC3589X=y
# CONFIG_GPIO_TIMBERDALE is not set
CONFIG_GPIO_TPS65086=y
CONFIG_GPIO_TPS65218=y
# CONFIG_GPIO_TPS6586X is not set
CONFIG_GPIO_TPS65912=y
CONFIG_GPIO_TQMX86=y
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_UCB1400=y
# CONFIG_GPIO_WM831X is not set
# CONFIG_GPIO_WM8994 is not set
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
CONFIG_GPIO_AMD8111=y
CONFIG_GPIO_BT8XX=y
CONFIG_GPIO_MLXBF=y
CONFIG_GPIO_MLXBF2=y
CONFIG_GPIO_ML_IOH=y
CONFIG_GPIO_PCH=y
# CONFIG_GPIO_PCI_IDIO_16 is not set
CONFIG_GPIO_PCIE_IDIO_24=y
CONFIG_GPIO_RDC321X=y
# end of PCI GPIO expanders

#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=y
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
CONFIG_GPIO_VIRTIO=y
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

CONFIG_W1=y
# CONFIG_W1_CON is not set

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=y
CONFIG_W1_MASTER_DS2490=y
CONFIG_W1_MASTER_DS2482=y
CONFIG_W1_MASTER_MXC=y
# CONFIG_W1_MASTER_DS1WM is not set
# CONFIG_W1_MASTER_GPIO is not set
CONFIG_W1_MASTER_SGI=y
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
# CONFIG_W1_SLAVE_THERM is not set
# CONFIG_W1_SLAVE_SMEM is not set
CONFIG_W1_SLAVE_DS2405=y
CONFIG_W1_SLAVE_DS2408=y
# CONFIG_W1_SLAVE_DS2408_READBACK is not set
# CONFIG_W1_SLAVE_DS2413 is not set
CONFIG_W1_SLAVE_DS2406=y
CONFIG_W1_SLAVE_DS2423=y
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
# CONFIG_W1_SLAVE_DS2431 is not set
CONFIG_W1_SLAVE_DS2433=y
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=y
CONFIG_W1_SLAVE_DS250X=y
CONFIG_W1_SLAVE_DS2780=y
CONFIG_W1_SLAVE_DS2781=y
CONFIG_W1_SLAVE_DS28E04=y
# CONFIG_W1_SLAVE_DS28E17 is not set
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_AS3722=y
# CONFIG_POWER_RESET_BRCMKONA is not set
CONFIG_POWER_RESET_BRCMSTB=y
# CONFIG_POWER_RESET_GEMINI_POWEROFF is not set
# CONFIG_POWER_RESET_GPIO is not set
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_OCELOT_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
# CONFIG_POWER_RESET_LTC2952 is not set
CONFIG_POWER_RESET_MT6323=y
# CONFIG_POWER_RESET_REGULATOR is not set
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_TPS65086=y
# CONFIG_POWER_RESET_KEYSTONE is not set
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
# CONFIG_POWER_RESET_RMOBILE is not set
CONFIG_REBOOT_MODE=y
# CONFIG_SYSCON_REBOOT_MODE is not set
# CONFIG_POWER_RESET_SC27XX is not set
CONFIG_NVMEM_REBOOT_MODE=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
# CONFIG_POWER_SUPPLY_HWMON is not set
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
CONFIG_IP5XXX_POWER=y
CONFIG_WM831X_BACKUP=y
CONFIG_WM831X_POWER=y
CONFIG_TEST_POWER=y
# CONFIG_CHARGER_ADP5061 is not set
CONFIG_BATTERY_ACT8945A=y
# CONFIG_BATTERY_CW2015 is not set
CONFIG_BATTERY_DS2760=y
CONFIG_BATTERY_DS2780=y
CONFIG_BATTERY_DS2781=y
CONFIG_BATTERY_DS2782=y
# CONFIG_BATTERY_LEGO_EV3 is not set
CONFIG_BATTERY_SAMSUNG_SDI=y
CONFIG_BATTERY_INGENIC=y
# CONFIG_BATTERY_WM97XX is not set
CONFIG_BATTERY_SBS=y
# CONFIG_CHARGER_SBS is not set
CONFIG_MANAGER_SBS=y
CONFIG_BATTERY_BQ27XXX=y
CONFIG_BATTERY_BQ27XXX_I2C=y
CONFIG_BATTERY_BQ27XXX_HDQ=y
# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
CONFIG_BATTERY_DA9030=y
CONFIG_CHARGER_AXP20X=y
CONFIG_BATTERY_AXP20X=y
# CONFIG_AXP20X_POWER is not set
CONFIG_BATTERY_MAX17040=y
CONFIG_BATTERY_MAX17042=y
CONFIG_BATTERY_MAX1721X=y
CONFIG_BATTERY_TWL4030_MADC=y
CONFIG_CHARGER_PCF50633=y
# CONFIG_BATTERY_RX51 is not set
CONFIG_CHARGER_ISP1704=y
# CONFIG_CHARGER_MAX8903 is not set
CONFIG_CHARGER_TWL4030=y
CONFIG_CHARGER_LP8727=y
CONFIG_CHARGER_GPIO=y
CONFIG_CHARGER_MANAGER=y
CONFIG_CHARGER_LT3651=y
CONFIG_CHARGER_LTC4162L=y
CONFIG_CHARGER_DETECTOR_MAX14656=y
# CONFIG_CHARGER_MAX77976 is not set
CONFIG_CHARGER_MAX8998=y
# CONFIG_CHARGER_MP2629 is not set
CONFIG_CHARGER_MT6360=y
# CONFIG_CHARGER_QCOM_SMBB is not set
# CONFIG_CHARGER_BQ2415X is not set
CONFIG_CHARGER_BQ24190=y
CONFIG_CHARGER_BQ24257=y
CONFIG_CHARGER_BQ24735=y
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
CONFIG_CHARGER_BQ25980=y
CONFIG_CHARGER_BQ256XX=y
CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65090=y
# CONFIG_CHARGER_TPS65217 is not set
CONFIG_BATTERY_GAUGE_LTC2941=y
# CONFIG_BATTERY_GOLDFISH is not set
CONFIG_BATTERY_RT5033=y
# CONFIG_CHARGER_RT9455 is not set
CONFIG_CHARGER_SC2731=y
# CONFIG_FUEL_GAUGE_SC27XX is not set
CONFIG_CHARGER_UCS1002=y
CONFIG_CHARGER_BD99954=y
CONFIG_RN5T618_POWER=y
# CONFIG_BATTERY_ACER_A500 is not set
CONFIG_BATTERY_UG3105=y
CONFIG_HWMON=y
CONFIG_HWMON_VID=y
CONFIG_HWMON_DEBUG_CHIP=y

#
# Native drivers
#
CONFIG_SENSORS_AD7414=y
# CONFIG_SENSORS_AD7418 is not set
CONFIG_SENSORS_ADM1025=y
CONFIG_SENSORS_ADM1026=y
CONFIG_SENSORS_ADM1029=y
CONFIG_SENSORS_ADM1031=y
CONFIG_SENSORS_ADM1177=y
CONFIG_SENSORS_ADM9240=y
CONFIG_SENSORS_ADT7X10=y
CONFIG_SENSORS_ADT7410=y
# CONFIG_SENSORS_ADT7411 is not set
CONFIG_SENSORS_ADT7462=y
CONFIG_SENSORS_ADT7470=y
# CONFIG_SENSORS_ADT7475 is not set
CONFIG_SENSORS_AHT10=y
CONFIG_SENSORS_AS370=y
# CONFIG_SENSORS_ASC7621 is not set
CONFIG_SENSORS_AXI_FAN_CONTROL=y
# CONFIG_SENSORS_ARM_SCMI is not set
CONFIG_SENSORS_ASB100=y
CONFIG_SENSORS_ASPEED=y
CONFIG_SENSORS_ATXP1=y
CONFIG_SENSORS_BT1_PVT=y
# CONFIG_SENSORS_BT1_PVT_ALARMS is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
CONFIG_SENSORS_CORSAIR_PSU=y
# CONFIG_SENSORS_DS620 is not set
CONFIG_SENSORS_DS1621=y
CONFIG_SENSORS_I5K_AMB=y
CONFIG_SENSORS_SPARX5=y
CONFIG_SENSORS_F71805F=y
CONFIG_SENSORS_F71882FG=y
CONFIG_SENSORS_F75375S=y
CONFIG_SENSORS_GSC=y
CONFIG_SENSORS_MC13783_ADC=y
CONFIG_SENSORS_FSCHMD=y
# CONFIG_SENSORS_FTSTEUTATES is not set
CONFIG_SENSORS_GL518SM=y
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
CONFIG_SENSORS_IBMAEM=y
CONFIG_SENSORS_IBMPEX=y
# CONFIG_SENSORS_IIO_HWMON is not set
CONFIG_SENSORS_IT87=y
CONFIG_SENSORS_JC42=y
CONFIG_SENSORS_POWR1220=y
CONFIG_SENSORS_LAN966X=y
CONFIG_SENSORS_LINEAGE=y
CONFIG_SENSORS_LTC2945=y
# CONFIG_SENSORS_LTC2947_I2C is not set
CONFIG_SENSORS_LTC2990=y
# CONFIG_SENSORS_LTC2992 is not set
CONFIG_SENSORS_LTC4151=y
# CONFIG_SENSORS_LTC4215 is not set
CONFIG_SENSORS_LTC4222=y
CONFIG_SENSORS_LTC4245=y
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
CONFIG_SENSORS_MAX127=y
CONFIG_SENSORS_MAX16065=y
# CONFIG_SENSORS_MAX1619 is not set
CONFIG_SENSORS_MAX1668=y
# CONFIG_SENSORS_MAX197 is not set
CONFIG_SENSORS_MAX31730=y
# CONFIG_SENSORS_MAX6620 is not set
CONFIG_SENSORS_MAX6621=y
CONFIG_SENSORS_MAX6639=y
CONFIG_SENSORS_MAX6650=y
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
CONFIG_SENSORS_MCP3021=y
CONFIG_SENSORS_TC654=y
# CONFIG_SENSORS_TPS23861 is not set
CONFIG_SENSORS_MENF21BMC_HWMON=y
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
CONFIG_SENSORS_LM75=y
CONFIG_SENSORS_LM77=y
CONFIG_SENSORS_LM78=y
CONFIG_SENSORS_LM80=y
CONFIG_SENSORS_LM83=y
# CONFIG_SENSORS_LM85 is not set
CONFIG_SENSORS_LM87=y
CONFIG_SENSORS_LM90=y
# CONFIG_SENSORS_LM92 is not set
CONFIG_SENSORS_LM93=y
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
CONFIG_SENSORS_LM95245=y
CONFIG_SENSORS_PC87360=y
CONFIG_SENSORS_PC87427=y
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
CONFIG_SENSORS_NCT6775_CORE=y
# CONFIG_SENSORS_NCT6775 is not set
CONFIG_SENSORS_NCT6775_I2C=y
CONFIG_SENSORS_NCT7802=y
CONFIG_SENSORS_NCT7904=y
CONFIG_SENSORS_NPCM7XX=y
# CONFIG_SENSORS_NSA320 is not set
CONFIG_SENSORS_OCC_P8_I2C=y
CONFIG_SENSORS_OCC=y
# CONFIG_SENSORS_PCF8591 is not set
CONFIG_PMBUS=y
CONFIG_SENSORS_PMBUS=y
# CONFIG_SENSORS_ADM1266 is not set
CONFIG_SENSORS_ADM1275=y
CONFIG_SENSORS_BEL_PFE=y
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
CONFIG_SENSORS_FSP_3Y=y
CONFIG_SENSORS_IBM_CFFPS=y
CONFIG_SENSORS_DPS920AB=y
CONFIG_SENSORS_INSPUR_IPSPS=y
CONFIG_SENSORS_IR35221=y
CONFIG_SENSORS_IR36021=y
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
CONFIG_SENSORS_ISL68137=y
CONFIG_SENSORS_LM25066=y
# CONFIG_SENSORS_LM25066_REGULATOR is not set
# CONFIG_SENSORS_LT7182S is not set
CONFIG_SENSORS_LTC2978=y
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
# CONFIG_SENSORS_LTC3815 is not set
CONFIG_SENSORS_MAX15301=y
CONFIG_SENSORS_MAX16064=y
CONFIG_SENSORS_MAX16601=y
CONFIG_SENSORS_MAX20730=y
CONFIG_SENSORS_MAX20751=y
# CONFIG_SENSORS_MAX31785 is not set
CONFIG_SENSORS_MAX34440=y
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_MP2888 is not set
CONFIG_SENSORS_MP2975=y
# CONFIG_SENSORS_MP5023 is not set
CONFIG_SENSORS_PIM4328=y
CONFIG_SENSORS_PLI1209BC=y
CONFIG_SENSORS_PLI1209BC_REGULATOR=y
CONFIG_SENSORS_PM6764TR=y
CONFIG_SENSORS_PXE1610=y
CONFIG_SENSORS_Q54SJ108A2=y
CONFIG_SENSORS_STPDDC60=y
CONFIG_SENSORS_TPS40422=y
CONFIG_SENSORS_TPS53679=y
CONFIG_SENSORS_UCD9000=y
CONFIG_SENSORS_UCD9200=y
CONFIG_SENSORS_XDPE152=y
CONFIG_SENSORS_XDPE122=y
# CONFIG_SENSORS_XDPE122_REGULATOR is not set
# CONFIG_SENSORS_ZL6100 is not set
# CONFIG_SENSORS_PWM_FAN is not set
CONFIG_SENSORS_RASPBERRYPI_HWMON=y
CONFIG_SENSORS_SL28CPLD=y
CONFIG_SENSORS_SBTSI=y
CONFIG_SENSORS_SBRMI=y
CONFIG_SENSORS_SHT15=y
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
CONFIG_SENSORS_SHT4x=y
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
CONFIG_SENSORS_SY7636A=y
# CONFIG_SENSORS_DME1737 is not set
CONFIG_SENSORS_EMC1403=y
CONFIG_SENSORS_EMC2103=y
CONFIG_SENSORS_EMC6W201=y
# CONFIG_SENSORS_SMSC47M1 is not set
CONFIG_SENSORS_SMSC47M192=y
CONFIG_SENSORS_SMSC47B397=y
CONFIG_SENSORS_SCH56XX_COMMON=y
CONFIG_SENSORS_SCH5627=y
CONFIG_SENSORS_SCH5636=y
CONFIG_SENSORS_STTS751=y
CONFIG_SENSORS_SMM665=y
# CONFIG_SENSORS_ADC128D818 is not set
CONFIG_SENSORS_ADS7828=y
# CONFIG_SENSORS_AMC6821 is not set
CONFIG_SENSORS_INA209=y
CONFIG_SENSORS_INA2XX=y
CONFIG_SENSORS_INA238=y
CONFIG_SENSORS_INA3221=y
# CONFIG_SENSORS_TC74 is not set
CONFIG_SENSORS_THMC50=y
CONFIG_SENSORS_TMP102=y
CONFIG_SENSORS_TMP103=y
CONFIG_SENSORS_TMP108=y
CONFIG_SENSORS_TMP401=y
CONFIG_SENSORS_TMP421=y
CONFIG_SENSORS_TMP464=y
CONFIG_SENSORS_TMP513=y
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
CONFIG_SENSORS_VT8231=y
CONFIG_SENSORS_W83773G=y
CONFIG_SENSORS_W83781D=y
# CONFIG_SENSORS_W83791D is not set
CONFIG_SENSORS_W83792D=y
CONFIG_SENSORS_W83793=y
CONFIG_SENSORS_W83795=y
CONFIG_SENSORS_W83795_FANCTRL=y
CONFIG_SENSORS_W83L785TS=y
# CONFIG_SENSORS_W83L786NG is not set
CONFIG_SENSORS_W83627HF=y
CONFIG_SENSORS_W83627EHF=y
# CONFIG_SENSORS_WM831X is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_NETLINK=y
CONFIG_THERMAL_STATISTICS=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
# CONFIG_THERMAL_OF is not set
# CONFIG_THERMAL_WRITABLE_TRIPS is not set
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE=y
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
# CONFIG_THERMAL_GOV_STEP_WISE is not set
CONFIG_THERMAL_GOV_BANG_BANG=y
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_HISI_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_IMX_SC_THERMAL=y
CONFIG_IMX8MM_THERMAL=y
CONFIG_K3_THERMAL=y
# CONFIG_SPEAR_THERMAL is not set
# CONFIG_SUN8I_THERMAL is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RCAR_THERMAL=y
# CONFIG_RCAR_GEN3_THERMAL is not set
CONFIG_RZG2L_THERMAL=y
# CONFIG_KIRKWOOD_THERMAL is not set
CONFIG_DOVE_THERMAL=y
CONFIG_ARMADA_THERMAL=y
# CONFIG_DA9062_THERMAL is not set
CONFIG_MTK_THERMAL=y

#
# Intel thermal drivers
#

#
# ACPI INT340X thermal drivers
#
# end of ACPI INT340X thermal drivers
# end of Intel thermal drivers

#
# Broadcom thermal drivers
#
CONFIG_BRCMSTB_THERMAL=y
CONFIG_BCM_NS_THERMAL=y
CONFIG_BCM_SR_THERMAL=y
# end of Broadcom thermal drivers

#
# Texas Instruments thermal drivers
#
CONFIG_TI_SOC_THERMAL=y
# CONFIG_TI_THERMAL is not set
# CONFIG_OMAP3_THERMAL is not set
CONFIG_OMAP4_THERMAL=y
# CONFIG_OMAP5_THERMAL is not set
CONFIG_DRA752_THERMAL=y
# end of Texas Instruments thermal drivers

#
# Samsung thermal drivers
#
# end of Samsung thermal drivers

#
# NVIDIA Tegra thermal drivers
#
CONFIG_TEGRA_SOCTHERM=y
CONFIG_TEGRA_BPMP_THERMAL=y
CONFIG_TEGRA30_TSENSOR=y
# end of NVIDIA Tegra thermal drivers

CONFIG_GENERIC_ADC_THERMAL=y

#
# Qualcomm thermal drivers
#
CONFIG_QCOM_SPMI_ADC_TM5=y
# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
# end of Qualcomm thermal drivers

CONFIG_SPRD_THERMAL=y
# CONFIG_KHADAS_MCU_FAN_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
# CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
CONFIG_WATCHDOG_SYSFS=y
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_DA9052_WATCHDOG is not set
# CONFIG_DA9055_WATCHDOG is not set
# CONFIG_DA9063_WATCHDOG is not set
CONFIG_DA9062_WATCHDOG=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_MENF21BMC_WATCHDOG=y
CONFIG_MENZ069_WATCHDOG=y
CONFIG_WM831X_WATCHDOG=y
# CONFIG_XILINX_WATCHDOG is not set
CONFIG_ZIIRAVE_WATCHDOG=y
CONFIG_SL28CPLD_WATCHDOG=y
# CONFIG_ARMADA_37XX_WATCHDOG is not set
# CONFIG_ASM9260_WATCHDOG is not set
CONFIG_AT91RM9200_WATCHDOG=y
# CONFIG_AT91SAM9X_WATCHDOG is not set
CONFIG_SAMA5D4_WATCHDOG=y
CONFIG_CADENCE_WATCHDOG=y
CONFIG_FTWDT010_WATCHDOG=y
# CONFIG_S3C2410_WATCHDOG is not set
CONFIG_DW_WATCHDOG=y
CONFIG_EP93XX_WATCHDOG=y
CONFIG_OMAP_WATCHDOG=y
CONFIG_PNX4008_WATCHDOG=y
# CONFIG_DAVINCI_WATCHDOG is not set
# CONFIG_K3_RTI_WATCHDOG is not set
CONFIG_RN5T618_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
# CONFIG_NPCM7XX_WATCHDOG is not set
CONFIG_TWL4030_WATCHDOG=y
# CONFIG_STMP3XXX_RTC_WATCHDOG is not set
# CONFIG_TS4800_WATCHDOG is not set
CONFIG_TS72XX_WATCHDOG=y
CONFIG_MAX63XX_WATCHDOG=y
CONFIG_MAX77620_WATCHDOG=y
# CONFIG_IMX2_WDT is not set
# CONFIG_IMX7ULP_WDT is not set
# CONFIG_RETU_WATCHDOG is not set
CONFIG_MOXART_WDT=y
# CONFIG_ST_LPC_WATCHDOG is not set
CONFIG_TEGRA_WATCHDOG=y
CONFIG_QCOM_WDT=y
CONFIG_MESON_GXBB_WATCHDOG=y
CONFIG_MESON_WATCHDOG=y
# CONFIG_MEDIATEK_WATCHDOG is not set
CONFIG_DIGICOLOR_WATCHDOG=y
CONFIG_LPC18XX_WATCHDOG=y
CONFIG_RENESAS_WDT=y
# CONFIG_RENESAS_RZAWDT is not set
# CONFIG_RENESAS_RZN1WDT is not set
# CONFIG_RENESAS_RZG2LWDT is not set
CONFIG_ASPEED_WATCHDOG=y
CONFIG_STPMIC1_WATCHDOG=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_RTD119X_WATCHDOG=y
# CONFIG_REALTEK_OTTO_WDT is not set
CONFIG_SPRD_WATCHDOG=y
# CONFIG_PM8916_WATCHDOG is not set
CONFIG_VISCONTI_WATCHDOG=y
CONFIG_MSC313E_WATCHDOG=y
CONFIG_APPLE_WATCHDOG=y
CONFIG_SUNPLUS_WATCHDOG=y
CONFIG_ALIM7101_WDT=y
CONFIG_SC520_WDT=y
CONFIG_I6300ESB_WDT=y
CONFIG_KEMPLD_WDT=y
CONFIG_RDC321X_WDT=y
CONFIG_BCM47XX_WDT=y
# CONFIG_BCM2835_WDT is not set
# CONFIG_BCM_KONA_WDT is not set
CONFIG_BCM7038_WDT=y
CONFIG_IMGPDC_WDT=y
# CONFIG_MPC5200_WDT is not set
# CONFIG_MEN_A21_WDT is not set
CONFIG_UML_WATCHDOG=y

#
# PCI-based Watchdog Cards
#
CONFIG_PCIPCWATCHDOG=y
CONFIG_WDTPCI=y

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=y
CONFIG_SSB_SPROM=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
# CONFIG_SSB_DRIVER_PCICORE is not set
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
# CONFIG_BCMA_HOST_PCI is not set
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_PCI=y
# CONFIG_BCMA_DRIVER_MIPS is not set
# CONFIG_BCMA_SFLASH is not set
# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
# CONFIG_BCMA_DRIVER_GPIO is not set
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_ACT8945A=y
# CONFIG_MFD_SUN4I_GPADC is not set
CONFIG_MFD_AS3711=y
CONFIG_MFD_AS3722=y
CONFIG_PMIC_ADP5520=y
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_AT91_USART is not set
CONFIG_MFD_ATMEL_FLEXCOM=y
CONFIG_MFD_ATMEL_HLCDC=y
CONFIG_MFD_BCM590XX=y
CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
# CONFIG_MFD_CROS_EC_DEV is not set
CONFIG_MFD_MADERA=y
CONFIG_MFD_MADERA_I2C=y
# CONFIG_MFD_CS47L15 is not set
# CONFIG_MFD_CS47L35 is not set
# CONFIG_MFD_CS47L85 is not set
CONFIG_MFD_CS47L90=y
# CONFIG_MFD_CS47L92 is not set
# CONFIG_MFD_ASIC3 is not set
CONFIG_PMIC_DA903X=y
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
CONFIG_MFD_DA9062=y
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
CONFIG_MFD_DLN2=y
# CONFIG_MFD_ENE_KB3930 is not set
CONFIG_MFD_EXYNOS_LPASS=y
CONFIG_MFD_GATEWORKS_GSC=y
CONFIG_MFD_MC13XXX=y
CONFIG_MFD_MC13XXX_I2C=y
CONFIG_MFD_MP2629=y
CONFIG_MFD_MXS_LRADC=y
CONFIG_MFD_MX25_TSADC=y
CONFIG_MFD_HI6421_PMIC=y
CONFIG_MFD_HI6421_SPMI=y
# CONFIG_MFD_HI655X_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
CONFIG_HTC_I2CPLD=y
# CONFIG_LPC_ICH is not set
CONFIG_LPC_SCH=y
# CONFIG_MFD_IQS62X is not set
CONFIG_MFD_JANZ_CMODIO=y
CONFIG_MFD_KEMPLD=y
CONFIG_MFD_88PM800=y
CONFIG_MFD_88PM805=y
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
CONFIG_MFD_MAX77686=y
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
CONFIG_MFD_MAX77843=y
CONFIG_MFD_MAX8907=y
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
CONFIG_MFD_MAX8998=y
CONFIG_MFD_MT6360=y
CONFIG_MFD_MT6397=y
CONFIG_MFD_MENF21BMC=y
CONFIG_MFD_VIPERBOARD=y
CONFIG_MFD_NTXEC=y
CONFIG_MFD_RETU=y
CONFIG_MFD_PCF50633=y
CONFIG_PCF50633_ADC=y
# CONFIG_PCF50633_GPIO is not set
CONFIG_UCB1400_CORE=y
CONFIG_MFD_PM8XXX=y
CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_RDC321X=y
# CONFIG_MFD_RT4831 is not set
CONFIG_MFD_RT5033=y
CONFIG_MFD_RC5T583=y
# CONFIG_MFD_RK808 is not set
CONFIG_MFD_RN5T618=y
# CONFIG_MFD_SEC_CORE is not set
CONFIG_MFD_SI476X_CORE=y
CONFIG_MFD_SIMPLE_MFD_I2C=y
CONFIG_MFD_SL28CPLD=y
CONFIG_MFD_SM501=y
CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_SKY81452 is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
CONFIG_MFD_LP3943=y
CONFIG_MFD_LP8788=y
# CONFIG_MFD_TI_LMU is not set
CONFIG_MFD_OMAP_USB_HOST=y
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
CONFIG_TPS65010=y
# CONFIG_TPS6507X is not set
CONFIG_MFD_TPS65086=y
CONFIG_MFD_TPS65090=y
CONFIG_MFD_TPS65217=y
# CONFIG_MFD_TI_LP873X is not set
CONFIG_MFD_TI_LP87565=y
CONFIG_MFD_TPS65218=y
CONFIG_MFD_TPS6586X=y
# CONFIG_MFD_TPS65910 is not set
CONFIG_MFD_TPS65912=y
CONFIG_MFD_TPS65912_I2C=y
CONFIG_TWL4030_CORE=y
CONFIG_MFD_TWL4030_AUDIO=y
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=y
CONFIG_MFD_LM3533=y
CONFIG_MFD_TIMBERDALE=y
CONFIG_MFD_TC3589X=y
CONFIG_MFD_TQMX86=y
CONFIG_MFD_VX855=y
# CONFIG_MFD_LOCHNAGAR is not set
CONFIG_MFD_ARIZONA=y
CONFIG_MFD_ARIZONA_I2C=y
CONFIG_MFD_CS47L24=y
CONFIG_MFD_WM5102=y
# CONFIG_MFD_WM5110 is not set
# CONFIG_MFD_WM8997 is not set
# CONFIG_MFD_WM8998 is not set
CONFIG_MFD_WM8400=y
CONFIG_MFD_WM831X=y
CONFIG_MFD_WM831X_I2C=y
# CONFIG_MFD_WM8350_I2C is not set
CONFIG_MFD_WM8994=y
CONFIG_MFD_STW481X=y
CONFIG_MFD_ROHM_BD718XX=y
CONFIG_MFD_ROHM_BD71828=y
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STM32_LPTIMER is not set
CONFIG_MFD_STM32_TIMERS=y
CONFIG_MFD_STPMIC1=y
CONFIG_MFD_STMFX=y
CONFIG_MFD_WCD934X=y
# CONFIG_MFD_ATC260X_I2C is not set
CONFIG_MFD_KHADAS_MCU=y
CONFIG_MFD_ACER_A500_EC=y
CONFIG_MFD_QCOM_PM8008=y
# CONFIG_MFD_RSMU_I2C is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
CONFIG_REGULATOR_88PG86X=y
CONFIG_REGULATOR_88PM800=y
# CONFIG_REGULATOR_ACT8865 is not set
CONFIG_REGULATOR_ACT8945A=y
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_ANATOP=y
# CONFIG_REGULATOR_ARIZONA_LDO1 is not set
# CONFIG_REGULATOR_ARIZONA_MICSUPP is not set
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_AS3711=y
# CONFIG_REGULATOR_AS3722 is not set
# CONFIG_REGULATOR_AXP20X is not set
CONFIG_REGULATOR_BCM590XX=y
CONFIG_REGULATOR_BD71815=y
# CONFIG_REGULATOR_BD71828 is not set
# CONFIG_REGULATOR_BD718XX is not set
# CONFIG_REGULATOR_BD9571MWV is not set
# CONFIG_REGULATOR_CROS_EC is not set
# CONFIG_REGULATOR_DA9062 is not set
# CONFIG_REGULATOR_DA9121 is not set
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_DA9211=y
# CONFIG_REGULATOR_FAN53555 is not set
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_HI6421=y
CONFIG_REGULATOR_HI6421V530=y
CONFIG_REGULATOR_HI6421V600=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
CONFIG_REGULATOR_LP3972=y
CONFIG_REGULATOR_LP872X=y
CONFIG_REGULATOR_LP8755=y
CONFIG_REGULATOR_LP87565=y
CONFIG_REGULATOR_LP8788=y
CONFIG_REGULATOR_LTC3589=y
CONFIG_REGULATOR_LTC3676=y
CONFIG_REGULATOR_MAX1586=y
# CONFIG_REGULATOR_MAX77620 is not set
CONFIG_REGULATOR_MAX77650=y
CONFIG_REGULATOR_MAX8649=y
CONFIG_REGULATOR_MAX8660=y
CONFIG_REGULATOR_MAX8893=y
CONFIG_REGULATOR_MAX8907=y
CONFIG_REGULATOR_MAX8952=y
CONFIG_REGULATOR_MAX8998=y
# CONFIG_REGULATOR_MAX20086 is not set
CONFIG_REGULATOR_MAX77686=y
CONFIG_REGULATOR_MAX77693=y
# CONFIG_REGULATOR_MAX77802 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MC13783 is not set
# CONFIG_REGULATOR_MC13892 is not set
CONFIG_REGULATOR_MCP16502=y
CONFIG_REGULATOR_MP5416=y
CONFIG_REGULATOR_MP8859=y
# CONFIG_REGULATOR_MP886X is not set
CONFIG_REGULATOR_MPQ7920=y
CONFIG_REGULATOR_MT6311=y
# CONFIG_REGULATOR_MT6315 is not set
CONFIG_REGULATOR_MT6323=y
CONFIG_REGULATOR_MT6358=y
# CONFIG_REGULATOR_MT6359 is not set
# CONFIG_REGULATOR_MT6360 is not set
CONFIG_REGULATOR_MT6380=y
CONFIG_REGULATOR_MT6397=y
CONFIG_REGULATOR_PBIAS=y
CONFIG_REGULATOR_PCA9450=y
# CONFIG_REGULATOR_PCF50633 is not set
CONFIG_REGULATOR_PF8X00=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_REGULATOR_PV88060=y
CONFIG_REGULATOR_PV88080=y
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_RPMH is not set
# CONFIG_REGULATOR_QCOM_SMD_RPM is not set
CONFIG_REGULATOR_QCOM_SPMI=y
CONFIG_REGULATOR_QCOM_USB_VBUS=y
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y
CONFIG_REGULATOR_RC5T583=y
CONFIG_REGULATOR_RN5T618=y
CONFIG_REGULATOR_ROHM=y
# CONFIG_REGULATOR_RT4801 is not set
CONFIG_REGULATOR_RT5033=y
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
CONFIG_REGULATOR_RT6245=y
# CONFIG_REGULATOR_RTQ2134 is not set
CONFIG_REGULATOR_RTMV20=y
CONFIG_REGULATOR_RTQ6752=y
CONFIG_REGULATOR_S2MPA01=y
# CONFIG_REGULATOR_S2MPS11 is not set
CONFIG_REGULATOR_S5M8767=y
# CONFIG_REGULATOR_SC2731 is not set
CONFIG_REGULATOR_SLG51000=y
# CONFIG_REGULATOR_STM32_BOOSTER is not set
CONFIG_REGULATOR_STM32_VREFBUF=y
# CONFIG_REGULATOR_STM32_PWR is not set
CONFIG_REGULATOR_STPMIC1=y
CONFIG_REGULATOR_TI_ABB=y
# CONFIG_REGULATOR_STW481X_VMMC is not set
CONFIG_REGULATOR_SY7636A=y
CONFIG_REGULATOR_SY8106A=y
CONFIG_REGULATOR_SY8824X=y
# CONFIG_REGULATOR_SY8827N is not set
CONFIG_REGULATOR_TPS51632=y
CONFIG_REGULATOR_TPS62360=y
CONFIG_REGULATOR_TPS6286X=y
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
# CONFIG_REGULATOR_TPS65086 is not set
CONFIG_REGULATOR_TPS65090=y
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS65217 is not set
CONFIG_REGULATOR_TPS65218=y
CONFIG_REGULATOR_TPS6586X=y
CONFIG_REGULATOR_TPS65912=y
# CONFIG_REGULATOR_TPS68470 is not set
CONFIG_REGULATOR_TWL4030=y
CONFIG_REGULATOR_UNIPHIER=y
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_WM831X is not set
CONFIG_REGULATOR_WM8400=y
# CONFIG_REGULATOR_WM8994 is not set
CONFIG_REGULATOR_QCOM_LABIBB=y
CONFIG_RC_CORE=y
CONFIG_BPF_LIRC_MODE2=y
CONFIG_LIRC=y
# CONFIG_RC_MAP is not set
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=y
CONFIG_IR_JVC_DECODER=y
# CONFIG_IR_MCE_KBD_DECODER is not set
CONFIG_IR_NEC_DECODER=y
# CONFIG_IR_RC5_DECODER is not set
# CONFIG_IR_RC6_DECODER is not set
# CONFIG_IR_RCMM_DECODER is not set
CONFIG_IR_SANYO_DECODER=y
CONFIG_IR_SHARP_DECODER=y
CONFIG_IR_SONY_DECODER=y
# CONFIG_IR_XMP_DECODER is not set
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=y
CONFIG_IR_FINTEK=y
CONFIG_IR_GPIO_CIR=y
CONFIG_IR_GPIO_TX=y
# CONFIG_IR_HIX5HD2 is not set
CONFIG_IR_IGORPLUGUSB=y
CONFIG_IR_IGUANA=y
CONFIG_IR_IMON=y
CONFIG_IR_IMON_RAW=y
CONFIG_IR_ITE_CIR=y
# CONFIG_IR_MCEUSB is not set
# CONFIG_IR_MESON is not set
CONFIG_IR_MESON_TX=y
# CONFIG_IR_MTK is not set
# CONFIG_IR_NUVOTON is not set
# CONFIG_IR_PWM_TX is not set
# CONFIG_IR_REDRAT3 is not set
CONFIG_IR_RX51=y
CONFIG_IR_SERIAL=y
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_STREAMZAP=y
CONFIG_IR_SUNXI=y
# CONFIG_IR_TOY is not set
CONFIG_IR_TTUSBIR=y
CONFIG_IR_WINBOND_CIR=y
# CONFIG_RC_ATI_REMOTE is not set
# CONFIG_RC_LOOPBACK is not set
CONFIG_RC_ST=y
CONFIG_RC_XBOX_DVD=y
CONFIG_IR_IMG=y
CONFIG_IR_IMG_RAW=y
# CONFIG_IR_IMG_HW is not set
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
# CONFIG_MEDIA_CEC_RC is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_SUPPORT_FILTER is not set
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

#
# Media core support
#
# CONFIG_VIDEO_DEV is not set
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y
# end of Media core support

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
# end of Media controller options

#
# Digital TV options
#
# CONFIG_DVB_NET is not set
CONFIG_DVB_MAX_ADAPTERS=16
# CONFIG_DVB_DYNAMIC_MINORS is not set
CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y
CONFIG_DVB_ULE_DEBUG=y
# end of Digital TV options

#
# Media drivers
#

#
# Media drivers
#
# CONFIG_MEDIA_USB_SUPPORT is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
# CONFIG_MEDIA_PLATFORM_DRIVERS is not set

#
# MMC/SDIO DVB adapters
#
# CONFIG_SMS_SDIO_DRV is not set
CONFIG_DVB_TEST_DRIVERS=y
CONFIG_DVB_VIDTV=y
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_TUNER=y

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_FC0011=y
CONFIG_MEDIA_TUNER_FC0012=y
CONFIG_MEDIA_TUNER_FC0013=y
CONFIG_MEDIA_TUNER_IT913X=y
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
CONFIG_MEDIA_TUNER_MAX2165=y
CONFIG_MEDIA_TUNER_MC44S803=y
CONFIG_MEDIA_TUNER_MT2060=y
CONFIG_MEDIA_TUNER_MT2063=y
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2131=y
CONFIG_MEDIA_TUNER_MT2266=y
CONFIG_MEDIA_TUNER_MXL301RF=y
CONFIG_MEDIA_TUNER_MXL5005S=y
# CONFIG_MEDIA_TUNER_MXL5007T is not set
CONFIG_MEDIA_TUNER_QM1D1B0004=y
CONFIG_MEDIA_TUNER_QM1D1C0042=y
# CONFIG_MEDIA_TUNER_QT1010 is not set
CONFIG_MEDIA_TUNER_R820T=y
# CONFIG_MEDIA_TUNER_SI2157 is not set
CONFIG_MEDIA_TUNER_SIMPLE=y
# CONFIG_MEDIA_TUNER_TDA18212 is not set
CONFIG_MEDIA_TUNER_TDA18218=y
CONFIG_MEDIA_TUNER_TDA18250=y
# CONFIG_MEDIA_TUNER_TDA18271 is not set
CONFIG_MEDIA_TUNER_TDA827X=y
# CONFIG_MEDIA_TUNER_TDA8290 is not set
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_TUA9001=y
# CONFIG_MEDIA_TUNER_XC2028 is not set
# CONFIG_MEDIA_TUNER_XC4000 is not set
CONFIG_MEDIA_TUNER_XC5000=y
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
# CONFIG_DVB_M88DS3103 is not set
CONFIG_DVB_MXL5XX=y
CONFIG_DVB_STB0899=y
CONFIG_DVB_STB6100=y
CONFIG_DVB_STV090x=y
CONFIG_DVB_STV0910=y
CONFIG_DVB_STV6110x=y
CONFIG_DVB_STV6111=y

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=y
CONFIG_DVB_MN88472=y
CONFIG_DVB_MN88473=y
# CONFIG_DVB_SI2165 is not set
CONFIG_DVB_TDA18271C2DD=y

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=y
CONFIG_DVB_CX24116=y
CONFIG_DVB_CX24117=y
CONFIG_DVB_CX24120=y
# CONFIG_DVB_CX24123 is not set
CONFIG_DVB_DS3000=y
CONFIG_DVB_MB86A16=y
CONFIG_DVB_MT312=y
CONFIG_DVB_S5H1420=y
# CONFIG_DVB_SI21XX is not set
# CONFIG_DVB_STB6000 is not set
# CONFIG_DVB_STV0288 is not set
CONFIG_DVB_STV0299=y
CONFIG_DVB_STV0900=y
CONFIG_DVB_STV6110=y
CONFIG_DVB_TDA10071=y
CONFIG_DVB_TDA10086=y
CONFIG_DVB_TDA8083=y
# CONFIG_DVB_TDA8261 is not set
CONFIG_DVB_TDA826X=y
CONFIG_DVB_TS2020=y
CONFIG_DVB_TUA6100=y
CONFIG_DVB_TUNER_CX24113=y
CONFIG_DVB_TUNER_ITD1000=y
CONFIG_DVB_VES1X93=y
CONFIG_DVB_ZL10036=y
CONFIG_DVB_ZL10039=y

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=y
CONFIG_DVB_CX22700=y
# CONFIG_DVB_CX22702 is not set
CONFIG_DVB_CXD2820R=y
# CONFIG_DVB_CXD2841ER is not set
# CONFIG_DVB_DIB3000MB is not set
# CONFIG_DVB_DIB3000MC is not set
# CONFIG_DVB_DIB7000M is not set
CONFIG_DVB_DIB7000P=y
CONFIG_DVB_DIB9000=y
CONFIG_DVB_DRXD=y
CONFIG_DVB_EC100=y
# CONFIG_DVB_L64781 is not set
# CONFIG_DVB_MT352 is not set
CONFIG_DVB_NXT6000=y
# CONFIG_DVB_RTL2830 is not set
# CONFIG_DVB_RTL2832 is not set
CONFIG_DVB_S5H1432=y
CONFIG_DVB_SI2168=y
CONFIG_DVB_SP887X=y
CONFIG_DVB_STV0367=y
CONFIG_DVB_TDA10048=y
CONFIG_DVB_TDA1004X=y
CONFIG_DVB_ZD1301_DEMOD=y
# CONFIG_DVB_ZL10353 is not set

#
# DVB-C (cable) frontends
#
# CONFIG_DVB_STV0297 is not set
# CONFIG_DVB_TDA10021 is not set
CONFIG_DVB_TDA10023=y
# CONFIG_DVB_VES1820 is not set

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
# CONFIG_DVB_AU8522_DTV is not set
CONFIG_DVB_BCM3510=y
# CONFIG_DVB_LG2160 is not set
CONFIG_DVB_LGDT3305=y
CONFIG_DVB_LGDT3306A=y
# CONFIG_DVB_LGDT330X is not set
CONFIG_DVB_MXL692=y
# CONFIG_DVB_NXT200X is not set
CONFIG_DVB_OR51132=y
# CONFIG_DVB_OR51211 is not set
CONFIG_DVB_S5H1409=y
# CONFIG_DVB_S5H1411 is not set

#
# ISDB-T (terrestrial) frontends
#
# CONFIG_DVB_DIB8000 is not set
# CONFIG_DVB_MB86A20S is not set
# CONFIG_DVB_S921 is not set

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_MN88443X=y
CONFIG_DVB_TC90522=y

#
# Digital terrestrial only tuners/PLL
#
# CONFIG_DVB_PLL is not set
# CONFIG_DVB_TUNER_DIB0070 is not set
CONFIG_DVB_TUNER_DIB0090=y

#
# SEC control devices for DVB-S
#
# CONFIG_DVB_A8293 is not set
# CONFIG_DVB_AF9033 is not set
CONFIG_DVB_ASCOT2E=y
CONFIG_DVB_ATBM8830=y
CONFIG_DVB_HELENE=y
# CONFIG_DVB_HORUS3A is not set
CONFIG_DVB_ISL6405=y
# CONFIG_DVB_ISL6421 is not set
# CONFIG_DVB_ISL6423 is not set
CONFIG_DVB_IX2505V=y
CONFIG_DVB_LGS8GL5=y
CONFIG_DVB_LGS8GXX=y
CONFIG_DVB_LNBH25=y
CONFIG_DVB_LNBH29=y
CONFIG_DVB_LNBP21=y
# CONFIG_DVB_LNBP22 is not set
CONFIG_DVB_M88RS2000=y
CONFIG_DVB_TDA665x=y
CONFIG_DVB_DRX39XYJ=y

#
# Common Interface (EN50221) controller drivers
#
# CONFIG_DVB_CXD2099 is not set
CONFIG_DVB_SP2=y
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=y
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KUNIT_TEST=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS=y
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
# CONFIG_DRM_FBDEV_EMULATION is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DP_AUX_BUS=y
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
CONFIG_DRM_DP_CEC=y
CONFIG_DRM_TTM=y
CONFIG_DRM_VRAM_HELPER=y
CONFIG_DRM_TTM_HELPER=y
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=y

#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=y
CONFIG_DRM_I2C_SIL164=y
CONFIG_DRM_I2C_NXP_TDA998X=y
CONFIG_DRM_I2C_NXP_TDA9950=y
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=y
# CONFIG_DRM_HDLCD_SHOW_UNDERRUN is not set
CONFIG_DRM_MALI_DISPLAY=y
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
CONFIG_DRM_NOUVEAU=y
# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set
CONFIG_NOUVEAU_DEBUG=5
CONFIG_NOUVEAU_DEBUG_DEFAULT=3
CONFIG_NOUVEAU_DEBUG_MMU=y
CONFIG_NOUVEAU_DEBUG_PUSH=y
# CONFIG_DRM_NOUVEAU_BACKLIGHT is not set
# CONFIG_DRM_KMB_DISPLAY is not set
# CONFIG_DRM_VGEM is not set
CONFIG_DRM_VKMS=y
CONFIG_DRM_EXYNOS=y

#
# CRTCs
#
# CONFIG_DRM_EXYNOS_FIMD is not set
CONFIG_DRM_EXYNOS5433_DECON=y
# CONFIG_DRM_EXYNOS7_DECON is not set
# CONFIG_DRM_EXYNOS_MIXER is not set
# CONFIG_DRM_EXYNOS_VIDI is not set

#
# Encoders and Bridges
#
# CONFIG_DRM_EXYNOS_DSI is not set
CONFIG_DRM_EXYNOS_HDMI=y
# CONFIG_DRM_EXYNOS_MIC is not set

#
# Sub-drivers
#
CONFIG_DRM_EXYNOS_G2D=y
CONFIG_DRM_EXYNOS_IPP=y
CONFIG_DRM_EXYNOS_FIMC=y
CONFIG_DRM_EXYNOS_ROTATOR=y
# CONFIG_DRM_EXYNOS_SCALER is not set
# CONFIG_DRM_EXYNOS_GSC is not set
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_VOP=y
# CONFIG_ROCKCHIP_VOP2 is not set
CONFIG_ROCKCHIP_ANALOGIX_DP=y
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_LVDS is not set
# CONFIG_ROCKCHIP_RGB is not set
CONFIG_ROCKCHIP_RK3066_HDMI=y
CONFIG_DRM_UDL=y
CONFIG_DRM_AST=y
CONFIG_DRM_MGAG200=y
# CONFIG_DRM_RCAR_DW_HDMI is not set
CONFIG_DRM_RCAR_USE_LVDS=y
CONFIG_DRM_RCAR_MIPI_DSI=y
# CONFIG_DRM_SUN4I is not set
CONFIG_DRM_QXL=y
# CONFIG_DRM_VIRTIO_GPU is not set
# CONFIG_DRM_MSM is not set
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ARM_VERSATILE=y
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=y
CONFIG_DRM_PANEL_BOE_HIMAX8279D=y
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_EDP is not set
CONFIG_DRM_PANEL_EBBG_FT8719=y
CONFIG_DRM_PANEL_ELIDA_KD35T133=y
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
CONFIG_DRM_PANEL_JDI_R63452=y
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=y
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
CONFIG_DRM_PANEL_NOVATEK_NT35560=y
CONFIG_DRM_PANEL_NOVATEK_NT35950=y
CONFIG_DRM_PANEL_NOVATEK_NT36672A=y
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=y
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=y
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=y
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=y
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
CONFIG_DRM_PANEL_RAYDIUM_RM68200=y
CONFIG_DRM_PANEL_RONBO_RB070D30=y
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=y
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=y
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
CONFIG_DRM_PANEL_SITRONIX_ST7703=y
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=y
CONFIG_DRM_PANEL_TDO_TL070WSH30=y
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y
CONFIG_DRM_PANEL_VISIONOX_RM69299=y
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
CONFIG_DRM_CHIPONE_ICN6211=y
CONFIG_DRM_CHRONTEL_CH7033=y
CONFIG_DRM_CROS_EC_ANX7688=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_FSL_LDB=y
CONFIG_DRM_ITE_IT6505=y
CONFIG_DRM_LONTIUM_LT8912B=y
CONFIG_DRM_LONTIUM_LT9211=y
CONFIG_DRM_LONTIUM_LT9611=y
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
CONFIG_DRM_ITE_IT66121=y
CONFIG_DRM_LVDS_CODEC=y
CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=y
# CONFIG_DRM_NWL_MIPI_DSI is not set
CONFIG_DRM_NXP_PTN3460=y
CONFIG_DRM_PARADE_PS8622=y
CONFIG_DRM_PARADE_PS8640=y
CONFIG_DRM_SIL_SII8620=y
# CONFIG_DRM_SII902X is not set
CONFIG_DRM_SII9234=y
# CONFIG_DRM_SIMPLE_BRIDGE is not set
CONFIG_DRM_THINE_THC63LVD1024=y
CONFIG_DRM_TOSHIBA_TC358762=y
CONFIG_DRM_TOSHIBA_TC358764=y
CONFIG_DRM_TOSHIBA_TC358767=y
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
CONFIG_DRM_TI_DLPC3433=y
CONFIG_DRM_TI_TFP410=y
# CONFIG_DRM_TI_SN65DSI83 is not set
CONFIG_DRM_TI_SN65DSI86=y
CONFIG_DRM_TI_TPD12S015=y
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=y
CONFIG_DRM_ANALOGIX_ANX7625=y
# CONFIG_DRM_I2C_ADV7511 is not set
CONFIG_DRM_CDNS_MHDP8546=y
CONFIG_DRM_CDNS_MHDP8546_J721E=y
CONFIG_DRM_IMX8QM_LDB=y
# CONFIG_DRM_IMX8QXP_LDB is not set
# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
CONFIG_DRM_IMX8QXP_PIXEL_LINK=y
CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=y
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_GP_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=y
# end of Display Interface Bridges

CONFIG_DRM_IMX=y
CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
CONFIG_DRM_IMX_TVE=y
CONFIG_DRM_IMX_LDB=y
CONFIG_DRM_IMX_HDMI=y
CONFIG_DRM_INGENIC=y
CONFIG_DRM_INGENIC_IPU=y
# CONFIG_DRM_V3D is not set
CONFIG_DRM_VC4=y
CONFIG_DRM_VC4_HDMI_CEC=y
# CONFIG_DRM_ETNAVIV is not set
CONFIG_DRM_HISI_HIBMC=y
# CONFIG_DRM_LOGICVC is not set
CONFIG_DRM_MXS=y
# CONFIG_DRM_MXSFB is not set
CONFIG_DRM_IMX_LCDIF=y
# CONFIG_DRM_ARCPGU is not set
CONFIG_DRM_BOCHS=y
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
CONFIG_DRM_SIMPLEDRM=y
CONFIG_DRM_PL111=y
# CONFIG_DRM_TVE200 is not set
CONFIG_DRM_LIMA=y
CONFIG_DRM_PANFROST=y
CONFIG_DRM_ASPEED_GFX=y
CONFIG_DRM_MCDE=y
CONFIG_DRM_TIDSS=y
CONFIG_DRM_GUD=y
CONFIG_DRM_SSD130X=y
CONFIG_DRM_SSD130X_I2C=y
CONFIG_DRM_SPRD=y
CONFIG_DRM_LEGACY=y
CONFIG_DRM_TDFX=y
CONFIG_DRM_R128=y
# CONFIG_DRM_MGA is not set
# CONFIG_DRM_VIA is not set
# CONFIG_DRM_SAVAGE is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_NOMODESET=y

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_DDC=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_SVGALIB=y
CONFIG_FB_BACKLIGHT=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y

#
# Frame buffer hardware drivers
#
CONFIG_FB_CIRRUS=y
CONFIG_FB_PM2=y
# CONFIG_FB_PM2_FIFO_DISCONNECT is not set
CONFIG_FB_CLPS711X=y
# CONFIG_FB_IMX is not set
CONFIG_FB_CYBER2000=y
# CONFIG_FB_CYBER2000_DDC is not set
CONFIG_FB_ARC=y
# CONFIG_FB_CONTROL is not set
# CONFIG_FB_ASILIANT is not set
CONFIG_FB_IMSTT=y
CONFIG_FB_UVESA=y
CONFIG_FB_EFI=y
CONFIG_FB_GBE=y
CONFIG_FB_GBE_MEM=4
CONFIG_FB_PVR2=y
# CONFIG_FB_OPENCORES is not set
CONFIG_FB_S1D13XXX=y
CONFIG_FB_ATMEL=y
# CONFIG_FB_NVIDIA is not set
CONFIG_FB_RIVA=y
CONFIG_FB_RIVA_I2C=y
# CONFIG_FB_RIVA_DEBUG is not set
CONFIG_FB_RIVA_BACKLIGHT=y
CONFIG_FB_I740=y
# CONFIG_FB_MATROX is not set
CONFIG_FB_RADEON=y
CONFIG_FB_RADEON_I2C=y
CONFIG_FB_RADEON_BACKLIGHT=y
CONFIG_FB_RADEON_DEBUG=y
CONFIG_FB_ATY128=y
CONFIG_FB_ATY128_BACKLIGHT=y
CONFIG_FB_ATY=y
CONFIG_FB_ATY_CT=y
CONFIG_FB_ATY_GENERIC_LCD=y
CONFIG_FB_ATY_GX=y
# CONFIG_FB_ATY_BACKLIGHT is not set
# CONFIG_FB_S3 is not set
CONFIG_FB_SAVAGE=y
# CONFIG_FB_SAVAGE_I2C is not set
# CONFIG_FB_SAVAGE_ACCEL is not set
# CONFIG_FB_SIS is not set
CONFIG_FB_VIA=y
CONFIG_FB_VIA_DIRECT_PROCFS=y
# CONFIG_FB_VIA_X_COMPATIBILITY is not set
# CONFIG_FB_NEOMAGIC is not set
CONFIG_FB_KYRO=y
CONFIG_FB_3DFX=y
CONFIG_FB_3DFX_ACCEL=y
# CONFIG_FB_3DFX_I2C is not set
CONFIG_FB_VOODOO1=y
CONFIG_FB_VT8623=y
CONFIG_FB_TRIDENT=y
CONFIG_FB_ARK=y
# CONFIG_FB_PM3 is not set
CONFIG_FB_CARMINE=y
CONFIG_FB_CARMINE_DRAM_EVAL=y
# CONFIG_CARMINE_DRAM_CUSTOM is not set
CONFIG_FB_WM8505=y
# CONFIG_FB_WMT_GE_ROPS is not set
CONFIG_FB_PXA168=y
CONFIG_FB_W100=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_TMIO=y
# CONFIG_FB_TMIO_ACCELL is not set
# CONFIG_FB_S3C is not set
# CONFIG_FB_SM501 is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
CONFIG_FB_IBM_GXT4500=y
# CONFIG_FB_GOLDFISH is not set
CONFIG_FB_DA8XX=y
# CONFIG_FB_VIRTUAL is not set
CONFIG_FB_METRONOME=y
CONFIG_FB_MB862XX=y
CONFIG_FB_MB862XX_PCI_GDC=y
# CONFIG_FB_MB862XX_I2C is not set
CONFIG_FB_BROADSHEET=y
CONFIG_FB_SSD1307=y
CONFIG_FB_SM712=y
# CONFIG_FB_OMAP_LCD_H3 is not set
# CONFIG_FB_OMAP2 is not set
CONFIG_MMP_DISP=y
CONFIG_MMP_DISP_CONTROLLER=y
# CONFIG_MMP_FB is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_ATMEL_LCDC=y
CONFIG_BACKLIGHT_KTD253=y
CONFIG_BACKLIGHT_LM3533=y
CONFIG_BACKLIGHT_OMAP1=y
# CONFIG_BACKLIGHT_PWM is not set
CONFIG_BACKLIGHT_DA903X=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_BACKLIGHT_WM831X=y
CONFIG_BACKLIGHT_ADP5520=y
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
CONFIG_BACKLIGHT_PCF50633=y
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
CONFIG_BACKLIGHT_LP855X=y
CONFIG_BACKLIGHT_LP8788=y
# CONFIG_BACKLIGHT_PANDORA is not set
CONFIG_BACKLIGHT_TPS65217=y
# CONFIG_BACKLIGHT_AS3711 is not set
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LV5207LP=y
CONFIG_BACKLIGHT_BD6107=y
CONFIG_BACKLIGHT_ARCXCNN=y
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support

CONFIG_VGASTATE=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
# CONFIG_LOGO_LINUX_CLUT224 is not set
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_CTL_FAST_LOOKUP is not set
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
CONFIG_SND_PCM_XRUN_DEBUG=y
CONFIG_SND_CTL_INPUT_VALIDATION=y
# CONFIG_SND_CTL_DEBUG is not set
CONFIG_SND_JACK_INJECTION_DEBUG=y
CONFIG_SND_VMASTER=y
CONFIG_SND_CTL_LED=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_SEQ_DUMMY=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=y
CONFIG_SND_SEQ_MIDI=y
CONFIG_SND_SEQ_MIDI_EMUL=y
CONFIG_SND_SEQ_VIRMIDI=y
CONFIG_SND_MPU401_UART=y
CONFIG_SND_OPL3_LIB=y
CONFIG_SND_OPL3_LIB_SEQ=y
CONFIG_SND_VX_LIB=y
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=y
# CONFIG_SND_ALOOP is not set
CONFIG_SND_VIRMIDI=y
CONFIG_SND_MTPAV=y
# CONFIG_SND_MTS64 is not set
CONFIG_SND_SERIAL_U16550=y
CONFIG_SND_MPU401=y
CONFIG_SND_PORTMAN2X4=y
CONFIG_SND_AC97_POWER_SAVE=y
CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ATIIXP is not set
CONFIG_SND_ATIIXP_MODEM=y
# CONFIG_SND_AU8810 is not set
CONFIG_SND_AU8820=y
CONFIG_SND_AU8830=y
CONFIG_SND_AW2=y
CONFIG_SND_BT87X=y
# CONFIG_SND_BT87X_OVERCLOCK is not set
CONFIG_SND_CA0106=y
CONFIG_SND_CMIPCI=y
CONFIG_SND_OXYGEN_LIB=y
CONFIG_SND_OXYGEN=y
# CONFIG_SND_CS4281 is not set
CONFIG_SND_CS46XX=y
# CONFIG_SND_CS46XX_NEW_DSP is not set
# CONFIG_SND_CS5535AUDIO is not set
CONFIG_SND_CTXFI=y
CONFIG_SND_DARLA20=y
CONFIG_SND_GINA20=y
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
CONFIG_SND_GINA24=y
CONFIG_SND_LAYLA24=y
# CONFIG_SND_MONA is not set
CONFIG_SND_MIA=y
CONFIG_SND_ECHO3G=y
CONFIG_SND_INDIGO=y
# CONFIG_SND_INDIGOIO is not set
CONFIG_SND_INDIGODJ=y
# CONFIG_SND_INDIGOIOX is not set
CONFIG_SND_INDIGODJX=y
CONFIG_SND_ENS1370=y
# CONFIG_SND_ENS1371 is not set
CONFIG_SND_FM801=y
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
CONFIG_SND_ICE1724=y
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LOLA is not set
CONFIG_SND_LX6464ES=y
CONFIG_SND_MIXART=y
# CONFIG_SND_NM256 is not set
CONFIG_SND_PCXHR=y
CONFIG_SND_RIPTIDE=y
# CONFIG_SND_RME32 is not set
CONFIG_SND_RME96=y
CONFIG_SND_RME9652=y
CONFIG_SND_VIA82XX=y
CONFIG_SND_VIA82XX_MODEM=y
CONFIG_SND_VIRTUOSO=y
CONFIG_SND_VX222=y
# CONFIG_SND_YMFPCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA=y
CONFIG_SND_HDA_GENERIC_LEDS=y
CONFIG_SND_HDA_INTEL=y
# CONFIG_SND_HDA_HWDEP is not set
CONFIG_SND_HDA_RECONFIG=y
CONFIG_SND_HDA_INPUT_BEEP=y
CONFIG_SND_HDA_INPUT_BEEP_MODE=1
CONFIG_SND_HDA_PATCH_LOADER=y
CONFIG_SND_HDA_CODEC_REALTEK=y
CONFIG_SND_HDA_CODEC_ANALOG=y
CONFIG_SND_HDA_CODEC_SIGMATEL=y
# CONFIG_SND_HDA_CODEC_VIA is not set
CONFIG_SND_HDA_CODEC_HDMI=y
CONFIG_SND_HDA_CODEC_CIRRUS=y
CONFIG_SND_HDA_CODEC_CS8409=y
CONFIG_SND_HDA_CODEC_CONEXANT=y
CONFIG_SND_HDA_CODEC_CA0110=y
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
CONFIG_SND_HDA_CODEC_SI3054=y
CONFIG_SND_HDA_GENERIC=y
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y
# end of HD-Audio

CONFIG_SND_HDA_CORE=y
CONFIG_SND_HDA_DSP_LOADER=y
CONFIG_SND_HDA_COMPONENT=y
CONFIG_SND_HDA_EXT_CORE=y
CONFIG_SND_HDA_PREALLOC_SIZE=64
CONFIG_SND_INTEL_DSP_CONFIG=y
CONFIG_SND_PXA2XX_LIB=y
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
CONFIG_SND_USB_UA101=y
CONFIG_SND_USB_CAIAQ=y
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_US122L=y
# CONFIG_SND_USB_6FIRE is not set
CONFIG_SND_USB_HIFACE=y
CONFIG_SND_BCD2000=y
CONFIG_SND_USB_LINE6=y
CONFIG_SND_USB_POD=y
# CONFIG_SND_USB_PODHD is not set
CONFIG_SND_USB_TONEPORT=y
# CONFIG_SND_USB_VARIAX is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_COMPRESS=y
CONFIG_SND_SOC_TOPOLOGY=y
# CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST is not set
CONFIG_SND_SOC_UTILS_KUNIT_TEST=y
# CONFIG_SND_SOC_ADI is not set
# CONFIG_SND_SOC_AMD_ACP is not set
CONFIG_SND_AMD_ACP_CONFIG=y
# CONFIG_SND_ATMEL_SOC is not set
CONFIG_SND_BCM2835_SOC_I2S=y
CONFIG_SND_SOC_CYGNUS=y
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
# CONFIG_SND_EP93XX_SOC is not set
CONFIG_SND_DESIGNWARE_I2S=y
CONFIG_SND_DESIGNWARE_PCM=y

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
CONFIG_SND_SOC_FSL_SAI=y
# CONFIG_SND_SOC_FSL_MQS is not set
CONFIG_SND_SOC_FSL_AUDMIX=y
CONFIG_SND_SOC_FSL_SSI=y
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
CONFIG_SND_SOC_FSL_MICFIL=y
CONFIG_SND_SOC_FSL_XCVR=y
CONFIG_SND_SOC_FSL_AUD2HTX=y
CONFIG_SND_SOC_FSL_UTILS=y
# CONFIG_SND_SOC_FSL_RPMSG is not set
CONFIG_SND_SOC_IMX_AUDMUX=y
# CONFIG_SND_IMX_SOC is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
CONFIG_SND_JZ4740_SOC_I2S=y
# CONFIG_SND_KIRKWOOD_SOC is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_INTEL_SST_TOPLEVEL is not set
CONFIG_SND_SOC_INTEL_KEEMBAY=y
CONFIG_SND_SOC_INTEL_AVS=y

#
# Intel AVS Machine drivers
#

#
# Available DSP configurations
#
CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=y
CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=y
# CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO is not set
CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=y
CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=y
# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373 is not set
CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=y
# CONFIG_SND_SOC_INTEL_AVS_MACH_RT274 is not set
CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=y
# CONFIG_SND_SOC_INTEL_AVS_MACH_RT298 is not set
# CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682 is not set
# CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567 is not set
# end of Intel AVS Machine drivers

CONFIG_SND_SOC_MEDIATEK=y
CONFIG_SND_SOC_MT8186=y
# CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357 is not set
CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S=y
CONFIG_SND_SOC_MTK_BTCVSD=y
# CONFIG_SND_SOC_MT8195 is not set

#
# ASoC support for Amlogic platforms
#
CONFIG_SND_MESON_AIU=y
CONFIG_SND_MESON_AXG_FIFO=y
# CONFIG_SND_MESON_AXG_FRDDR is not set
CONFIG_SND_MESON_AXG_TODDR=y
CONFIG_SND_MESON_AXG_TDM_FORMATTER=y
CONFIG_SND_MESON_AXG_TDM_INTERFACE=y
# CONFIG_SND_MESON_AXG_TDMIN is not set
CONFIG_SND_MESON_AXG_TDMOUT=y
CONFIG_SND_MESON_AXG_SOUND_CARD=y
CONFIG_SND_MESON_AXG_SPDIFOUT=y
CONFIG_SND_MESON_AXG_SPDIFIN=y
# CONFIG_SND_MESON_AXG_PDM is not set
CONFIG_SND_MESON_CARD_UTILS=y
CONFIG_SND_MESON_CODEC_GLUE=y
CONFIG_SND_MESON_GX_SOUND_CARD=y
CONFIG_SND_MESON_G12A_TOACODEC=y
CONFIG_SND_MESON_G12A_TOHDMITX=y
CONFIG_SND_SOC_MESON_T9015=y
# end of ASoC support for Amlogic platforms

# CONFIG_SND_MXS_SOC is not set
CONFIG_SND_PXA2XX_SOC=y
# CONFIG_SND_SOC_QCOM is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_I2S=y
# CONFIG_SND_SOC_ROCKCHIP_I2S_TDM is not set
CONFIG_SND_SOC_ROCKCHIP_PDM=y
# CONFIG_SND_SOC_ROCKCHIP_SPDIF is not set
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=y
CONFIG_SND_SOC_SAMSUNG=y
CONFIG_SND_S3C24XX_I2S=y
# CONFIG_SND_SAMSUNG_PCM is not set
CONFIG_SND_SAMSUNG_SPDIF=y
CONFIG_SND_SAMSUNG_I2S=y
CONFIG_SND_SOC_SAMSUNG_NEO1973_WM8753=y
CONFIG_SND_SOC_SAMSUNG_SMDK_WM8580=y
CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994=y
CONFIG_SND_SOC_SAMSUNG_S3C24XX_UDA134X=y
CONFIG_SND_SOC_SAMSUNG_SIMTEC=y
CONFIG_SND_SOC_SAMSUNG_SIMTEC_TLV320AIC23=y
CONFIG_SND_SOC_SAMSUNG_SIMTEC_HERMES=y
CONFIG_SND_SOC_SAMSUNG_H1940_UDA1380=y
CONFIG_SND_SOC_SAMSUNG_RX1950_UDA1380=y
# CONFIG_SND_SOC_SMARTQ is not set
# CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF is not set
# CONFIG_SND_SOC_SMDK_WM8994_PCM is not set
CONFIG_SND_SOC_TOBERMORY=y
CONFIG_SND_SOC_LOWLAND=y
# CONFIG_SND_SOC_LITTLEMILL is not set
CONFIG_SND_SOC_SNOW=y
# CONFIG_SND_SOC_ODROID is not set
# CONFIG_SND_SOC_ARNDALE is not set
CONFIG_SND_SOC_SAMSUNG_ARIES_WM8994=y
CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=y

#
# SoC Audio support for Renesas SoCs
#
# CONFIG_SND_SOC_SH4_FSI is not set
CONFIG_SND_SOC_RCAR=y
CONFIG_SND_SOC_RZ=y
# end of SoC Audio support for Renesas SoCs

CONFIG_SND_SOC_SOF_TOPLEVEL=y
CONFIG_SND_SOC_SOF_PCI_DEV=y
CONFIG_SND_SOC_SOF_PCI=y
# CONFIG_SND_SOC_SOF_ACPI is not set
# CONFIG_SND_SOC_SOF_OF is not set
CONFIG_SND_SOC_SOF_CLIENT=y
CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT=y
# CONFIG_SND_SOC_SOF_FORCE_PROBE_WORKQUEUE is not set
CONFIG_SND_SOC_SOF_NOCODEC=y
CONFIG_SND_SOC_SOF_NOCODEC_SUPPORT=y
CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS=y
CONFIG_SND_SOC_SOF_DEBUG=y
CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE=y
# CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP is not set
# CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC is not set
CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION=y
CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE=y
CONFIG_SND_SOC_SOF_DEBUG_ENABLE_FIRMWARE_TRACE=y
CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST=y
CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST_NUM=2
# CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR is not set
# CONFIG_SND_SOC_SOF_DEBUG_RETAIN_DSP_CONTEXT is not set
CONFIG_SND_SOC_SOF=y
CONFIG_SND_SOC_SOF_IPC3=y
CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=y
CONFIG_SND_SOC_SOF_AMD_COMMON=y
CONFIG_SND_SOC_SOF_AMD_RENOIR=y
# CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL is not set
CONFIG_SND_SOC_SPRD=y
CONFIG_SND_SOC_SPRD_MCDT=y
# CONFIG_SND_SOC_STI is not set

#
# STMicroelectronics STM32 SOC audio support
#
CONFIG_SND_SOC_STM32_SAI=y
# CONFIG_SND_SOC_STM32_I2S is not set
CONFIG_SND_SOC_STM32_SPDIFRX=y
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
# CONFIG_SND_SUN4I_CODEC is not set
CONFIG_SND_SUN8I_CODEC=y
CONFIG_SND_SUN8I_CODEC_ANALOG=y
CONFIG_SND_SUN50I_CODEC_ANALOG=y
# CONFIG_SND_SUN4I_I2S is not set
# CONFIG_SND_SUN4I_SPDIF is not set
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y
# end of Allwinner SoC Audio support

CONFIG_SND_SOC_TEGRA=y
CONFIG_SND_SOC_TEGRA20_AC97=y
CONFIG_SND_SOC_TEGRA20_DAS=y
# CONFIG_SND_SOC_TEGRA20_I2S is not set
CONFIG_SND_SOC_TEGRA20_SPDIF=y
CONFIG_SND_SOC_TEGRA30_AHUB=y
# CONFIG_SND_SOC_TEGRA30_I2S is not set
# CONFIG_SND_SOC_TEGRA210_AHUB is not set
CONFIG_SND_SOC_TEGRA210_DMIC=y
# CONFIG_SND_SOC_TEGRA210_I2S is not set
CONFIG_SND_SOC_TEGRA210_OPE=y
CONFIG_SND_SOC_TEGRA186_ASRC=y
CONFIG_SND_SOC_TEGRA186_DSPK=y
CONFIG_SND_SOC_TEGRA210_ADMAIF=y
CONFIG_SND_SOC_TEGRA210_MVC=y
CONFIG_SND_SOC_TEGRA210_SFC=y
CONFIG_SND_SOC_TEGRA210_AMX=y
# CONFIG_SND_SOC_TEGRA210_ADX is not set
CONFIG_SND_SOC_TEGRA210_MIXER=y
CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=y
CONFIG_SND_SOC_TEGRA_MACHINE_DRV=y
# CONFIG_SND_SOC_TEGRA_RT5640 is not set
CONFIG_SND_SOC_TEGRA_WM8753=y
# CONFIG_SND_SOC_TEGRA_WM8903 is not set
CONFIG_SND_SOC_TEGRA_WM9712=y
CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
# CONFIG_SND_SOC_TEGRA_ALC5632 is not set
CONFIG_SND_SOC_TEGRA_MAX98090=y
CONFIG_SND_SOC_TEGRA_RT5677=y
# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set

#
# Audio support for Texas Instruments SoCs
#
CONFIG_SND_SOC_TI_EDMA_PCM=y
CONFIG_SND_SOC_TI_SDMA_PCM=y
CONFIG_SND_SOC_TI_UDMA_PCM=y

#
# Texas Instruments DAI support for:
#
CONFIG_SND_SOC_DAVINCI_ASP=y
CONFIG_SND_SOC_DAVINCI_MCASP=y
# CONFIG_SND_SOC_DAVINCI_VCIF is not set
CONFIG_SND_SOC_OMAP_DMIC=y
CONFIG_SND_SOC_OMAP_MCBSP=y
CONFIG_SND_SOC_OMAP_MCPDM=y

#
# Audio support for boards with Texas Instruments SoCs
#
CONFIG_SND_SOC_OMAP3_TWL4030=y
CONFIG_SND_SOC_OMAP_HDMI=y
CONFIG_SND_SOC_J721E_EVM=y
# end of Audio support for Texas Instruments SoCs

CONFIG_SND_SOC_UNIPHIER=y
CONFIG_SND_SOC_UNIPHIER_AIO=y
CONFIG_SND_SOC_UNIPHIER_LD11=y
CONFIG_SND_SOC_UNIPHIER_PXS2=y
CONFIG_SND_SOC_UNIPHIER_EVEA_CODEC=y
CONFIG_SND_SOC_XILINX_I2S=y
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
CONFIG_SND_SOC_XILINX_SPDIF=y
CONFIG_SND_SOC_XTFPGA_I2S=y
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
# CONFIG_SND_SOC_ALL_CODECS is not set
CONFIG_SND_SOC_WM_HUBS=y
# CONFIG_SND_SOC_AC97_CODEC is not set
CONFIG_SND_SOC_ADAU_UTILS=y
CONFIG_SND_SOC_ADAU1372=y
CONFIG_SND_SOC_ADAU1372_I2C=y
CONFIG_SND_SOC_ADAU1701=y
# CONFIG_SND_SOC_ADAU1761_I2C is not set
CONFIG_SND_SOC_ADAU7002=y
CONFIG_SND_SOC_ADAU7118=y
CONFIG_SND_SOC_ADAU7118_HW=y
CONFIG_SND_SOC_ADAU7118_I2C=y
CONFIG_SND_SOC_AK4118=y
CONFIG_SND_SOC_AK4375=y
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
CONFIG_SND_SOC_AK5386=y
CONFIG_SND_SOC_AK5558=y
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_AW8738 is not set
# CONFIG_SND_SOC_BD28623 is not set
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_CROS_EC_CODEC=y
CONFIG_SND_SOC_CS35L32=y
CONFIG_SND_SOC_CS35L33=y
CONFIG_SND_SOC_CS35L34=y
CONFIG_SND_SOC_CS35L35=y
CONFIG_SND_SOC_CS35L36=y
# CONFIG_SND_SOC_CS35L41_I2C is not set
CONFIG_SND_SOC_CS35L45_TABLES=y
CONFIG_SND_SOC_CS35L45=y
CONFIG_SND_SOC_CS35L45_I2C=y
CONFIG_SND_SOC_CS42L42=y
CONFIG_SND_SOC_CS42L51=y
CONFIG_SND_SOC_CS42L51_I2C=y
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
CONFIG_SND_SOC_CS42L73=y
CONFIG_SND_SOC_CS4234=y
CONFIG_SND_SOC_CS4265=y
# CONFIG_SND_SOC_CS4270 is not set
CONFIG_SND_SOC_CS4271=y
CONFIG_SND_SOC_CS4271_I2C=y
CONFIG_SND_SOC_CS42XX8=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_CS43130=y
CONFIG_SND_SOC_CS4341=y
# CONFIG_SND_SOC_CS4349 is not set
CONFIG_SND_SOC_CS53L30=y
CONFIG_SND_SOC_CX2072X=y
# CONFIG_SND_SOC_JZ4740_CODEC is not set
# CONFIG_SND_SOC_JZ4725B_CODEC is not set
CONFIG_SND_SOC_JZ4760_CODEC=y
CONFIG_SND_SOC_JZ4770_CODEC=y
CONFIG_SND_SOC_L3=y
# CONFIG_SND_SOC_DA7213 is not set
CONFIG_SND_SOC_DA7219=y
CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=y
CONFIG_SND_SOC_ES7241=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
# CONFIG_SND_SOC_GTM601 is not set
CONFIG_SND_SOC_HDA=y
CONFIG_SND_SOC_ICS43432=y
# CONFIG_SND_SOC_INNO_RK3036 is not set
CONFIG_SND_SOC_MAX98088=y
CONFIG_SND_SOC_MAX98090=y
CONFIG_SND_SOC_MAX98095=y
CONFIG_SND_SOC_MAX98357A=y
# CONFIG_SND_SOC_MAX98504 is not set
CONFIG_SND_SOC_MAX9867=y
CONFIG_SND_SOC_MAX98927=y
CONFIG_SND_SOC_MAX98520=y
CONFIG_SND_SOC_MAX98373=y
CONFIG_SND_SOC_MAX98373_I2C=y
CONFIG_SND_SOC_MAX98373_SDW=y
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX98396 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
CONFIG_SND_SOC_PCM1681=y
CONFIG_SND_SOC_PCM1789=y
CONFIG_SND_SOC_PCM1789_I2C=y
# CONFIG_SND_SOC_PCM179X_I2C is not set
CONFIG_SND_SOC_PCM186X=y
CONFIG_SND_SOC_PCM186X_I2C=y
CONFIG_SND_SOC_PCM3060=y
CONFIG_SND_SOC_PCM3060_I2C=y
CONFIG_SND_SOC_PCM3168A=y
CONFIG_SND_SOC_PCM3168A_I2C=y
# CONFIG_SND_SOC_PCM5102A is not set
CONFIG_SND_SOC_PCM512x=y
CONFIG_SND_SOC_PCM512x_I2C=y
# CONFIG_SND_SOC_RK3328 is not set
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_RL6347A=y
CONFIG_SND_SOC_RT286=y
CONFIG_SND_SOC_RT1015P=y
CONFIG_SND_SOC_RT1308_SDW=y
CONFIG_SND_SOC_RT1316_SDW=y
CONFIG_SND_SOC_RT5616=y
CONFIG_SND_SOC_RT5631=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5659=y
CONFIG_SND_SOC_RT5677=y
# CONFIG_SND_SOC_RT5682_SDW is not set
CONFIG_SND_SOC_RT5682S=y
CONFIG_SND_SOC_RT700=y
CONFIG_SND_SOC_RT700_SDW=y
# CONFIG_SND_SOC_RT711_SDW is not set
# CONFIG_SND_SOC_RT711_SDCA_SDW is not set
CONFIG_SND_SOC_RT715=y
CONFIG_SND_SOC_RT715_SDW=y
# CONFIG_SND_SOC_RT715_SDCA_SDW is not set
CONFIG_SND_SOC_RT9120=y
# CONFIG_SND_SOC_SDW_MOCKUP is not set
CONFIG_SND_SOC_SGTL5000=y
CONFIG_SND_SOC_SIGMADSP=y
CONFIG_SND_SOC_SIGMADSP_I2C=y
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
# CONFIG_SND_SOC_SIMPLE_MUX is not set
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2518=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_I2C=y
# CONFIG_SND_SOC_SSM4567 is not set
CONFIG_SND_SOC_STA32X=y
CONFIG_SND_SOC_STA350=y
CONFIG_SND_SOC_STI_SAS=y
CONFIG_SND_SOC_TAS2552=y
CONFIG_SND_SOC_TAS2562=y
CONFIG_SND_SOC_TAS2764=y
CONFIG_SND_SOC_TAS2770=y
CONFIG_SND_SOC_TAS2780=y
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS5805M is not set
CONFIG_SND_SOC_TAS6424=y
CONFIG_SND_SOC_TDA7419=y
CONFIG_SND_SOC_TFA9879=y
# CONFIG_SND_SOC_TFA989X is not set
# CONFIG_SND_SOC_TLV320ADC3XXX is not set
CONFIG_SND_SOC_TLV320AIC23=y
CONFIG_SND_SOC_TLV320AIC23_I2C=y
CONFIG_SND_SOC_TLV320AIC31XX=y
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_TLV320AIC3X_I2C=y
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=y
CONFIG_SND_SOC_TSCS42XX=y
# CONFIG_SND_SOC_TSCS454 is not set
CONFIG_SND_SOC_TWL4030=y
# CONFIG_SND_SOC_UDA1334 is not set
CONFIG_SND_SOC_UDA134X=y
CONFIG_SND_SOC_UDA1380=y
CONFIG_SND_SOC_WCD9335=y
CONFIG_SND_SOC_WCD_MBHC=y
CONFIG_SND_SOC_WCD934X=y
CONFIG_SND_SOC_WCD938X=y
CONFIG_SND_SOC_WCD938X_SDW=y
CONFIG_SND_SOC_WM5100=y
CONFIG_SND_SOC_WM8510=y
CONFIG_SND_SOC_WM8523=y
CONFIG_SND_SOC_WM8524=y
CONFIG_SND_SOC_WM8580=y
CONFIG_SND_SOC_WM8711=y
CONFIG_SND_SOC_WM8728=y
# CONFIG_SND_SOC_WM8731_I2C is not set
CONFIG_SND_SOC_WM8737=y
CONFIG_SND_SOC_WM8741=y
CONFIG_SND_SOC_WM8750=y
CONFIG_SND_SOC_WM8753=y
# CONFIG_SND_SOC_WM8776 is not set
CONFIG_SND_SOC_WM8782=y
CONFIG_SND_SOC_WM8804=y
CONFIG_SND_SOC_WM8804_I2C=y
CONFIG_SND_SOC_WM8903=y
CONFIG_SND_SOC_WM8904=y
CONFIG_SND_SOC_WM8940=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SOC_WM8974=y
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
CONFIG_SND_SOC_WM8994=y
CONFIG_SND_SOC_WM9081=y
CONFIG_SND_SOC_WM9712=y
# CONFIG_SND_SOC_WSA881X is not set
# CONFIG_SND_SOC_WSA883X is not set
CONFIG_SND_SOC_MAX9759=y
CONFIG_SND_SOC_MT6351=y
CONFIG_SND_SOC_MT6358=y
# CONFIG_SND_SOC_MT6359 is not set
CONFIG_SND_SOC_MT6359_ACCDET=y
CONFIG_SND_SOC_MT6660=y
# CONFIG_SND_SOC_NAU8315 is not set
CONFIG_SND_SOC_NAU8540=y
CONFIG_SND_SOC_NAU8810=y
# CONFIG_SND_SOC_NAU8821 is not set
CONFIG_SND_SOC_NAU8822=y
CONFIG_SND_SOC_NAU8824=y
CONFIG_SND_SOC_NAU8825=y
# CONFIG_SND_SOC_TPA6130A2 is not set
CONFIG_SND_SOC_LPASS_MACRO_COMMON=y
# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
CONFIG_SND_SOC_LPASS_VA_MACRO=y
CONFIG_SND_SOC_LPASS_RX_MACRO=y
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
CONFIG_SND_TEST_COMPONENT=y
# CONFIG_SND_VIRTIO is not set
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
CONFIG_UHID=y
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
# CONFIG_HID_ACRUX_FF is not set
CONFIG_HID_APPLE=y
CONFIG_HID_AUREAL=y
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_MACALLY is not set
CONFIG_HID_CMEDIA=y
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
CONFIG_HID_ELECOM=y
# CONFIG_HID_EZKEY is not set
CONFIG_HID_GEMBIRD=y
CONFIG_HID_GFRM=y
CONFIG_HID_GLORIOUS=y
CONFIG_HID_VIVALDI_COMMON=y
CONFIG_HID_VIVALDI=y
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_VIEWSONIC is not set
CONFIG_HID_XIAOMI=y
# CONFIG_HID_GYRATION is not set
CONFIG_HID_ICADE=y
CONFIG_HID_ITE=y
# CONFIG_HID_JABRA is not set
# CONFIG_HID_TWINHAN is not set
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LED=y
CONFIG_HID_LENOVO=y
CONFIG_HID_MAGICMOUSE=y
# CONFIG_HID_MALTRON is not set
CONFIG_HID_MAYFLASH=y
CONFIG_HID_REDRAGON=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NINTENDO=y
# CONFIG_NINTENDO_FF is not set
CONFIG_HID_NTI=y
# CONFIG_HID_ORTEK is not set
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
# CONFIG_HID_PICOLCD_LEDS is not set
# CONFIG_HID_PICOLCD_CIR is not set
CONFIG_HID_PLANTRONICS=y
# CONFIG_HID_PLAYSTATION is not set
# CONFIG_HID_RAZER is not set
CONFIG_HID_PRIMAX=y
# CONFIG_HID_SAITEK is not set
CONFIG_HID_SEMITEK=y
CONFIG_HID_SPEEDLINK=y
# CONFIG_HID_STEAM is not set
CONFIG_HID_STEELSERIES=y
CONFIG_HID_SUNPLUS=y
CONFIG_HID_RMI=y
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=y
# CONFIG_SMARTJOYPLUS_FF is not set
CONFIG_HID_TIVO=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THINGM=y
CONFIG_HID_UDRAW_PS3=y
# CONFIG_HID_WIIMOTE is not set
CONFIG_HID_XINMO=y
# CONFIG_HID_ZEROPLUS is not set
CONFIG_HID_ZYDACRON=y
CONFIG_HID_SENSOR_HUB=y
CONFIG_HID_SENSOR_CUSTOM_SENSOR=y
# CONFIG_HID_ALPS is not set
# end of Special HID drivers

#
# USB HID support
#
# CONFIG_USB_HID is not set
# CONFIG_HID_PID is not set

#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
# end of USB HID Boot Protocol drivers
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID_OF=y
# CONFIG_I2C_HID_OF_ELAN is not set
CONFIG_I2C_HID_OF_GOODIX=y
# end of I2C HID support

CONFIG_I2C_HID_CORE=y

#
# Intel ISH HID support
#
# end of Intel ISH HID support

#
# AMD SFH HID Support
#
CONFIG_AMD_SFH_HID=y
# end of AMD SFH HID Support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
# CONFIG_USB_LED_TRIG is not set
CONFIG_USB_ULPI_BUS=y
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
# CONFIG_USB_DEFAULT_PERSIST is not set
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
CONFIG_USB_OTG_PRODUCTLIST=y
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
# CONFIG_USB_MON is not set

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=y
# CONFIG_USB_XHCI_HCD is not set
CONFIG_USB_EHCI_BRCMSTB=y
CONFIG_USB_BRCMSTB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_EHCI_HCD_NPCM7XX=y
CONFIG_USB_EHCI_HCD_OMAP=y
CONFIG_USB_EHCI_HCD_ORION=y
# CONFIG_USB_EHCI_HCD_SPEAR is not set
CONFIG_USB_EHCI_HCD_STI=y
CONFIG_USB_EHCI_HCD_AT91=y
CONFIG_USB_EHCI_SH=y
CONFIG_USB_EHCI_EXYNOS=y
CONFIG_USB_EHCI_MV=y
# CONFIG_USB_CNS3XXX_EHCI is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_OXU210HP_HCD is not set
CONFIG_USB_ISP116X_HCD=y
CONFIG_USB_ISP1362_HCD=y
CONFIG_USB_FOTG210_HCD=y
# CONFIG_USB_OHCI_HCD is not set
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_U132_HCD=y
CONFIG_USB_SL811_HCD=y
CONFIG_USB_SL811_HCD_ISO=y
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_RENESAS_USBHS_HCD is not set
# CONFIG_USB_HCD_BCMA is not set
CONFIG_USB_HCD_SSB=y
CONFIG_USB_HCD_TEST_MODE=y
CONFIG_USB_RENESAS_USBHS=y

#
# USB Device Class drivers
#
CONFIG_USB_PRINTER=y
# CONFIG_USB_WDM is not set
CONFIG_USB_TMC=y

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
CONFIG_USBIP_CORE=y
CONFIG_USBIP_VHCI_HCD=y
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=y
# CONFIG_USBIP_VUDC is not set
CONFIG_USBIP_DEBUG=y
CONFIG_USB_CDNS_SUPPORT=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
# CONFIG_USB_CDNS3_HOST is not set
CONFIG_USB_CDNS3_TI=y
# CONFIG_USB_CDNS3_IMX is not set
# CONFIG_USB_MTU3 is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
# CONFIG_USB_MUSB_TUSB6010 is not set
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_MUSB_UX500=y
CONFIG_USB_MUSB_MEDIATEK=y
CONFIG_USB_MUSB_POLARFIRE_SOC=y

#
# MUSB DMA mode
#
CONFIG_MUSB_PIO_ONLY=y
# CONFIG_USB_DWC3 is not set
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
# CONFIG_USB_USS720 is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
CONFIG_USB_EMI26=y
CONFIG_USB_ADUTUX=y
CONFIG_USB_SEVSEG=y
CONFIG_USB_LEGOTOWER=y
CONFIG_USB_LCD=y
CONFIG_USB_CYPRESS_CY7C63=y
CONFIG_USB_CYTHERM=y
# CONFIG_USB_IDMOUSE is not set
CONFIG_USB_FTDI_ELAN=y
CONFIG_USB_APPLEDISPLAY=y
CONFIG_USB_QCOM_EUD=y
CONFIG_APPLE_MFI_FASTCHARGE=y
# CONFIG_USB_SISUSBVGA is not set
CONFIG_USB_LD=y
CONFIG_USB_TRANCEVIBRATOR=y
CONFIG_USB_IOWARRIOR=y
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
CONFIG_USB_YUREX=y
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_HSIC_USB4604=y
# CONFIG_USB_LINK_LAYER_TEST is not set
# CONFIG_USB_CHAOSKEY is not set
# CONFIG_BRCM_USB_PINMAP is not set
CONFIG_USB_ONBOARD_HUB=y
CONFIG_USB_ATM=y
CONFIG_USB_SPEEDTOUCH=y
CONFIG_USB_CXACRU=y
CONFIG_USB_UEAGLEATM=y
CONFIG_USB_XUSBATM=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_AM335X_CONTROL_USB=y
CONFIG_AM335X_PHY_USB=y
CONFIG_USB_GPIO_VBUS=y
# CONFIG_TAHVO_USB is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_TEGRA_PHY is not set
# CONFIG_USB_ULPI is not set
# CONFIG_JZ4770_PHY is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG=y
CONFIG_USB_GADGET_VERBOSE=y
CONFIG_USB_GADGET_DEBUG_FILES=y
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2

#
# USB Peripheral Controller
#
# CONFIG_USB_LPC32XX is not set
# CONFIG_USB_FOTG210_UDC is not set
CONFIG_USB_GR_UDC=y
CONFIG_USB_R8A66597=y
CONFIG_USB_RENESAS_USBHS_UDC=y
# CONFIG_USB_RENESAS_USB3 is not set
CONFIG_USB_PXA27X=y
CONFIG_USB_MV_UDC=y
CONFIG_USB_MV_U3D=y
CONFIG_USB_SNP_CORE=y
# CONFIG_USB_SNP_UDC_PLAT is not set
CONFIG_USB_M66592=y
CONFIG_USB_BDC_UDC=y
CONFIG_USB_AMD5536UDC=y
CONFIG_USB_NET2272=y
# CONFIG_USB_NET2272_DMA is not set
CONFIG_USB_NET2280=y
CONFIG_USB_GOKU=y
CONFIG_USB_EG20T=y
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_ASPEED_UDC is not set
# CONFIG_USB_ASPEED_VHUB is not set
CONFIG_USB_DUMMY_HCD=y
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_SS_LB=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_FS=y
# CONFIG_USB_CONFIGFS is not set

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=y
# CONFIG_USB_AUDIO is not set
CONFIG_USB_ETH=y
# CONFIG_USB_ETH_RNDIS is not set
# CONFIG_USB_ETH_EEM is not set
CONFIG_USB_G_NCM=y
CONFIG_USB_GADGETFS=y
CONFIG_USB_FUNCTIONFS=y
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_G_HID is not set
# CONFIG_USB_RAW_GADGET is not set
# end of USB Gadget precomposed configurations

# CONFIG_TYPEC is not set
CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SIMPLE=y
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_DEBUG=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
# CONFIG_MMC_SDHCI_OF_ASPEED is not set
CONFIG_MMC_SDHCI_OF_AT91=y
CONFIG_MMC_SDHCI_OF_ESDHC=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
# CONFIG_MMC_SDHCI_OF_SPARX5 is not set
# CONFIG_MMC_SDHCI_CADENCE is not set
# CONFIG_MMC_SDHCI_CNS3XXX is not set
CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_MMC_SDHCI_DOVE=y
CONFIG_MMC_SDHCI_TEGRA=y
CONFIG_MMC_SDHCI_S3C=y
CONFIG_MMC_SDHCI_PXAV3=y
# CONFIG_MMC_SDHCI_PXAV2 is not set
# CONFIG_MMC_SDHCI_SPEAR is not set
# CONFIG_MMC_SDHCI_S3C_DMA is not set
CONFIG_MMC_SDHCI_BCM_KONA=y
# CONFIG_MMC_SDHCI_F_SDH30 is not set
CONFIG_MMC_SDHCI_MILBEAUT=y
# CONFIG_MMC_SDHCI_IPROC is not set
CONFIG_MMC_MESON_GX=y
# CONFIG_MMC_MESON_MX_SDHC is not set
# CONFIG_MMC_MESON_MX_SDIO is not set
CONFIG_MMC_MOXART=y
CONFIG_MMC_SDHCI_ST=y
CONFIG_MMC_OMAP_HS=y
# CONFIG_MMC_ALCOR is not set
CONFIG_MMC_SDHCI_MSM=y
CONFIG_MMC_TIFM_SD=y
# CONFIG_MMC_DAVINCI is not set
# CONFIG_MMC_S3C is not set
CONFIG_MMC_SDHCI_SPRD=y
CONFIG_MMC_TMIO_CORE=y
CONFIG_MMC_TMIO=y
# CONFIG_MMC_SDHI is not set
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_CB710=y
CONFIG_MMC_VIA_SDMMC=y
# CONFIG_MMC_CAVIUM_THUNDERX is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
CONFIG_MMC_DW_HI3798CV200=y
CONFIG_MMC_DW_K3=y
CONFIG_MMC_DW_PCI=y
CONFIG_MMC_SH_MMCIF=y
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
CONFIG_MMC_USDHI6ROL0=y
CONFIG_MMC_REALTEK_PCI=y
# CONFIG_MMC_REALTEK_USB is not set
# CONFIG_MMC_SUNXI is not set
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=y
CONFIG_MMC_BCM2835=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MMC_SDHCI_OMAP=y
# CONFIG_MMC_SDHCI_AM654 is not set
# CONFIG_MMC_OWL is not set
CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
CONFIG_MMC_LITEX=y
CONFIG_MEMSTICK=y
CONFIG_MEMSTICK_DEBUG=y

#
# MemoryStick drivers
#
CONFIG_MEMSTICK_UNSAFE_RESUME=y

#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=y
CONFIG_MEMSTICK_JMICRON_38X=y
CONFIG_MEMSTICK_R592=y
# CONFIG_MEMSTICK_REALTEK_PCI is not set
CONFIG_MEMSTICK_REALTEK_USB=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=y
CONFIG_LEDS_ARIEL=y
CONFIG_LEDS_AW2013=y
CONFIG_LEDS_BCM6328=y
CONFIG_LEDS_BCM6358=y
CONFIG_LEDS_TURRIS_OMNIA=y
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
CONFIG_LEDS_LM3533=y
CONFIG_LEDS_LM3642=y
CONFIG_LEDS_LM3692X=y
CONFIG_LEDS_MT6323=y
# CONFIG_LEDS_S3C24XX is not set
# CONFIG_LEDS_COBALT_QUBE is not set
# CONFIG_LEDS_COBALT_RAQ is not set
CONFIG_LEDS_PCA9532=y
# CONFIG_LEDS_PCA9532_GPIO is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
CONFIG_LEDS_LP50XX=y
CONFIG_LEDS_LP55XX_COMMON=y
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
CONFIG_LEDS_LP5562=y
# CONFIG_LEDS_LP8501 is not set
# CONFIG_LEDS_LP8788 is not set
CONFIG_LEDS_LP8860=y
CONFIG_LEDS_PCA955X=y
# CONFIG_LEDS_PCA955X_GPIO is not set
# CONFIG_LEDS_PCA963X is not set
CONFIG_LEDS_WM831X_STATUS=y
CONFIG_LEDS_DA903X=y
# CONFIG_LEDS_PWM is not set
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=y
CONFIG_LEDS_LT3593=y
CONFIG_LEDS_ADP5520=y
CONFIG_LEDS_MC13783=y
# CONFIG_LEDS_NS2 is not set
# CONFIG_LEDS_NETXBIG is not set
# CONFIG_LEDS_TCA6507 is not set
CONFIG_LEDS_TLC591XX=y
CONFIG_LEDS_LM355x=y
CONFIG_LEDS_OT200=y
CONFIG_LEDS_MENF21BMC=y
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=y
# CONFIG_LEDS_SYSCON is not set
CONFIG_LEDS_PM8058=y
# CONFIG_LEDS_MLXREG is not set
CONFIG_LEDS_USER=y
CONFIG_LEDS_TI_LMU_COMMON=y
CONFIG_LEDS_LM3697=y
# CONFIG_LEDS_IP30 is not set
CONFIG_LEDS_ACER_A500=y
# CONFIG_LEDS_BCM63138 is not set
CONFIG_LEDS_LGM=y

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=y
# CONFIG_LEDS_AS3645A is not set
# CONFIG_LEDS_KTD2692 is not set
# CONFIG_LEDS_LM3601X is not set
# CONFIG_LEDS_MT6360 is not set
CONFIG_LEDS_RT4505=y
CONFIG_LEDS_RT8515=y
CONFIG_LEDS_SGM3140=y

#
# RGB LED drivers
#
CONFIG_LEDS_PWM_MULTICOLOR=y
CONFIG_LEDS_QCOM_LPG=y

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y

#
# Simple LED drivers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_DEBUG=y
# CONFIG_EDAC_AL_MC is not set
# CONFIG_EDAC_SIFIVE is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_SYSTOHC is not set
CONFIG_RTC_DEBUG=y
CONFIG_RTC_LIB_KUNIT_TEST=y
# CONFIG_RTC_NVMEM is not set

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
# CONFIG_RTC_INTF_PROC is not set
# CONFIG_RTC_INTF_DEV is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_88PM80X=y
CONFIG_RTC_DRV_ABB5ZES3=y
CONFIG_RTC_DRV_ABEOZ9=y
# CONFIG_RTC_DRV_ABX80X is not set
# CONFIG_RTC_DRV_BRCMSTB is not set
CONFIG_RTC_DRV_AS3722=y
CONFIG_RTC_DRV_DS1307=y
# CONFIG_RTC_DRV_DS1307_CENTURY is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_LP8788=y
CONFIG_RTC_DRV_MAX6900=y
CONFIG_RTC_DRV_MAX8907=y
# CONFIG_RTC_DRV_MAX8998 is not set
# CONFIG_RTC_DRV_MAX77686 is not set
CONFIG_RTC_DRV_NCT3018Y=y
CONFIG_RTC_DRV_RS5C372=y
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_ISL12022=y
CONFIG_RTC_DRV_ISL12026=y
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
CONFIG_RTC_DRV_PCF85063=y
CONFIG_RTC_DRV_PCF85363=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_PCF8583=y
# CONFIG_RTC_DRV_M41T80 is not set
CONFIG_RTC_DRV_BD70528=y
CONFIG_RTC_DRV_BQ32K=y
CONFIG_RTC_DRV_TWL4030=y
CONFIG_RTC_DRV_TPS6586X=y
CONFIG_RTC_DRV_RC5T583=y
CONFIG_RTC_DRV_RC5T619=y
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
CONFIG_RTC_DRV_RX8010=y
# CONFIG_RTC_DRV_RX8581 is not set
CONFIG_RTC_DRV_RX8025=y
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
CONFIG_RTC_DRV_RV3032=y
CONFIG_RTC_DRV_RV8803=y
CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_SD3078=y

#
# SPI RTC drivers
#
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=y
# CONFIG_RTC_DRV_DS3232_HWMON is not set
# CONFIG_RTC_DRV_PCF2127 is not set
CONFIG_RTC_DRV_RV3029C2=y
CONFIG_RTC_DRV_RV3029_HWMON=y
CONFIG_RTC_DRV_RX6110=y

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
CONFIG_RTC_DRV_DS1553=y
CONFIG_RTC_DRV_DS1685_FAMILY=y
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
# CONFIG_RTC_DRV_DS1742 is not set
CONFIG_RTC_DRV_DS2404=y
# CONFIG_RTC_DRV_DA9063 is not set
CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_STK17TA8=y
CONFIG_RTC_DRV_M48T86=y
CONFIG_RTC_DRV_M48T35=y
CONFIG_RTC_DRV_M48T59=y
# CONFIG_RTC_DRV_MSM6242 is not set
CONFIG_RTC_DRV_BQ4802=y
CONFIG_RTC_DRV_RP5C01=y
# CONFIG_RTC_DRV_V3020 is not set
CONFIG_RTC_DRV_GAMECUBE=y
CONFIG_RTC_DRV_WM831X=y
CONFIG_RTC_DRV_SC27XX=y
# CONFIG_RTC_DRV_SPEAR is not set
# CONFIG_RTC_DRV_PCF50633 is not set
CONFIG_RTC_DRV_ZYNQMP=y
CONFIG_RTC_DRV_CROS_EC=y
CONFIG_RTC_DRV_NTXEC=y

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_ASM9260=y
CONFIG_RTC_DRV_DAVINCI=y
CONFIG_RTC_DRV_DIGICOLOR=y
CONFIG_RTC_DRV_FSL_FTM_ALARM=y
CONFIG_RTC_DRV_MESON=y
CONFIG_RTC_DRV_MESON_VRTC=y
CONFIG_RTC_DRV_OMAP=y
CONFIG_RTC_DRV_S3C=y
CONFIG_RTC_DRV_EP93XX=y
# CONFIG_RTC_DRV_AT91RM9200 is not set
CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_RTC_DRV_RZN1=y
# CONFIG_RTC_DRV_GENERIC is not set
CONFIG_RTC_DRV_VT8500=y
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_SUNXI is not set
CONFIG_RTC_DRV_MV=y
# CONFIG_RTC_DRV_ARMADA38X is not set
CONFIG_RTC_DRV_CADENCE=y
CONFIG_RTC_DRV_FTRTC010=y
CONFIG_RTC_DRV_STMP=y
# CONFIG_RTC_DRV_MC13XXX is not set
# CONFIG_RTC_DRV_JZ4740 is not set
CONFIG_RTC_DRV_LPC24XX=y
CONFIG_RTC_DRV_LPC32XX=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_RTC_DRV_TEGRA=y
CONFIG_RTC_DRV_MXC=y
CONFIG_RTC_DRV_MXC_V2=y
# CONFIG_RTC_DRV_SNVS is not set
CONFIG_RTC_DRV_MOXART=y
# CONFIG_RTC_DRV_MT2712 is not set
CONFIG_RTC_DRV_MT6397=y
CONFIG_RTC_DRV_MT7622=y
# CONFIG_RTC_DRV_XGENE is not set
# CONFIG_RTC_DRV_R7301 is not set
CONFIG_RTC_DRV_STM32=y
# CONFIG_RTC_DRV_RTD119X is not set
# CONFIG_RTC_DRV_ASPEED is not set
CONFIG_RTC_DRV_TI_K3=y

#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_GOLDFISH=y
CONFIG_RTC_DRV_MSC313=y
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_APPLE_ADMAC=y
CONFIG_AXI_DMAC=y
CONFIG_DMA_JZ4780=y
CONFIG_DMA_SA11X0=y
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_EP93XX_DMA is not set
# CONFIG_FSL_EDMA is not set
CONFIG_HISI_DMA=y
CONFIG_IMG_MDC_DMA=y
CONFIG_INTEL_IDMA64=y
CONFIG_INTEL_IOP_ADMA=y
CONFIG_K3_DMA=y
# CONFIG_MCF_EDMA is not set
# CONFIG_MILBEAUT_HDMAC is not set
CONFIG_MILBEAUT_XDMAC=y
CONFIG_MMP_PDMA=y
CONFIG_MMP_TDMA=y
# CONFIG_MV_XOR is not set
# CONFIG_MXS_DMA is not set
CONFIG_NBPFAXI_DMA=y
CONFIG_PCH_DMA=y
CONFIG_PLX_DMA=y
# CONFIG_STM32_DMA is not set
CONFIG_STM32_DMAMUX=y
CONFIG_STM32_MDMA=y
CONFIG_SPRD_DMA=y
CONFIG_S3C24XX_DMAC=y
# CONFIG_TEGRA186_GPC_DMA is not set
# CONFIG_TEGRA20_APB_DMA is not set
CONFIG_TEGRA210_ADMA=y
CONFIG_TIMB_DMA=y
CONFIG_UNIPHIER_MDMAC=y
# CONFIG_UNIPHIER_XDMAC is not set
# CONFIG_XGENE_DMA is not set
CONFIG_XILINX_ZYNQMP_DMA=y
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_MTK_HSDMA is not set
# CONFIG_MTK_CQDMA is not set
CONFIG_QCOM_HIDMA_MGMT=y
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
CONFIG_RZN1_DMAMUX=y
CONFIG_DW_DMAC_PCI=y
CONFIG_DW_EDMA=y
CONFIG_DW_EDMA_PCIE=y
# CONFIG_SF_PDMA is not set
CONFIG_RENESAS_DMA=y
CONFIG_SH_DMAE_BASE=y
# CONFIG_SH_DMAE is not set
CONFIG_RCAR_DMAC=y
# CONFIG_RENESAS_USB_DMAC is not set
# CONFIG_RZ_DMAC is not set
CONFIG_TI_EDMA=y
CONFIG_DMA_OMAP=y
CONFIG_TI_DMA_CROSSBAR=y
# CONFIG_INTEL_LDMA is not set

#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
# CONFIG_UDMABUF is not set
CONFIG_DMABUF_MOVE_NOTIFY=y
CONFIG_DMABUF_DEBUG=y
CONFIG_DMABUF_SELFTESTS=y
# CONFIG_DMABUF_HEAPS is not set
CONFIG_DMABUF_SYSFS_STATS=y
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=y
CONFIG_LINEDISP=y
CONFIG_HD44780_COMMON=y
CONFIG_HD44780=y
# CONFIG_IMG_ASCII_LCD is not set
# CONFIG_HT16K33 is not set
CONFIG_LCD2S=y
CONFIG_PARPORT_PANEL=y
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_PANEL=y
CONFIG_UIO=y
# CONFIG_UIO_CIF is not set
CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_UIO_AEC=y
CONFIG_UIO_SERCOS3=y
CONFIG_UIO_PCI_GENERIC=y
CONFIG_UIO_NETX=y
CONFIG_UIO_PRUSS=y
# CONFIG_UIO_MF624 is not set
CONFIG_VFIO=y
CONFIG_VFIO_VIRQFD=y
CONFIG_VFIO_NOIOMMU=y
CONFIG_VFIO_PCI_CORE=y
CONFIG_VFIO_PCI_MMAP=y
CONFIG_VFIO_PCI_INTX=y
CONFIG_VFIO_PCI=y
# CONFIG_VFIO_PLATFORM is not set
CONFIG_VFIO_MDEV=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=y
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_VDPA=y
# CONFIG_VIRTIO_BALLOON is not set
# CONFIG_VIRTIO_INPUT is not set
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VDPA=y
# CONFIG_VDPA_USER is not set
CONFIG_IFCVF=y
CONFIG_VP_VDPA=y
# CONFIG_VHOST_MENU is not set

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

CONFIG_GREYBUS=y
CONFIG_GREYBUS_ES2=y
# CONFIG_COMEDI is not set
CONFIG_STAGING=y

#
# IIO staging drivers
#

#
# Accelerometers
#
# end of Accelerometers

#
# Analog to digital converters
#
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=y
CONFIG_ADT7316_I2C=y
# end of Analog digital bi-direction converters

#
# Capacitance to digital converters
#
CONFIG_AD7746=y
# end of Capacitance to digital converters

#
# Direct Digital Synthesis
#
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=y
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# end of Resolver to digital converters
# end of IIO staging drivers

CONFIG_FB_SM750=y
CONFIG_USB_EMXX=y
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_SUNXI=y
CONFIG_STAGING_BOARD=y
CONFIG_COMMON_CLK_XLNX_CLKWZRD=y
# CONFIG_MOST_COMPONENTS is not set
CONFIG_GREYBUS_AUDIO=y
# CONFIG_GREYBUS_AUDIO_APB_CODEC is not set
CONFIG_GREYBUS_BOOTROM=y
# CONFIG_GREYBUS_HID is not set
CONFIG_GREYBUS_LIGHT=y
CONFIG_GREYBUS_LOG=y
# CONFIG_GREYBUS_LOOPBACK is not set
CONFIG_GREYBUS_POWER=y
CONFIG_GREYBUS_RAW=y
CONFIG_GREYBUS_VIBRATOR=y
# CONFIG_GREYBUS_BRIDGED_PHY is not set
CONFIG_GREYBUS_ARCHE=y
CONFIG_BCM_VIDEOCORE=y
CONFIG_BCM2835_VCHIQ=y
CONFIG_VCHIQ_CDEV=y
CONFIG_SND_BCM2835=y
CONFIG_BCM2835_VCHIQ_MMAL=y
CONFIG_XIL_AXIS_FIFO=y
CONFIG_FIELDBUS_DEV=y
# CONFIG_HMS_ANYBUSS_BUS is not set
CONFIG_VME_BUS=y

#
# VME Bridge Drivers
#
CONFIG_VME_TSI148=y
CONFIG_VME_FAKE=y

#
# VME Device Drivers
#
# CONFIG_VME_USER is not set
CONFIG_GOLDFISH=y
CONFIG_GOLDFISH_PIPE=y
CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_RPMSG=y
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=y
CONFIG_CROS_KUNIT=y
# CONFIG_MELLANOX_PLATFORM is not set
# CONFIG_OLPC_XO175 is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_WM831X is not set

#
# Clock driver for ARM Reference designs
#
CONFIG_CLK_ICST=y
CONFIG_CLK_SP810=y
# end of Clock driver for ARM Reference designs

CONFIG_CLK_HSDK=y
CONFIG_COMMON_CLK_APPLE_NCO=y
CONFIG_COMMON_CLK_MAX77686=y
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_HI655X=y
# CONFIG_COMMON_CLK_SCMI is not set
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
CONFIG_COMMON_CLK_SI5351=y
# CONFIG_COMMON_CLK_SI514 is not set
CONFIG_COMMON_CLK_SI544=y
CONFIG_COMMON_CLK_SI570=y
# CONFIG_COMMON_CLK_BM1880 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_TPS68470 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_COMMON_CLK_EN7523 is not set
CONFIG_COMMON_CLK_FSL_FLEXSPI=y
CONFIG_COMMON_CLK_FSL_SAI=y
CONFIG_COMMON_CLK_GEMINI=y
# CONFIG_COMMON_CLK_LAN966X is not set
CONFIG_COMMON_CLK_ASPEED=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_COMMON_CLK_AXI_CLKGEN=y
# CONFIG_CLK_QORIQ is not set
CONFIG_CLK_LS1028A_PLLDIG=y
# CONFIG_COMMON_CLK_XGENE is not set
# CONFIG_COMMON_CLK_PWM is not set
# CONFIG_COMMON_CLK_OXNAS is not set
CONFIG_COMMON_CLK_RS9_PCIE=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_MMP2_AUDIO is not set
# CONFIG_COMMON_CLK_BD718XX is not set
CONFIG_COMMON_CLK_FIXED_MMIO=y
CONFIG_CLK_ACTIONS=y
CONFIG_CLK_OWL_S500=y
CONFIG_CLK_OWL_S700=y
CONFIG_CLK_OWL_S900=y
# CONFIG_CLK_BAIKAL_T1 is not set
# CONFIG_CLK_BCM2711_DVP is not set
CONFIG_CLK_BCM2835=y
CONFIG_CLK_BCM_63XX=y
CONFIG_CLK_BCM_63XX_GATE=y
# CONFIG_CLK_BCM_KONA is not set
CONFIG_COMMON_CLK_IPROC=y
CONFIG_CLK_BCM_CYGNUS=y
# CONFIG_CLK_BCM_HR2 is not set
CONFIG_CLK_BCM_NSP=y
# CONFIG_CLK_BCM_NS2 is not set
# CONFIG_CLK_BCM_SR is not set
CONFIG_CLK_RASPBERRYPI=y
# CONFIG_COMMON_CLK_HI3516CV300 is not set
CONFIG_COMMON_CLK_HI3519=y
# CONFIG_COMMON_CLK_HI3559A is not set
CONFIG_COMMON_CLK_HI3660=y
CONFIG_COMMON_CLK_HI3670=y
# CONFIG_COMMON_CLK_HI3798CV200 is not set
CONFIG_COMMON_CLK_HI6220=y
CONFIG_RESET_HISI=y
CONFIG_STUB_CLK_HI6220=y
# CONFIG_STUB_CLK_HI3660 is not set
CONFIG_COMMON_CLK_BOSTON=y
CONFIG_MXC_CLK=y
# CONFIG_CLK_IMX8MM is not set
CONFIG_CLK_IMX8MN=y
# CONFIG_CLK_IMX8MP is not set
CONFIG_CLK_IMX8MQ=y
# CONFIG_CLK_IMX8ULP is not set
# CONFIG_CLK_IMX93 is not set

#
# Ingenic SoCs drivers
#
CONFIG_INGENIC_CGU_COMMON=y
# CONFIG_INGENIC_CGU_JZ4740 is not set
CONFIG_INGENIC_CGU_JZ4725B=y
# CONFIG_INGENIC_CGU_JZ4760 is not set
CONFIG_INGENIC_CGU_JZ4770=y
# CONFIG_INGENIC_CGU_JZ4780 is not set
CONFIG_INGENIC_CGU_X1000=y
CONFIG_INGENIC_CGU_X1830=y
# CONFIG_INGENIC_TCU_CLK is not set
# end of Ingenic SoCs drivers

CONFIG_COMMON_CLK_KEYSTONE=y
CONFIG_TI_SYSCON_CLK=y

#
# Clock driver for MediaTek SoC
#
CONFIG_COMMON_CLK_MEDIATEK=y
# CONFIG_COMMON_CLK_MT2701 is not set
# CONFIG_COMMON_CLK_MT2712 is not set
CONFIG_COMMON_CLK_MT6765=y
# CONFIG_COMMON_CLK_MT6765_AUDIOSYS is not set
# CONFIG_COMMON_CLK_MT6765_CAMSYS is not set
# CONFIG_COMMON_CLK_MT6765_GCESYS is not set
# CONFIG_COMMON_CLK_MT6765_MMSYS is not set
CONFIG_COMMON_CLK_MT6765_IMGSYS=y
CONFIG_COMMON_CLK_MT6765_VCODECSYS=y
# CONFIG_COMMON_CLK_MT6765_MFGSYS is not set
# CONFIG_COMMON_CLK_MT6765_MIPI0ASYS is not set
# CONFIG_COMMON_CLK_MT6765_MIPI0BSYS is not set
CONFIG_COMMON_CLK_MT6765_MIPI1ASYS=y
CONFIG_COMMON_CLK_MT6765_MIPI1BSYS=y
# CONFIG_COMMON_CLK_MT6765_MIPI2ASYS is not set
# CONFIG_COMMON_CLK_MT6765_MIPI2BSYS is not set
CONFIG_COMMON_CLK_MT6779=y
# CONFIG_COMMON_CLK_MT6779_MMSYS is not set
# CONFIG_COMMON_CLK_MT6779_IMGSYS is not set
CONFIG_COMMON_CLK_MT6779_IPESYS=y
# CONFIG_COMMON_CLK_MT6779_CAMSYS is not set
CONFIG_COMMON_CLK_MT6779_VDECSYS=y
# CONFIG_COMMON_CLK_MT6779_VENCSYS is not set
CONFIG_COMMON_CLK_MT6779_MFGCFG=y
CONFIG_COMMON_CLK_MT6779_AUDSYS=y
CONFIG_COMMON_CLK_MT6797=y
# CONFIG_COMMON_CLK_MT6797_MMSYS is not set
CONFIG_COMMON_CLK_MT6797_IMGSYS=y
# CONFIG_COMMON_CLK_MT6797_VDECSYS is not set
CONFIG_COMMON_CLK_MT6797_VENCSYS=y
# CONFIG_COMMON_CLK_MT7622 is not set
CONFIG_COMMON_CLK_MT7629=y
CONFIG_COMMON_CLK_MT7629_ETHSYS=y
# CONFIG_COMMON_CLK_MT7629_HIFSYS is not set
CONFIG_COMMON_CLK_MT7986=y
CONFIG_COMMON_CLK_MT7986_ETHSYS=y
# CONFIG_COMMON_CLK_MT8135 is not set
# CONFIG_COMMON_CLK_MT8167 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8183 is not set
CONFIG_COMMON_CLK_MT8186=y
# CONFIG_COMMON_CLK_MT8192 is not set
CONFIG_COMMON_CLK_MT8195=y
# CONFIG_COMMON_CLK_MT8516 is not set
# end of Clock driver for MediaTek SoC

#
# Clock support for Amlogic platforms
#
# CONFIG_COMMON_CLK_AXG_AUDIO is not set
# end of Clock support for Amlogic platforms

# CONFIG_MSTAR_MSC313_MPLL is not set
CONFIG_MCHP_CLK_MPFS=y
# CONFIG_COMMON_CLK_PISTACHIO is not set
# CONFIG_COMMON_CLK_QCOM is not set
# CONFIG_CLK_MT7621 is not set
# CONFIG_CLK_RENESAS is not set
CONFIG_COMMON_CLK_SAMSUNG=y
CONFIG_S3C64XX_COMMON_CLK=y
# CONFIG_S5PV210_COMMON_CLK is not set
CONFIG_EXYNOS_3250_COMMON_CLK=y
CONFIG_EXYNOS_4_COMMON_CLK=y
# CONFIG_EXYNOS_5250_COMMON_CLK is not set
# CONFIG_EXYNOS_5260_COMMON_CLK is not set
# CONFIG_EXYNOS_5410_COMMON_CLK is not set
CONFIG_EXYNOS_5420_COMMON_CLK=y
CONFIG_EXYNOS_ARM64_COMMON_CLK=y
# CONFIG_EXYNOS_AUDSS_CLK_CON is not set
CONFIG_EXYNOS_CLKOUT=y
# CONFIG_S3C2410_COMMON_CLK is not set
CONFIG_S3C2412_COMMON_CLK=y
CONFIG_S3C2443_COMMON_CLK=y
CONFIG_TESLA_FSD_COMMON_CLK=y
# CONFIG_CLK_SIFIVE is not set
CONFIG_CLK_INTEL_SOCFPGA=y
CONFIG_CLK_INTEL_SOCFPGA32=y
CONFIG_CLK_INTEL_SOCFPGA64=y
CONFIG_SPRD_COMMON_CLK=y
CONFIG_SPRD_SC9860_CLK=y
CONFIG_SPRD_SC9863A_CLK=y
CONFIG_CLK_STARFIVE=y
CONFIG_CLK_STARFIVE_JH7100=y
CONFIG_CLK_STARFIVE_JH7100_AUDIO=y
CONFIG_CLK_STARFIVE_JH7110_SYS=y
CONFIG_CLK_STARFIVE_JH7110_AON=y
CONFIG_CLK_SUNXI=y
# CONFIG_CLK_SUNXI_CLOCKS is not set
CONFIG_CLK_SUNXI_PRCM_SUN6I=y
# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
CONFIG_CLK_SUNXI_PRCM_SUN9I=y
CONFIG_SUNXI_CCU=y
# CONFIG_SUNIV_F1C100S_CCU is not set
CONFIG_SUN20I_D1_CCU=y
CONFIG_SUN20I_D1_R_CCU=y
CONFIG_SUN50I_A64_CCU=y
# CONFIG_SUN50I_A100_CCU is not set
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN4I_A10_CCU=y
CONFIG_SUN5I_CCU=y
CONFIG_SUN6I_A31_CCU=y
CONFIG_SUN6I_RTC_CCU=y
# CONFIG_SUN8I_A23_CCU is not set
# CONFIG_SUN8I_A33_CCU is not set
CONFIG_SUN8I_A83T_CCU=y
# CONFIG_SUN8I_H3_CCU is not set
CONFIG_SUN8I_V3S_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R40_CCU=y
# CONFIG_SUN9I_A80_CCU is not set
CONFIG_SUN8I_R_CCU=y
CONFIG_COMMON_CLK_TI_ADPLL=y
CONFIG_CLK_UNIPHIER=y
CONFIG_COMMON_CLK_VISCONTI=y
CONFIG_CLK_LGM_CGU=y
# CONFIG_XILINX_VCU is not set
CONFIG_COMMON_CLK_ZYNQMP=y
CONFIG_CLK_KUNIT_TEST=y
CONFIG_CLK_GATE_KUNIT_TEST=y
# CONFIG_HWSPINLOCK is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
# CONFIG_BCM2835_TIMER is not set
CONFIG_BCM_KONA_TIMER=y
# CONFIG_DAVINCI_TIMER is not set
# CONFIG_DIGICOLOR_TIMER is not set
CONFIG_OMAP_DM_TIMER=y
# CONFIG_DW_APB_TIMER is not set
CONFIG_FTTMR010_TIMER=y
CONFIG_IXP4XX_TIMER=y
CONFIG_MESON6_TIMER=y
CONFIG_OWL_TIMER=y
CONFIG_RDA_TIMER=y
CONFIG_SUN4I_TIMER=y
# CONFIG_SUN5I_HSTIMER is not set
# CONFIG_TEGRA_TIMER is not set
# CONFIG_TEGRA186_TIMER is not set
CONFIG_VT8500_TIMER=y
# CONFIG_NPCM7XX_TIMER is not set
CONFIG_CADENCE_TTC_TIMER=y
# CONFIG_ASM9260_TIMER is not set
# CONFIG_CLKSRC_DBX500_PRCMU is not set
CONFIG_CLPS711X_TIMER=y
# CONFIG_MXS_TIMER is not set
# CONFIG_NSPIRE_TIMER is not set
CONFIG_INTEGRATOR_AP_TIMER=y
# CONFIG_CLKSRC_PISTACHIO is not set
CONFIG_CLKSRC_TI_32K=y
CONFIG_CLKSRC_STM32_LP=y
CONFIG_CLKSRC_MPS2=y
# CONFIG_ARC_TIMERS is not set
# CONFIG_ARM_TIMER_SP804 is not set
CONFIG_ARMV7M_SYSTICK=y
CONFIG_ATMEL_PIT=y
CONFIG_ATMEL_ST=y
CONFIG_CLKSRC_SAMSUNG_PWM=y
CONFIG_FSL_FTM_TIMER=y
CONFIG_OXNAS_RPS_TIMER=y
# CONFIG_MTK_TIMER is not set
CONFIG_SPRD_TIMER=y
# CONFIG_CLKSRC_JCORE_PIT is not set
# CONFIG_SH_TIMER_CMT is not set
CONFIG_SH_TIMER_MTU2=y
CONFIG_RENESAS_OSTM=y
# CONFIG_SH_TIMER_TMU is not set
CONFIG_EM_TIMER_STI=y
CONFIG_CLKSRC_VERSATILE=y
CONFIG_CLKSRC_PXA=y
# CONFIG_TIMER_IMX_SYS_CTR is not set
CONFIG_CLKSRC_ST_LPC=y
# CONFIG_GXP_TIMER is not set
CONFIG_RISCV_TIMER=y
CONFIG_CLINT_TIMER=y
# CONFIG_MSC313E_TIMER is not set
CONFIG_INGENIC_TIMER=y
# CONFIG_INGENIC_SYSOST is not set
CONFIG_INGENIC_OST=y
# CONFIG_MICROCHIP_PIT64B is not set
CONFIG_GOLDFISH_TIMER=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_IMX_MBOX=y
# CONFIG_PLATFORM_MHU is not set
CONFIG_ARMADA_37XX_RWTM_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ALTERA_MBOX=y
CONFIG_HI3660_MBOX=y
CONFIG_HI6220_MBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_POLARFIRE_SOC_MAILBOX=y
CONFIG_QCOM_APCS_IPC=y
CONFIG_BCM_PDC_MBOX=y
CONFIG_STM32_IPCC=y
CONFIG_MTK_ADSP_MBOX=y
# CONFIG_MTK_CMDQ_MBOX is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_SPRD_MBOX=y
# CONFIG_QCOM_IPCC is not set
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST=y
# end of Generic IOMMU Pagetable Support

CONFIG_IOMMU_DEBUGFS=y
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
CONFIG_OF_IOMMU=y
CONFIG_OMAP_IOMMU=y
# CONFIG_OMAP_IOMMU_DEBUG is not set
CONFIG_ROCKCHIP_IOMMU=y
# CONFIG_SUN50I_IOMMU is not set
# CONFIG_EXYNOS_IOMMU is not set
CONFIG_IPMMU_VMSA=y
CONFIG_APPLE_DART=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS=y
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
# CONFIG_S390_CCW_IOMMU is not set
CONFIG_S390_AP_IOMMU=y
CONFIG_MTK_IOMMU=y
CONFIG_QCOM_IOMMU=y
CONFIG_SPRD_IOMMU=y

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
# CONFIG_INGENIC_VPU_RPROC is not set
CONFIG_MTK_SCP=y
CONFIG_MESON_MX_AO_ARC_REMOTEPROC=y
CONFIG_RCAR_REMOTEPROC=y
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_NS=y
CONFIG_RPMSG_MTK_SCP=y
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_VIRTIO=y
# end of Rpmsg drivers

CONFIG_SOUNDWIRE=y

#
# SoundWire Devices
#
CONFIG_SOUNDWIRE_QCOM=y

#
# SOC (System On Chip) specific Drivers
#
# CONFIG_OWL_PM_DOMAINS is not set

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
# CONFIG_MESON_CLK_MEASURE is not set
# CONFIG_MESON_GX_SOCINFO is not set
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=y
CONFIG_MESON_MX_SOCINFO=y
# end of Amlogic SoC drivers

#
# Apple SoC drivers
#
# CONFIG_APPLE_PMGR_PWRSTATE is not set
CONFIG_APPLE_RTKIT=y
# CONFIG_APPLE_SART is not set
# end of Apple SoC drivers

#
# ASPEED SoC drivers
#
CONFIG_ASPEED_LPC_CTRL=y
CONFIG_ASPEED_LPC_SNOOP=y
CONFIG_ASPEED_UART_ROUTING=y
CONFIG_ASPEED_P2A_CTRL=y
CONFIG_ASPEED_SOCINFO=y
# end of ASPEED SoC drivers

CONFIG_AT91_SOC_ID=y
CONFIG_AT91_SOC_SFR=y

#
# Broadcom SoC drivers
#
# CONFIG_BCM2835_POWER is not set
CONFIG_SOC_BCM63XX=y
CONFIG_SOC_BRCMSTB=y
# CONFIG_BCM63XX_POWER is not set
CONFIG_BCM_PMB=y
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
CONFIG_FSL_GUTS=y
CONFIG_DPAA2_CONSOLE=y
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
CONFIG_IMX_GPCV2_PM_DOMAINS=y
# CONFIG_SOC_IMX8M is not set
# end of i.MX SoC drivers

#
# IXP4xx SoC drivers
#
CONFIG_IXP4XX_QMGR=y
# CONFIG_IXP4XX_NPE is not set
# end of IXP4xx SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
CONFIG_LITEX=y
CONFIG_LITEX_SOC_CONTROLLER=y
# end of Enable LiteX SoC Builder specific drivers

#
# MediaTek SoC drivers
#
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_DEVAPC=y
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=y
# CONFIG_MTK_SCPSYS is not set
# CONFIG_MTK_SCPSYS_PM_DOMAINS is not set
CONFIG_MTK_MMSYS=y
# end of MediaTek SoC drivers

# CONFIG_POLARFIRE_SOC_SYS_CTRL is not set

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_AOSS_QMP=y
CONFIG_QCOM_COMMAND_DB=y
# CONFIG_QCOM_GENI_SE is not set
CONFIG_QCOM_GSBI=y
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_PDR_HELPERS=y
CONFIG_QCOM_QMI_HELPERS=y
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_RPMPD=y
CONFIG_QCOM_SMD_RPM=y
# CONFIG_QCOM_SPM is not set
# CONFIG_QCOM_WCNSS_CTRL is not set
CONFIG_QCOM_APR=y
# CONFIG_QCOM_ICC_BWMON is not set
# end of Qualcomm SoC drivers

# CONFIG_SOC_RENESAS is not set
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
# CONFIG_ROCKCHIP_PM_DOMAINS is not set
# CONFIG_SOC_SAMSUNG is not set
CONFIG_SIFIVE_L2=y
# CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER is not set
# CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER is not set
CONFIG_SOC_TI=y
# CONFIG_UX500_SOC_ID is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
# CONFIG_ARM_TEGRA_DEVFREQ is not set
# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set
# CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set
CONFIG_PM_DEVFREQ_EVENT=y
# CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set
CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y
# CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=y
CONFIG_EXTCON_FSA9480=y
# CONFIG_EXTCON_GPIO is not set
CONFIG_EXTCON_MAX3355=y
# CONFIG_EXTCON_MAX77843 is not set
CONFIG_EXTCON_PTN5150=y
CONFIG_EXTCON_QCOM_SPMI_MISC=y
CONFIG_EXTCON_RT8973A=y
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
CONFIG_EXTCON_USBC_CROS_EC=y
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_MEMORY=y
CONFIG_DDR=y
CONFIG_ATMEL_SDRAMC=y
# CONFIG_ATMEL_EBI is not set
CONFIG_BRCMSTB_DPFE=y
# CONFIG_BT1_L2_CTL is not set
# CONFIG_TI_AEMIF is not set
CONFIG_TI_EMIF=y
CONFIG_OMAP_GPMC=y
# CONFIG_OMAP_GPMC_DEBUG is not set
# CONFIG_MVEBU_DEVBUS is not set
CONFIG_FSL_CORENET_CF=y
CONFIG_FSL_IFC=y
CONFIG_JZ4780_NEMC=y
CONFIG_MTK_SMI=y
CONFIG_DA8XX_DDRCTL=y
CONFIG_RENESAS_RPCIF=y
# CONFIG_STM32_FMC2_EBI is not set
CONFIG_SAMSUNG_MC=y
CONFIG_EXYNOS5422_DMC=y
CONFIG_EXYNOS_SROM=y
CONFIG_TEGRA_MC=y
CONFIG_TEGRA20_EMC=y
CONFIG_TEGRA30_EMC=y
# CONFIG_TEGRA124_EMC is not set
CONFIG_TEGRA210_EMC_TABLE=y
CONFIG_TEGRA210_EMC=y
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_BUFFER_DMA=y
# CONFIG_IIO_BUFFER_DMAENGINE is not set
CONFIG_IIO_BUFFER_HW_CONSUMER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=y
# CONFIG_IIO_SW_TRIGGER is not set
CONFIG_IIO_TRIGGERED_EVENT=y

#
# Accelerometers
#
CONFIG_ADXL313=y
CONFIG_ADXL313_I2C=y
CONFIG_ADXL345=y
CONFIG_ADXL345_I2C=y
CONFIG_ADXL355=y
CONFIG_ADXL355_I2C=y
CONFIG_ADXL367=y
CONFIG_ADXL367_I2C=y
# CONFIG_ADXL372_I2C is not set
CONFIG_BMA180=y
# CONFIG_BMA400 is not set
CONFIG_BMC150_ACCEL=y
CONFIG_BMC150_ACCEL_I2C=y
CONFIG_DA280=y
# CONFIG_DA311 is not set
CONFIG_DMARD06=y
CONFIG_DMARD09=y
CONFIG_DMARD10=y
# CONFIG_FXLS8962AF_I2C is not set
CONFIG_HID_SENSOR_ACCEL_3D=y
# CONFIG_KXSD9 is not set
CONFIG_KXCJK1013=y
CONFIG_MC3230=y
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7660 is not set
# CONFIG_MMA8452 is not set
CONFIG_MMA9551_CORE=y
CONFIG_MMA9551=y
# CONFIG_MMA9553 is not set
# CONFIG_MXC4005 is not set
# CONFIG_MXC6255 is not set
CONFIG_STK8312=y
CONFIG_STK8BA50=y
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD7091R5=y
CONFIG_AD7291=y
CONFIG_AD7606=y
CONFIG_AD7606_IFACE_PARALLEL=y
CONFIG_AD799X=y
# CONFIG_ADI_AXI_ADC is not set
# CONFIG_ASPEED_ADC is not set
CONFIG_AT91_ADC=y
# CONFIG_AT91_SAMA5D2_ADC is not set
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
CONFIG_BCM_IPROC_ADC=y
CONFIG_BERLIN2_ADC=y
CONFIG_CC10001_ADC=y
CONFIG_DLN2_ADC=y
CONFIG_ENVELOPE_DETECTOR=y
CONFIG_EXYNOS_ADC=y
# CONFIG_MXS_LRADC_ADC is not set
# CONFIG_FSL_MX25_ADC is not set
CONFIG_HX711=y
CONFIG_INGENIC_ADC=y
# CONFIG_IMX7D_ADC is not set
CONFIG_IMX8QXP_ADC=y
# CONFIG_LP8788_ADC is not set
CONFIG_LPC18XX_ADC=y
CONFIG_LPC32XX_ADC=y
CONFIG_LTC2471=y
CONFIG_LTC2485=y
CONFIG_LTC2497=y
# CONFIG_MAX1363 is not set
CONFIG_MAX9611=y
CONFIG_MCP3422=y
CONFIG_MEDIATEK_MT6360_ADC=y
# CONFIG_MEDIATEK_MT6577_AUXADC is not set
CONFIG_MEN_Z188_ADC=y
CONFIG_MESON_SARADC=y
CONFIG_MP2629_ADC=y
CONFIG_NAU7802=y
CONFIG_NPCM_ADC=y
CONFIG_QCOM_VADC_COMMON=y
CONFIG_QCOM_PM8XXX_XOADC=y
CONFIG_QCOM_SPMI_RRADC=y
# CONFIG_QCOM_SPMI_IADC is not set
CONFIG_QCOM_SPMI_VADC=y
CONFIG_QCOM_SPMI_ADC5=y
# CONFIG_RCAR_GYRO_ADC is not set
CONFIG_RN5T618_ADC=y
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_RZG2L_ADC is not set
CONFIG_SC27XX_ADC=y
CONFIG_SPEAR_ADC=y
# CONFIG_SD_ADC_MODULATOR is not set
CONFIG_STM32_ADC_CORE=y
CONFIG_STM32_ADC=y
CONFIG_STM32_DFSDM_CORE=y
# CONFIG_STM32_DFSDM_ADC is not set
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADS1015 is not set
CONFIG_TWL4030_MADC=y
CONFIG_TWL6030_GPADC=y
# CONFIG_VF610_ADC is not set
CONFIG_VIPERBOARD_ADC=y
CONFIG_XILINX_XADC=y
CONFIG_XILINX_AMS=y
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=y
# end of Analog Front Ends

#
# Amplifiers
#
# CONFIG_HMC425 is not set
# end of Amplifiers

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=y
CONFIG_ATLAS_EZO_SENSOR=y
CONFIG_BME680=y
CONFIG_BME680_I2C=y
# CONFIG_CCS811 is not set
CONFIG_IAQCORE=y
# CONFIG_SCD30_CORE is not set
# CONFIG_SCD4X is not set
# CONFIG_SENSIRION_SGP30 is not set
# CONFIG_SENSIRION_SGP40 is not set
CONFIG_SPS30=y
CONFIG_SPS30_I2C=y
CONFIG_SENSEAIR_SUNRISE_CO2=y
# CONFIG_VZ89X is not set
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=y
CONFIG_HID_SENSOR_IIO_TRIGGER=y
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=y

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=y
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=y
CONFIG_IIO_ST_SENSORS_CORE=y

#
# Digital to analog converters
#
CONFIG_AD5064=y
CONFIG_AD5380=y
# CONFIG_AD5446 is not set
CONFIG_AD5592R_BASE=y
CONFIG_AD5593R=y
CONFIG_AD5686=y
CONFIG_AD5696_I2C=y
CONFIG_DPOT_DAC=y
# CONFIG_DS4424 is not set
# CONFIG_LPC18XX_DAC is not set
CONFIG_M62332=y
CONFIG_MAX517=y
# CONFIG_MAX5821 is not set
CONFIG_MCP4725=y
CONFIG_STM32_DAC=y
CONFIG_STM32_DAC_CORE=y
CONFIG_TI_DAC5571=y
# CONFIG_VF610_DAC is not set
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_BMG160=y
CONFIG_BMG160_I2C=y
CONFIG_FXAS21002C=y
CONFIG_FXAS21002C_I2C=y
CONFIG_HID_SENSOR_GYRO_3D=y
CONFIG_MPU3050=y
CONFIG_MPU3050_I2C=y
CONFIG_IIO_ST_GYRO_3AXIS=y
CONFIG_IIO_ST_GYRO_I2C_3AXIS=y
# CONFIG_ITG3200 is not set
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
# CONFIG_AFE4404 is not set
CONFIG_MAX30100=y
# CONFIG_MAX30102 is not set
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=y
CONFIG_DHT11=y
CONFIG_HDC100X=y
CONFIG_HDC2010=y
CONFIG_HID_SENSOR_HUMIDITY=y
# CONFIG_HTS221 is not set
CONFIG_HTU21=y
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_BMI160=y
CONFIG_BMI160_I2C=y
CONFIG_FXOS8700=y
CONFIG_FXOS8700_I2C=y
CONFIG_KMX61=y
CONFIG_INV_ICM42600=y
CONFIG_INV_ICM42600_I2C=y
CONFIG_INV_MPU6050_IIO=y
CONFIG_INV_MPU6050_I2C=y
CONFIG_IIO_ST_LSM6DSX=y
CONFIG_IIO_ST_LSM6DSX_I2C=y
CONFIG_IIO_ST_LSM6DSX_I3C=y
# end of Inertial measurement units

#
# Light sensors
#
# CONFIG_ADJD_S311 is not set
# CONFIG_ADUX1020 is not set
# CONFIG_AL3010 is not set
CONFIG_AL3320A=y
CONFIG_APDS9300=y
CONFIG_APDS9960=y
CONFIG_AS73211=y
# CONFIG_BH1750 is not set
CONFIG_BH1780=y
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
CONFIG_CM3605=y
# CONFIG_CM36651 is not set
# CONFIG_GP2AP002 is not set
CONFIG_GP2AP020A00F=y
CONFIG_IQS621_ALS=y
CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_ISL29028=y
# CONFIG_ISL29125 is not set
# CONFIG_HID_SENSOR_ALS is not set
CONFIG_HID_SENSOR_PROX=y
CONFIG_JSA1212=y
CONFIG_RPR0521=y
# CONFIG_SENSORS_LM3533 is not set
CONFIG_LTR501=y
CONFIG_LV0104CS=y
CONFIG_MAX44000=y
CONFIG_MAX44009=y
# CONFIG_NOA1305 is not set
CONFIG_OPT3001=y
CONFIG_PA12203001=y
CONFIG_SI1133=y
# CONFIG_SI1145 is not set
# CONFIG_STK3310 is not set
# CONFIG_ST_UVIS25 is not set
CONFIG_TCS3414=y
# CONFIG_TCS3472 is not set
CONFIG_SENSORS_TSL2563=y
CONFIG_TSL2583=y
CONFIG_TSL2591=y
CONFIG_TSL2772=y
CONFIG_TSL4531=y
# CONFIG_US5182D is not set
CONFIG_VCNL4000=y
CONFIG_VCNL4035=y
# CONFIG_VEML6030 is not set
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
CONFIG_ZOPT2201=y
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=y
CONFIG_AK8975=y
CONFIG_AK09911=y
CONFIG_BMC150_MAGN=y
CONFIG_BMC150_MAGN_I2C=y
CONFIG_MAG3110=y
CONFIG_HID_SENSOR_MAGNETOMETER_3D=y
CONFIG_MMC35240=y
CONFIG_IIO_ST_MAGN_3AXIS=y
CONFIG_IIO_ST_MAGN_I2C_3AXIS=y
CONFIG_SENSORS_HMC5843=y
CONFIG_SENSORS_HMC5843_I2C=y
# CONFIG_SENSORS_RM3100_I2C is not set
CONFIG_YAMAHA_YAS530=y
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=y
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=y
# CONFIG_HID_SENSOR_DEVICE_ROTATION is not set
# end of Inclinometer sensors

CONFIG_IIO_RESCALE_KUNIT_TEST=y
CONFIG_IIO_FORMAT_KUNIT_TEST=y

#
# Triggers - standalone
#
# CONFIG_IIO_INTERRUPT_TRIGGER is not set
CONFIG_IIO_STM32_LPTIMER_TRIGGER=y
CONFIG_IIO_STM32_TIMER_TRIGGER=y
# CONFIG_IIO_SYSFS_TRIGGER is not set
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_IQS624_POS=y
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=y
# end of Linear and angular position sensors

#
# Digital potentiometers
#
# CONFIG_AD5110 is not set
CONFIG_AD5272=y
# CONFIG_DS1803 is not set
CONFIG_MAX5432=y
CONFIG_MCP4018=y
CONFIG_MCP4531=y
CONFIG_TPL0102=y
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=y
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=y
CONFIG_BMP280=y
CONFIG_BMP280_I2C=y
CONFIG_DLHL60D=y
CONFIG_DPS310=y
CONFIG_HID_SENSOR_PRESS=y
# CONFIG_HP03 is not set
CONFIG_ICP10100=y
CONFIG_MPL115=y
CONFIG_MPL115_I2C=y
CONFIG_MPL3115=y
# CONFIG_MS5611 is not set
CONFIG_MS5637=y
# CONFIG_IIO_ST_PRESS is not set
CONFIG_T5403=y
CONFIG_HP206C=y
CONFIG_ZPA2326=y
CONFIG_ZPA2326_I2C=y
# end of Pressure sensors

#
# Lightning sensors
#
# end of Lightning sensors

#
# Proximity and distance sensors
#
CONFIG_CROS_EC_MKBP_PROXIMITY=y
CONFIG_ISL29501=y
CONFIG_LIDAR_LITE_V2=y
CONFIG_MB1232=y
CONFIG_PING=y
# CONFIG_RFD77402 is not set
CONFIG_SRF04=y
CONFIG_SX_COMMON=y
# CONFIG_SX9310 is not set
CONFIG_SX9324=y
CONFIG_SX9360=y
CONFIG_SX9500=y
CONFIG_SRF08=y
# CONFIG_VCNL3020 is not set
CONFIG_VL53L0X_I2C=y
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_IQS620AT_TEMP=y
CONFIG_HID_SENSOR_TEMP=y
CONFIG_MLX90614=y
# CONFIG_MLX90632 is not set
CONFIG_TMP006=y
# CONFIG_TMP007 is not set
CONFIG_TMP117=y
CONFIG_TSYS01=y
CONFIG_TSYS02D=y
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_DEBUG=y
CONFIG_PWM_ATMEL=y
CONFIG_PWM_ATMEL_HLCDC_PWM=y
CONFIG_PWM_ATMEL_TCB=y
CONFIG_PWM_BCM_IPROC=y
# CONFIG_PWM_BCM_KONA is not set
CONFIG_PWM_BCM2835=y
CONFIG_PWM_BERLIN=y
CONFIG_PWM_BRCMSTB=y
CONFIG_PWM_CLK=y
# CONFIG_PWM_CLPS711X is not set
# CONFIG_PWM_CROS_EC is not set
CONFIG_PWM_DWC=y
CONFIG_PWM_EP93XX=y
CONFIG_PWM_FSL_FTM=y
CONFIG_PWM_HIBVT=y
CONFIG_PWM_IMG=y
CONFIG_PWM_IMX1=y
CONFIG_PWM_IMX27=y
# CONFIG_PWM_IMX_TPM is not set
CONFIG_PWM_INTEL_LGM=y
CONFIG_PWM_IQS620A=y
CONFIG_PWM_JZ4740=y
CONFIG_PWM_KEEMBAY=y
CONFIG_PWM_LP3943=y
CONFIG_PWM_LPC18XX_SCT=y
CONFIG_PWM_LPC32XX=y
CONFIG_PWM_LPSS=y
CONFIG_PWM_LPSS_PCI=y
# CONFIG_PWM_LPSS_PLATFORM is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_MTK_DISP is not set
# CONFIG_PWM_MEDIATEK is not set
CONFIG_PWM_MXS=y
# CONFIG_PWM_NTXEC is not set
CONFIG_PWM_OMAP_DMTIMER=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_PXA=y
CONFIG_PWM_RASPBERRYPI_POE=y
CONFIG_PWM_RCAR=y
CONFIG_PWM_RENESAS_TPU=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SAMSUNG=y
CONFIG_PWM_SIFIVE=y
CONFIG_PWM_SL28CPLD=y
CONFIG_PWM_SPEAR=y
# CONFIG_PWM_SPRD is not set
CONFIG_PWM_STI=y
# CONFIG_PWM_STM32 is not set
CONFIG_PWM_STM32_LP=y
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_SUNPLUS is not set
CONFIG_PWM_TEGRA=y
CONFIG_PWM_TIECAP=y
CONFIG_PWM_TIEHRPWM=y
CONFIG_PWM_TWL=y
CONFIG_PWM_TWL_LED=y
CONFIG_PWM_VISCONTI=y
CONFIG_PWM_VT8500=y
CONFIG_PWM_XILINX=y

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
# CONFIG_AL_FIC is not set
CONFIG_MADERA_IRQ=y
CONFIG_JCORE_AIC=y
CONFIG_RENESAS_INTC_IRQPIN=y
# CONFIG_RENESAS_IRQC is not set
CONFIG_RENESAS_RZA1_IRQC=y
# CONFIG_RENESAS_RZG2L_IRQC is not set
CONFIG_SL28CPLD_INTC=y
CONFIG_TS4800_IRQ=y
# CONFIG_XILINX_INTC is not set
CONFIG_INGENIC_TCU_IRQ=y
CONFIG_IRQ_UNIPHIER_AIDET=y
CONFIG_MESON_IRQ_GPIO=y
CONFIG_IMX_IRQSTEER=y
# CONFIG_IMX_INTMUX is not set
CONFIG_RISCV_INTC=y
CONFIG_SIFIVE_PLIC=y
CONFIG_EXYNOS_IRQ_COMBINER=y
# CONFIG_MST_IRQ is not set
# CONFIG_MCHP_EIC is not set
CONFIG_SUNPLUS_SP7021_INTC=y
# end of IRQ chip support

CONFIG_IPACK_BUS=y
# CONFIG_BOARD_TPCI200 is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_A10SR=y
CONFIG_RESET_ATH79=y
CONFIG_RESET_AXS10X=y
CONFIG_RESET_BCM6345=y
CONFIG_RESET_BERLIN=y
CONFIG_RESET_BRCMSTB=y
CONFIG_RESET_BRCMSTB_RESCAL=y
CONFIG_RESET_HSDK=y
# CONFIG_RESET_IMX7 is not set
# CONFIG_RESET_INTEL_GW is not set
# CONFIG_RESET_K210 is not set
# CONFIG_RESET_LANTIQ is not set
# CONFIG_RESET_LPC18XX is not set
# CONFIG_RESET_MCHP_SPARX5 is not set
CONFIG_RESET_MESON=y
# CONFIG_RESET_MESON_AUDIO_ARB is not set
CONFIG_RESET_NPCM=y
# CONFIG_RESET_PISTACHIO is not set
CONFIG_RESET_QCOM_AOSS=y
CONFIG_RESET_QCOM_PDC=y
# CONFIG_RESET_RASPBERRYPI is not set
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
# CONFIG_RESET_SOCFPGA is not set
CONFIG_RESET_STARFIVE=y
CONFIG_RESET_SUNPLUS=y
CONFIG_RESET_SUNXI=y
CONFIG_RESET_TI_SCI=y
CONFIG_RESET_TI_SYSCON=y
CONFIG_RESET_TI_TPS380X=y
CONFIG_RESET_TN48M_CPLD=y
CONFIG_RESET_UNIPHIER=y
CONFIG_RESET_UNIPHIER_GLUE=y
CONFIG_RESET_ZYNQ=y
# CONFIG_COMMON_RESET_HI3660 is not set
CONFIG_COMMON_RESET_HI6220=y

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
CONFIG_PHY_LPC18XX_USB_OTG=y
# CONFIG_PHY_PISTACHIO_USB is not set
# CONFIG_PHY_XGENE is not set
CONFIG_USB_LGM_PHY=y
CONFIG_PHY_CAN_TRANSCEIVER=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
# CONFIG_PHY_SUN9I_USB is not set
CONFIG_PHY_SUN50I_USB3=y
# CONFIG_PHY_MESON8_HDMI_TX is not set
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
# CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG is not set
# CONFIG_PHY_MESON_G12A_USB2 is not set
# CONFIG_PHY_MESON_G12A_USB3_PCIE is not set
# CONFIG_PHY_MESON_AXG_PCIE is not set
# CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set
CONFIG_PHY_MESON_AXG_MIPI_DPHY=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_PHY_BCM63XX_USBH is not set
# CONFIG_PHY_CYGNUS_PCIE is not set
CONFIG_PHY_BCM_SR_USB=y
# CONFIG_BCM_KONA_USB2_PHY is not set
CONFIG_PHY_BCM_NS_USB2=y
# CONFIG_PHY_NS2_USB_DRD is not set
# CONFIG_PHY_BRCM_SATA is not set
CONFIG_PHY_BRCM_USB=y
CONFIG_PHY_BCM_SR_PCIE=y
# end of PHY drivers for Broadcom platforms

CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_CADENCE_DPHY=y
CONFIG_PHY_CADENCE_DPHY_RX=y
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
CONFIG_PHY_MIXEL_LVDS_PHY=y
CONFIG_PHY_MIXEL_MIPI_DPHY=y
CONFIG_PHY_FSL_IMX8M_PCIE=y
CONFIG_PHY_FSL_LYNX_28G=y
# CONFIG_PHY_HI6220_USB is not set
CONFIG_PHY_HI3660_USB=y
CONFIG_PHY_HI3670_USB=y
# CONFIG_PHY_HI3670_PCIE is not set
# CONFIG_PHY_HISTB_COMBPHY is not set
# CONFIG_PHY_HISI_INNO_USB2 is not set
CONFIG_PHY_INGENIC_USB=y
CONFIG_PHY_LANTIQ_VRX200_PCIE=y
CONFIG_PHY_LANTIQ_RCU_USB2=y
# CONFIG_ARMADA375_USBCLUSTER_PHY is not set
CONFIG_PHY_BERLIN_SATA=y
# CONFIG_PHY_BERLIN_USB is not set
# CONFIG_PHY_MVEBU_A3700_UTMI is not set
CONFIG_PHY_MVEBU_A38X_COMPHY=y
CONFIG_PHY_MVEBU_CP110_UTMI=y
CONFIG_PHY_PXA_28NM_HSIC=y
CONFIG_PHY_PXA_28NM_USB2=y
CONFIG_PHY_PXA_USB=y
CONFIG_PHY_MMP3_USB=y
# CONFIG_PHY_MMP3_HSIC is not set
CONFIG_PHY_MTK_PCIE=y
# CONFIG_PHY_MTK_TPHY is not set
# CONFIG_PHY_MTK_UFS is not set
CONFIG_PHY_MTK_XSPHY=y
CONFIG_PHY_MTK_HDMI=y
# CONFIG_PHY_MTK_MIPI_DSI is not set
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_SPARX5_SERDES is not set
CONFIG_PHY_LAN966X_SERDES=y
# CONFIG_PHY_CPCAP_USB is not set
CONFIG_PHY_MAPPHONE_MDM6600=y
CONFIG_PHY_OCELOT_SERDES=y
CONFIG_PHY_ATH79_USB=y
# CONFIG_PHY_QCOM_EDP is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
CONFIG_PHY_QCOM_PCIE2=y
CONFIG_PHY_QCOM_QMP=y
CONFIG_PHY_QCOM_QUSB2=y
# CONFIG_PHY_QCOM_USB_HS is not set
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_QCOM_USB_HS_28NM=y
CONFIG_PHY_QCOM_USB_SS=y
CONFIG_PHY_QCOM_IPQ806X_USB=y
CONFIG_PHY_MT7621_PCI=y
CONFIG_PHY_RALINK_USB=y
CONFIG_PHY_RCAR_GEN3_USB3=y
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_PCIE=y
# CONFIG_PHY_ROCKCHIP_TYPEC is not set
# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
CONFIG_PHY_EXYNOS_PCIE=y
CONFIG_PHY_SAMSUNG_UFS=y
CONFIG_PHY_SAMSUNG_USB2=y
CONFIG_PHY_S5PV210_USB2=y
CONFIG_PHY_UNIPHIER_USB2=y
# CONFIG_PHY_UNIPHIER_USB3 is not set
CONFIG_PHY_UNIPHIER_PCIE=y
CONFIG_PHY_UNIPHIER_AHCI=y
# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set
CONFIG_PHY_ST_SPEAR1340_MIPHY=y
CONFIG_PHY_STIH407_USB=y
CONFIG_PHY_STM32_USBPHYC=y
# CONFIG_PHY_TEGRA194_P2U is not set
CONFIG_PHY_DA8XX_USB=y
# CONFIG_PHY_DM816X_USB is not set
# CONFIG_PHY_AM654_SERDES is not set
CONFIG_PHY_J721E_WIZ=y
CONFIG_OMAP_CONTROL_PHY=y
# CONFIG_TI_PIPE3 is not set
CONFIG_PHY_TUSB1210=y
CONFIG_PHY_INTEL_KEEMBAY_EMMC=y
CONFIG_PHY_INTEL_KEEMBAY_USB=y
CONFIG_PHY_INTEL_LGM_COMBO=y
CONFIG_PHY_INTEL_LGM_EMMC=y
# CONFIG_PHY_INTEL_THUNDERBAY_EMMC is not set
# CONFIG_PHY_XILINX_ZYNQMP is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
CONFIG_MCB=y
# CONFIG_MCB_PCI is not set
CONFIG_MCB_LPC=y
CONFIG_RAS=y
CONFIG_USB4=y
CONFIG_USB4_DEBUGFS_WRITE=y
CONFIG_USB4_KUNIT_TEST=y
CONFIG_USB4_DMA_TEST=y

#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android

# CONFIG_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_IMX_IIM=y
CONFIG_NVMEM_IMX_OCOTP=y
# CONFIG_JZ4780_EFUSE is not set
CONFIG_NVMEM_LPC18XX_EEPROM=y
CONFIG_NVMEM_LPC18XX_OTP=y
# CONFIG_NVMEM_MXS_OCOTP is not set
# CONFIG_MTK_EFUSE is not set
# CONFIG_MICROCHIP_OTPC is not set
CONFIG_NVMEM_NINTENDO_OTP=y
# CONFIG_QCOM_QFPROM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
# CONFIG_ROCKCHIP_EFUSE is not set
# CONFIG_ROCKCHIP_OTP is not set
# CONFIG_NVMEM_BCM_OCOTP is not set
CONFIG_NVMEM_STM32_ROMEM=y
# CONFIG_UNIPHIER_EFUSE is not set
CONFIG_NVMEM_VF610_OCOTP=y
# CONFIG_MESON_MX_EFUSE is not set
# CONFIG_NVMEM_SNVS_LPGPR is not set
# CONFIG_SC27XX_EFUSE is not set
# CONFIG_SPRD_EFUSE is not set
# CONFIG_NVMEM_RMEM is not set
CONFIG_NVMEM_BRCM_NVRAM=y
# CONFIG_NVMEM_LAYERSCAPE_SFP is not set
CONFIG_NVMEM_SUNPLUS_OCOTP=y
CONFIG_NVMEM_APPLE_EFUSES=y

#
# HW tracing support
#
# CONFIG_STM is not set
CONFIG_INTEL_TH=y
CONFIG_INTEL_TH_PCI=y
CONFIG_INTEL_TH_GTH=y
# CONFIG_INTEL_TH_MSU is not set
# CONFIG_INTEL_TH_PTI is not set
CONFIG_INTEL_TH_DEBUG=y
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_GPIO is not set
CONFIG_MUX_MMIO=y
# end of Multiplexer drivers

CONFIG_PM_OPP=y
CONFIG_SIOX=y
CONFIG_SIOX_BUS_GPIO=y
CONFIG_SLIMBUS=y
# CONFIG_SLIM_QCOM_CTRL is not set
CONFIG_INTERCONNECT=y
# CONFIG_INTERCONNECT_IMX is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=y
# CONFIG_INTERCONNECT_SAMSUNG is not set
CONFIG_COUNTER=y
# CONFIG_104_QUAD_8 is not set
# CONFIG_INTERRUPT_CNT is not set
CONFIG_STM32_TIMER_CNT=y
CONFIG_STM32_LPTIMER_CNT=y
CONFIG_TI_EQEP=y
CONFIG_FTM_QUADDEC=y
# CONFIG_MICROCHIP_TCB_CAPTURE is not set
CONFIG_INTEL_QEP=y
CONFIG_MOST=y
CONFIG_MOST_USB_HDM=y
# CONFIG_MOST_CDEV is not set
# CONFIG_MOST_SND is not set
# CONFIG_PECI is not set
CONFIG_HTE=y
# end of Device Drivers

#
# File systems
#
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
# CONFIG_FILE_LOCKING is not set
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_VERITY=y
# CONFIG_FS_VERITY_DEBUG is not set
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=y
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set
# CONFIG_OVERLAY_FS_INDEX is not set
CONFIG_OVERLAY_FS_XINO_AUTO=y
CONFIG_OVERLAY_FS_METACOPY=y

#
# Caches
#
CONFIG_NETFS_SUPPORT=y
CONFIG_NETFS_STATS=y
# CONFIG_FSCACHE is not set
# end of Caches

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
# CONFIG_PROC_SYSCTL is not set
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
# CONFIG_HUGETLBFS is not set
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NETWORK_FILESYSTEMS=y
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
CONFIG_CODA_FS=y
CONFIG_AFS_FS=y
# CONFIG_AFS_DEBUG is not set
# CONFIG_AFS_DEBUG_CURSOR is not set
# CONFIG_9P_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
# CONFIG_NLS_CODEPAGE_850 is not set
CONFIG_NLS_CODEPAGE_852=y
# CONFIG_NLS_CODEPAGE_855 is not set
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_ISO8859_4=y
# CONFIG_NLS_ISO8859_5 is not set
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
CONFIG_NLS_ISO8859_14=y
# CONFIG_NLS_ISO8859_15 is not set
CONFIG_NLS_KOI8_R=y
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
CONFIG_NLS_MAC_CELTIC=y
CONFIG_NLS_MAC_CENTEURO=y
# CONFIG_NLS_MAC_CROATIAN is not set
CONFIG_NLS_MAC_CYRILLIC=y
CONFIG_NLS_MAC_GAELIC=y
CONFIG_NLS_MAC_GREEK=y
CONFIG_NLS_MAC_ICELAND=y
CONFIG_NLS_MAC_INUIT=y
CONFIG_NLS_MAC_ROMANIAN=y
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_REQUEST_CACHE=y
# CONFIG_PERSISTENT_KEYRINGS is not set
CONFIG_TRUSTED_KEYS=y

#
# No trust source selected!
#
CONFIG_ENCRYPTED_KEYS=y
# CONFIG_USER_DECRYPTED_DATA is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_KEY_NOTIFICATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
CONFIG_SECURITYFS=y
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_FORTIFY_SOURCE=y
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
# CONFIG_INIT_STACK_NONE is not set
CONFIG_INIT_STACK_ALL_PATTERN=y
# CONFIG_INIT_STACK_ALL_ZERO is not set
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization

CONFIG_CC_HAS_RANDSTRUCT=y
CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# end of Kernel hardening options
# end of Security options

CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=y
CONFIG_CRYPTO_ENGINE=y

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_ECDSA=y
CONFIG_CRYPTO_ECRDSA=y
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y

#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
# CONFIG_CRYPTO_AEGIS128 is not set
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
# CONFIG_CRYPTO_CFB is not set
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
# CONFIG_CRYPTO_OFB is not set
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XCTR=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=y
# CONFIG_CRYPTO_ADIANTUM is not set
CONFIG_CRYPTO_HCTR2=y
CONFIG_CRYPTO_ESSIV=y

#
# Hash modes
#
# CONFIG_CRYPTO_CMAC is not set
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_VMAC=y

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_XXHASH=y
# CONFIG_CRYPTO_BLAKE2B is not set
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLYVAL=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD160 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=y
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_CHACHA20=y
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_ARIA is not set
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
# CONFIG_CRYPTO_TWOFISH is not set

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_LZ4 is not set
CONFIG_CRYPTO_LZ4HC=y
# CONFIG_CRYPTO_ZSTD is not set

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# CONFIG_CRYPTO_STATS is not set
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ALLWINNER is not set
# CONFIG_CRYPTO_DEV_SL3516 is not set
# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set
# CONFIG_CRYPTO_DEV_S5P is not set
CONFIG_CRYPTO_DEV_ATMEL_AUTHENC=y
CONFIG_CRYPTO_DEV_ATMEL_AES=y
CONFIG_CRYPTO_DEV_ATMEL_TDES=y
CONFIG_CRYPTO_DEV_ATMEL_SHA=y
CONFIG_CRYPTO_DEV_ATMEL_I2C=y
CONFIG_CRYPTO_DEV_ATMEL_ECC=y
CONFIG_CRYPTO_DEV_ATMEL_SHA204A=y
CONFIG_CRYPTO_DEV_QAT=y
CONFIG_CRYPTO_DEV_QAT_DH895xCC=y
CONFIG_CRYPTO_DEV_QAT_C3XXX=y
CONFIG_CRYPTO_DEV_QAT_C62X=y
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=y
CONFIG_CRYPTO_DEV_QAT_C3XXXVF=y
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CAVIUM_CPT is not set
CONFIG_CRYPTO_DEV_NITROX=y
CONFIG_CRYPTO_DEV_NITROX_CNN55XX=y
# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SHA=y
CONFIG_CRYPTO_DEV_QCE_AEAD=y
CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
# CONFIG_CRYPTO_DEV_QCOM_RNG is not set
CONFIG_CRYPTO_DEV_IMGTEC_HASH=y
# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set
# CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_CRYPTO_DEV_SAFEXCEL=y
CONFIG_CRYPTO_DEV_CCREE=y
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
# CONFIG_CRYPTO_DEV_SA2UL is not set
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=y
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB=y
# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS is not set
# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC is not set
# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
CONFIG_SIGNED_PE_FILE_VERIFICATION=y
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
CONFIG_SECONDARY_TRUSTED_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
CONFIG_SYSTEM_REVOCATION_LIST=y
CONFIG_SYSTEM_REVOCATION_KEYS=""
# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=y
CONFIG_PRIME_NUMBERS=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_STMP_DEVICE=y

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_LIB_MEMNEQ=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
CONFIG_CRC32_SELFTEST=y
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
# CONFIG_CRC4 is not set
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
# CONFIG_XZ_DEC_ARM is not set
# CONFIG_XZ_DEC_ARMTHUMB is not set
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_TEST=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_BCH=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=y
CONFIG_TEXTSEARCH_BM=y
CONFIG_TEXTSEARCH_FSM=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_RESTRICTED_POOL=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_PERCENTAGE=10
# CONFIG_CMA_SIZE_SEL_MBYTES is not set
CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
CONFIG_DMA_API_DEBUG=y
CONFIG_DMA_API_DEBUG_SG=y
CONFIG_DMA_MAP_BENCHMARK=y
CONFIG_SGL_ALLOC=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_STACKDEPOT_ALWAYS_INIT=y
# CONFIG_PARMAN is not set
CONFIG_OBJAGG=y
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_POLYNOMIAL=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
# CONFIG_SYMBOLIC_ERRNAME is not set
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_MISC is not set

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=8192
CONFIG_STRIP_ASM_SYMS=y
CONFIG_HEADERS_INSTALL=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
# CONFIG_FRAME_POINTER is not set
# CONFIG_VMLINUX_MAP is not set
CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_FS_ALLOW_ALL is not set
CONFIG_DEBUG_FS_DISALLOW_MOUNT=y
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y
CONFIG_KGDB=y
# CONFIG_KGDB_TESTS is not set
CONFIG_KGDB_KDB=y
CONFIG_KDB_DEFAULT_ENABLE=0x1
CONFIG_KDB_CONTINUE_CATASTROPHIC=0
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
CONFIG_UBSAN=y
CONFIG_CC_HAS_UBSAN_BOUNDS=y
CONFIG_CC_HAS_UBSAN_ARRAY_BOUNDS=y
# CONFIG_UBSAN_BOUNDS is not set
CONFIG_UBSAN_SHIFT=y
CONFIG_UBSAN_UNREACHABLE=y
CONFIG_UBSAN_BOOL=y
# CONFIG_UBSAN_ENUM is not set
CONFIG_UBSAN_SANITIZE_ALL=y
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
CONFIG_DEBUG_NET=y
# end of Networking Debugging

#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
CONFIG_DEBUG_PAGEALLOC=y
# CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_PAGE_OWNER is not set
CONFIG_PAGE_TABLE_CHECK=y
CONFIG_PAGE_TABLE_CHECK_ENFORCED=y
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_OBJECTS_SELFTEST=y
# CONFIG_DEBUG_OBJECTS_FREE is not set
# CONFIG_DEBUG_OBJECTS_TIMERS is not set
CONFIG_DEBUG_OBJECTS_WORK=y
# CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set
# CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER is not set
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
# CONFIG_SHRINKER_DEBUG is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_STACK_USAGE=y
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
CONFIG_DEBUG_VIRTUAL=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
CONFIG_KASAN=y
CONFIG_KASAN_GENERIC=y
CONFIG_KASAN_OUTLINE=y
# CONFIG_KASAN_INLINE is not set
CONFIG_KASAN_VMALLOC=y
CONFIG_KASAN_KUNIT_TEST=y
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

CONFIG_DEBUG_SHIRQ=y

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_WQ_WATCHDOG is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set
# CONFIG_DEBUG_PREEMPT is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_PROVE_LOCKING=y
# CONFIG_PROVE_RAW_LOCK_NESTING is not set
CONFIG_LOCK_STAT=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
# CONFIG_DEBUG_LOCKDEP is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_LOCK_TORTURE_TEST=y
# CONFIG_WW_MUTEX_SELFTEST is not set
CONFIG_SCF_TORTURE_TEST=y
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

CONFIG_TRACE_IRQFLAGS=y
# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
CONFIG_WARN_ALL_UNSEEDED_RANDOM=y
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
CONFIG_DEBUG_SG=y
# CONFIG_DEBUG_NOTIFIERS is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
# CONFIG_PROVE_RCU_LIST is not set
CONFIG_TORTURE_TEST=y
CONFIG_RCU_SCALE_TEST=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_REF_SCALE_TEST=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
CONFIG_RCU_TRACE=y
CONFIG_RCU_EQS_DEBUG=y
# CONFIG_RCU_STRICT_GRACE_PERIOD is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set

#
# riscv Debugging
#
# end of riscv Debugging

#
# Kernel Testing and Coverage
#
CONFIG_KUNIT=y
CONFIG_KUNIT_DEBUGFS=y
CONFIG_KUNIT_TEST=y
CONFIG_KUNIT_EXAMPLE_TEST=y
CONFIG_KUNIT_ALL_TESTS=y
CONFIG_NOTIFIER_ERROR_INJECTION=y
# CONFIG_PM_NOTIFIER_ERROR_INJECT is not set
CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=y
# CONFIG_NETDEV_NOTIFIER_ERROR_INJECT is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage

# CONFIG_WARN_MISSING_DOCUMENTS is not set
CONFIG_WARN_ABI_ERRORS=y
# end of Kernel hacking

Re: [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver

[Linus Walleij]

On Fri, Sep 30, 2022 at 9:45 AM Hal Feng
<hal.feng@linux.starfivetech.com> wrote:

> From: Jianlong Huang <jianlong.huang@starfivetech.com>
>
> Add pinctrl driver for StarFive JH7110 SoC.
>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>

Since Emil submitted the first driver I would really appreciate his review
on this version.

Yours,
Linus Walleij

Re: [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver

[Emil Renner Berthing]

On Tue, 4 Oct 2022 at 10:57, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Fri, Sep 30, 2022 at 9:45 AM Hal Feng
> <hal.feng@linux.starfivetech.com> wrote:
>
> > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> >
> > Add pinctrl driver for StarFive JH7110 SoC.
> >
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
>
> Since Emil submitted the first driver I would really appreciate his review
> on this version.

I tried really hard to come up with a good way to share code between
the JH7100 and JH7110 drivers, but so many details different on the
JH7110 that it's probably best to just have a separate driver, so that
part is fine.

As mentioned elsewhere this driver certainly shouldn't be accepted
without following the generic pinctrl and pinmux bindings. You can see
the driver I wrote here:
https://github.com/esmil/linux/commit/c2633315385fef1a25aa3711facef07d915820e1

It is certainly not perfect and far from complete, but at least it
does follow the generic bindings. Feel free to copy all or parts of
that.

/Emil


>
> Yours,
> Linus Walleij
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver

[Hal Feng]

On Wed, 5 Oct 2022 15:31:59 +0200, Emil Renner Berthing wrote:
> On Tue, 4 Oct 2022 at 10:57, Linus Walleij <linus.walleij@linaro.org> wrote:
> >
> > On Fri, Sep 30, 2022 at 9:45 AM Hal Feng
> > <hal.feng@linux.starfivetech.com> wrote:
> >
> > > From: Jianlong Huang <jianlong.huang@starfivetech.com>
> > >
> > > Add pinctrl driver for StarFive JH7110 SoC.
> > >
> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> >
> > Since Emil submitted the first driver I would really appreciate his review
> > on this version.
> 
> I tried really hard to come up with a good way to share code between
> the JH7100 and JH7110 drivers, but so many details different on the
> JH7110 that it's probably best to just have a separate driver, so that
> part is fine.
> 
> As mentioned elsewhere this driver certainly shouldn't be accepted
> without following the generic pinctrl and pinmux bindings. You can see
> the driver I wrote here:
> https://github.com/esmil/linux/commit/c2633315385fef1a25aa3711facef07d915820e1
> 
> It is certainly not perfect and far from complete, but at least it
> does follow the generic bindings. Feel free to copy all or parts of
> that.

Thanks for your great contribution! We will rewrite the pinctrl driver
and bindings so make them follow the generic pinctrl framework.

Best regards,
Hal

[PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add initial device tree for the JH7110 RISC-V SoC by
StarFive Technology Ltd.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
 1 file changed, 449 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
new file mode 100644
index 000000000000..46f418d4198a
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive-jh7110-sys.h>
+#include <dt-bindings/clock/starfive-jh7110-aon.h>
+#include <dt-bindings/reset/starfive-jh7110.h>
+
+/ {
+	compatible = "starfive,jh7110";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <0>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <8192>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <16384>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imac";
+			tlb-split;
+			status = "disabled";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <1>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <2>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <3>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu4: cpu@4 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <4>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+
+				core4 {
+					cpu = <&cpu4>;
+				};
+			};
+		};
+	};
+
+	osc: osc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	clk_rtc: clk_rtc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	gmac0_rmii_refin: gmac0_rmii_refin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	gmac1_rmii_refin: gmac1_rmii_refin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	i2stx_bclk_ext: i2stx_bclk_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12288000>;
+	};
+
+	i2stx_lrck_ext: i2stx_lrck_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <192000>;
+	};
+
+	i2srx_bclk_ext: i2srx_bclk_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12288000>;
+	};
+
+	i2srx_lrck_ext: i2srx_lrck_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <192000>;
+	};
+
+	tdm_ext: tdm_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <49152000>;
+	};
+
+	mclk_ext: mclk_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <49152000>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clint: clint@2000000 {
+			compatible = "starfive,jh7110-clint", "sifive,clint0";
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>;
+		};
+
+		plic: plic@c000000 {
+			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			riscv,ndev = <136>;
+		};
+
+		ccache: cache-controller@2010000 {
+			compatible = "starfive,jh7110-ccache", "cache";
+			reg = <0x0 0x2010000 0x0 0x4000>;
+			interrupts = <1>, <3>, <4>, <2>;
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+		};
+
+		syscrg: syscrg@13020000 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x0 0x13020000 0x0 0x10000>;
+
+			syscrg_clk: clock-controller@13020000 {
+				compatible = "starfive,jh7110-clkgen-sys";
+				clocks = <&osc>, <&gmac1_rmii_refin>,
+					 <&gmac1_rgmii_rxin>,
+					 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+					 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+					 <&tdm_ext>, <&mclk_ext>;
+				clock-names = "osc", "gmac1_rmii_refin",
+					"gmac1_rgmii_rxin",
+					"i2stx_bclk_ext", "i2stx_lrck_ext",
+					"i2srx_bclk_ext", "i2srx_lrck_ext",
+					"tdm_ext", "mclk_ext";
+				#clock-cells = <1>;
+			};
+
+			syscrg_rst: reset-controller@13020000 {
+				compatible = "starfive,jh7110-reset";
+				#reset-cells = <1>;
+				starfive,assert-offset = <0x2F8>;
+				starfive,status-offset= <0x308>;
+				starfive,nr-resets = <JH7110_SYSRST_END>;
+			};
+		};
+
+		aoncrg: aoncrg@17000000 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x0 0x17000000 0x0 0x10000>;
+
+			aoncrg_clk: clock-controller@17000000 {
+				compatible = "starfive,jh7110-clkgen-aon";
+				clocks = <&osc>, <&clk_rtc>,
+					 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+					 <&syscrg_clk JH7110_SYSCLK_STG_AXIAHB>,
+					 <&syscrg_clk JH7110_SYSCLK_APB_BUS_FUNC>;
+				clock-names = "osc", "clk_rtc",
+					"gmac0_rmii_refin", "gmac0_rgmii_rxin",
+					"stg_axiahb", "apb_bus_func";
+				#clock-cells = <1>;
+			};
+
+			aoncrg_rst: reset-controller@17000000 {
+				compatible = "starfive,jh7110-reset";
+				#reset-cells = <1>;
+				starfive,assert-offset = <0x38>;
+				starfive,status-offset= <0x3C>;
+				starfive,nr-resets = <JH7110_AONRST_END>;
+			};
+		};
+
+		gpio: gpio@13040000 {
+			compatible = "starfive,jh7110-sys-pinctrl";
+			reg = <0x0 0x13040000 0x0 0x10000>;
+			reg-names = "control";
+			clocks = <&syscrg_clk JH7110_SYSCLK_IOMUX>;
+			resets = <&syscrg_rst JH7110_SYSRST_IOMUX>;
+			interrupts = <86>;
+			interrupt-controller;
+			#gpio-cells = <2>;
+			ngpios = <64>;
+		};
+
+		gpioa: gpio@17020000 {
+			compatible = "starfive,jh7110-aon-pinctrl";
+			reg = <0x0 0x17020000 0x0 0x10000>;
+			reg-names = "control";
+			resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>;
+			interrupts = <85>;
+			interrupt-controller;
+			#gpio-cells = <2>;
+			ngpios = <4>;
+		};
+
+		uart0: serial@10000000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10000000 0x0 0x10000>;
+			clocks = <&syscrg_clk JH7110_SYSCLK_UART0_CORE>,
+				 <&syscrg_clk JH7110_SYSCLK_UART0_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg_rst JH7110_SYSRST_UART0_APB>,
+				 <&syscrg_rst JH7110_SYSRST_UART0_CORE>;
+			interrupts = <32>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart1: serial@10010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10010000 0x0 0x10000>;
+			clocks = <&syscrg_clk JH7110_SYSCLK_UART1_CORE>,
+				 <&syscrg_clk JH7110_SYSCLK_UART1_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg_rst JH7110_SYSRST_UART1_APB>,
+				 <&syscrg_rst JH7110_SYSRST_UART1_CORE>;
+			interrupts = <33>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart2: serial@10020000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10020000 0x0 0x10000>;
+			clocks = <&syscrg_clk JH7110_SYSCLK_UART2_CORE>,
+				 <&syscrg_clk JH7110_SYSCLK_UART2_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg_rst JH7110_SYSRST_UART2_APB>,
+				 <&syscrg_rst JH7110_SYSRST_UART2_CORE>;
+			interrupts = <34>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart3: serial@12000000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12000000 0x0 0x10000>;
+			clocks = <&syscrg_clk JH7110_SYSCLK_UART3_CORE>,
+				 <&syscrg_clk JH7110_SYSCLK_UART3_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg_rst JH7110_SYSRST_UART3_APB>,
+				 <&syscrg_rst JH7110_SYSRST_UART3_CORE>;
+			interrupts = <45>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart4: serial@12010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12010000 0x0 0x10000>;
+			clocks = <&syscrg_clk JH7110_SYSCLK_UART4_CORE>,
+				 <&syscrg_clk JH7110_SYSCLK_UART4_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg_rst JH7110_SYSRST_UART4_APB>,
+				 <&syscrg_rst JH7110_SYSRST_UART4_CORE>;
+			interrupts = <46>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart5: serial@12020000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12020000 0x0 0x10000>;
+			clocks = <&syscrg_clk JH7110_SYSCLK_UART5_CORE>,
+				 <&syscrg_clk JH7110_SYSCLK_UART5_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg_rst JH7110_SYSRST_UART5_APB>,
+				 <&syscrg_rst JH7110_SYSRST_UART5_CORE>;
+			interrupts = <47>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.17.1

Re: [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree

[Conor Dooley]

On Fri, Sep 30, 2022 at 03:49:14PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add initial device tree for the JH7110 RISC-V SoC by
> StarFive Technology Ltd.
> 
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>

There's little point reviewing this dt since there's a load of issues
that you can trivially find by running dtbs_check/dt_binding_check, but
this SoB change is wrong - if Emil wrote the patch, then Jianlong's SoB
is either redundant or should be accompanied by a Co-developed-by tag.

Ditto for patch 28/30 "RISC-V: Add StarFive JH7110 VisionFive2 board
device tree".

> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
>  1 file changed, 449 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..46f418d4198a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi

> +
> +	osc: osc {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +	};
> +
> +	clk_rtc: clk_rtc {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +	};
> +
> +	gmac0_rmii_refin: gmac0_rmii_refin {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <50000000>;

I assume, given osc has it's frequency set in the board dts, that these
are all oscillators on the SoC?

> +	};
> +
> +	gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <125000000>;
> +	};
> +
> +	gmac1_rmii_refin: gmac1_rmii_refin {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <50000000>;
> +	};
> +
> +	gmac1_rgmii_rxin: gmac1_rgmii_rxin {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <125000000>;
> +	};
> +
> +	i2stx_bclk_ext: i2stx_bclk_ext {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <12288000>;
> +	};
> +
> +	i2stx_lrck_ext: i2stx_lrck_ext {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <192000>;
> +	};
> +
> +	i2srx_bclk_ext: i2srx_bclk_ext {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <12288000>;
> +	};
> +
> +	i2srx_lrck_ext: i2srx_lrck_ext {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <192000>;
> +	};
> +
> +	tdm_ext: tdm_ext {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <49152000>;
> +	};
> +
> +	mclk_ext: mclk_ext {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <49152000>;
> +	};

> +		syscrg: syscrg@13020000 {

The generic node name for syscons is just "syscon" afaik.

> +			compatible = "syscon", "simple-mfd";
> +			reg = <0x0 0x13020000 0x0 0x10000>;
> +

> +		aoncrg: aoncrg@17000000 {

Again, syscon as the node name?

> +			compatible = "syscon", "simple-mfd";
> +			reg = <0x0 0x17000000 0x0 0x10000>;
> +
> +		gpio: gpio@13040000 {

Someone else (Krzysztof maybe?) should comment, but is "pinctrl" not the
genric node name for pinctrl nodes?

Thanks,
Conor.

> +			compatible = "starfive,jh7110-sys-pinctrl";
> +			reg = <0x0 0x13040000 0x0 0x10000>;
> +			reg-names = "control";
> +			clocks = <&syscrg_clk JH7110_SYSCLK_IOMUX>;
> +			resets = <&syscrg_rst JH7110_SYSRST_IOMUX>;
> +			interrupts = <86>;
> +			interrupt-controller;
> +			#gpio-cells = <2>;
> +			ngpios = <64>;
> +		};
> +
> +		gpioa: gpio@17020000 {
> +			compatible = "starfive,jh7110-aon-pinctrl";
> +			reg = <0x0 0x17020000 0x0 0x10000>;
> +			reg-names = "control";
> +			resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>;
> +			interrupts = <85>;
> +			interrupt-controller;
> +			#gpio-cells = <2>;
> +			ngpios = <4>;
> +		};
> +
> +		uart0: serial@10000000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x10000000 0x0 0x10000>;
> +			clocks = <&syscrg_clk JH7110_SYSCLK_UART0_CORE>,
> +				 <&syscrg_clk JH7110_SYSCLK_UART0_APB>;
> +			clock-names = "baudclk", "apb_pclk";
> +			resets = <&syscrg_rst JH7110_SYSRST_UART0_APB>,
> +				 <&syscrg_rst JH7110_SYSRST_UART0_CORE>;
> +			interrupts = <32>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@10010000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x10010000 0x0 0x10000>;
> +			clocks = <&syscrg_clk JH7110_SYSCLK_UART1_CORE>,
> +				 <&syscrg_clk JH7110_SYSCLK_UART1_APB>;
> +			clock-names = "baudclk", "apb_pclk";
> +			resets = <&syscrg_rst JH7110_SYSRST_UART1_APB>,
> +				 <&syscrg_rst JH7110_SYSRST_UART1_CORE>;
> +			interrupts = <33>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@10020000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x10020000 0x0 0x10000>;
> +			clocks = <&syscrg_clk JH7110_SYSCLK_UART2_CORE>,
> +				 <&syscrg_clk JH7110_SYSCLK_UART2_APB>;
> +			clock-names = "baudclk", "apb_pclk";
> +			resets = <&syscrg_rst JH7110_SYSRST_UART2_APB>,
> +				 <&syscrg_rst JH7110_SYSRST_UART2_CORE>;
> +			interrupts = <34>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@12000000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x12000000 0x0 0x10000>;
> +			clocks = <&syscrg_clk JH7110_SYSCLK_UART3_CORE>,
> +				 <&syscrg_clk JH7110_SYSCLK_UART3_APB>;
> +			clock-names = "baudclk", "apb_pclk";
> +			resets = <&syscrg_rst JH7110_SYSRST_UART3_APB>,
> +				 <&syscrg_rst JH7110_SYSRST_UART3_CORE>;
> +			interrupts = <45>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@12010000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x12010000 0x0 0x10000>;
> +			clocks = <&syscrg_clk JH7110_SYSCLK_UART4_CORE>,
> +				 <&syscrg_clk JH7110_SYSCLK_UART4_APB>;
> +			clock-names = "baudclk", "apb_pclk";
> +			resets = <&syscrg_rst JH7110_SYSRST_UART4_APB>,
> +				 <&syscrg_rst JH7110_SYSRST_UART4_CORE>;
> +			interrupts = <46>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart5: serial@12020000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x12020000 0x0 0x10000>;
> +			clocks = <&syscrg_clk JH7110_SYSCLK_UART5_CORE>,
> +				 <&syscrg_clk JH7110_SYSCLK_UART5_APB>;
> +			clock-names = "baudclk", "apb_pclk";
> +			resets = <&syscrg_rst JH7110_SYSRST_UART5_APB>,
> +				 <&syscrg_rst JH7110_SYSRST_UART5_CORE>;
> +			interrupts = <47>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +	};
> +};
> -- 
> 2.17.1
> 

Re: [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree

[Krzysztof Kozlowski]

On 01/10/2022 12:52, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 03:49:14PM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by
>> StarFive Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> 
> There's little point reviewing this dt since there's a load of issues
> that you can trivially find by running dtbs_check/dt_binding_check, but

Yep...

> this SoB change is wrong - if Emil wrote the patch, then Jianlong's SoB
> is either redundant or should be accompanied by a Co-developed-by tag.

Depends. Jianlong might have just rebased the patch.

> 
> Ditto for patch 28/30 "RISC-V: Add StarFive JH7110 VisionFive2 board
> device tree".
> 
>> ---
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
>>  1 file changed, 449 insertions(+)
>>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..46f418d4198a
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> 
>> +
>> +	osc: osc {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +	};
>> +
>> +	clk_rtc: clk_rtc {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +	};
>> +
>> +	gmac0_rmii_refin: gmac0_rmii_refin {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <50000000>;
> 
> I assume, given osc has it's frequency set in the board dts, that these
> are all oscillators on the SoC?
> 
>> +	};
>> +
>> +	gmac0_rgmii_rxin: gmac0_rgmii_rxin {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <125000000>;
>> +	};
>> +
>> +	gmac1_rmii_refin: gmac1_rmii_refin {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <50000000>;
>> +	};
>> +
>> +	gmac1_rgmii_rxin: gmac1_rgmii_rxin {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <125000000>;
>> +	};
>> +
>> +	i2stx_bclk_ext: i2stx_bclk_ext {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <12288000>;
>> +	};
>> +
>> +	i2stx_lrck_ext: i2stx_lrck_ext {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <192000>;
>> +	};
>> +
>> +	i2srx_bclk_ext: i2srx_bclk_ext {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <12288000>;
>> +	};
>> +
>> +	i2srx_lrck_ext: i2srx_lrck_ext {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <192000>;
>> +	};
>> +
>> +	tdm_ext: tdm_ext {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <49152000>;
>> +	};
>> +
>> +	mclk_ext: mclk_ext {
>> +		compatible = "fixed-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <49152000>;
>> +	};
> 
>> +		syscrg: syscrg@13020000 {
> 
> The generic node name for syscons is just "syscon" afaik.

Yes.

> 
>> +			compatible = "syscon", "simple-mfd";

And this is not allowed. Needs specific compatible.


>> +			reg = <0x0 0x13020000 0x0 0x10000>;
>> +
> 
>> +		aoncrg: aoncrg@17000000 {
> 
> Again, syscon as the node name?

Yes.

> 
>> +			compatible = "syscon", "simple-mfd";

And this is a NAK.

>> +			reg = <0x0 0x17000000 0x0 0x10000>;
>> +
>> +		gpio: gpio@13040000 {
> 
> Someone else (Krzysztof maybe?) should comment, but is "pinctrl" not the
> genric node name for pinctrl nodes?

Yes, for pin controller nodes, this should be "pinctrl" and schema
requires it. The problem was that his driver did not use generic pinctrl
bindings, which is no-go on its own.

This could be a gpio controller (so "gpio" would be fine), although
compatible suggests otherwise.


Best regards,
Krzysztof

Re: [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree

[Hal Feng]

On Sat, 1 Oct 2022 11:52:00 +0100, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 03:49:14PM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> > 
> > Add initial device tree for the JH7110 RISC-V SoC by
> > StarFive Technology Ltd.
> > 
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> 
> There's little point reviewing this dt since there's a load of issues
> that you can trivially find by running dtbs_check/dt_binding_check, but
> this SoB change is wrong - if Emil wrote the patch, then Jianlong's SoB
> is either redundant or should be accompanied by a Co-developed-by tag.
> 
> Ditto for patch 28/30 "RISC-V: Add StarFive JH7110 VisionFive2 board
> device tree".

Will add Co-developed-by tag for Jianlong. Thanks.

> 
> > ---
> >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
> >  1 file changed, 449 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..46f418d4198a
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> 
> > +
> > +	osc: osc {
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	clk_rtc: clk_rtc {
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	gmac0_rmii_refin: gmac0_rmii_refin {
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +		clock-frequency = <50000000>;
> 
> I assume, given osc has it's frequency set in the board dts, that these
> are all oscillators on the SoC?

These are all on the board. Should move all "clock-frequency" to the board dts.
I will recheck and modify this patch.

Best regards,
Hal

[PATCH v1 28/30] RISC-V: Add StarFive JH7110 VisionFive2 board device tree

[Hal Feng]

From: Emil Renner Berthing <kernel@esmil.dk>

Add a minimal device tree for StarFive JH7110 VisionFive2 board.
Support booting and basic clock/reset/pinctrl/uart drivers.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 arch/riscv/boot/dts/starfive/Makefile         |  1 +
 .../jh7110-starfive-visionfive-v2.dts         | 91 +++++++++++++++++++
 2 files changed, 92 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 0ea1bc15ab30..e1237dbc6aac 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
new file mode 100644
index 000000000000..6b9fe32c7eac
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+
+/ {
+	model = "StarFive VisionFive V2";
+	compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	cpus {
+		timebase-frequency = <4000000>;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x1 0x0>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x20000000>;
+			alignment = <0x0 0x1000>;
+			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
+			linux,cma-default;
+		};
+
+		e24_mem: e24@c0000000 {
+			reg = <0x0 0xc0110000 0x0 0xf0000>;
+			no-map;
+		};
+
+		xrp_reserved: xrpbuffer@f0000000 {
+			reg = <0x0 0xf0000000 0x0 0x01ffffff>,
+			      <0x0 0xf2000000 0x0 0x00001000>,
+			      <0x0 0xf2001000 0x0 0x00fff000>,
+			      <0x0 0xf3000000 0x0 0x00001000>;
+		};
+
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+		priority = <224>;
+	};
+};
+
+&gpio {
+	uart0_pins: uart0-pins {
+		uart0-pins-tx {
+			starfive,pins = <PAD_GPIO5>;
+			starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+			starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+			starfive,pin-gpio-doen = <OEN_LOW>;
+		};
+
+		uart0-pins-rx {
+			starfive,pins = <PAD_GPIO6>;
+			starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
+			starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+			starfive,pin-gpio-doen = <OEN_HIGH>;
+			starfive,pin-gpio-din =  <GPI_UART0_SIN>;
+		};
+	};
+};
+
+&osc {
+	clock-frequency = <24000000>;
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
-- 
2.17.1

Re: [PATCH v1 28/30] RISC-V: Add StarFive JH7110 VisionFive2 board device tree

[Conor Dooley]

On Fri, Sep 30, 2022 at 03:53:53PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
> 
> Add a minimal device tree for StarFive JH7110 VisionFive2 board.
> Support booting and basic clock/reset/pinctrl/uart drivers.
>

I would like to see a link to the publicly available datasheet or
documentation for the board (and for the SoC in patch 28) please.

> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>

Ditto from patch 28 re: the SoB chain.

> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---

> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> new file mode 100644
> index 000000000000..6b9fe32c7eac
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> +/ {
> +	model = "StarFive VisionFive V2";
> +	compatible = "starfive,visionfive-v2", "starfive,jh7110";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};

Should we also have a chosen node here?

> +
> +	cpus {
> +		timebase-frequency = <4000000>;
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0x1 0x0>;

What is going to happen to the 2 GB variant if they attempt to use this
devicetree?

> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			reusable;
> +			size = <0x0 0x20000000>;
> +			alignment = <0x0 0x1000>;
> +			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
> +			linux,cma-default;
> +		};
> +
> +		e24_mem: e24@c0000000 {

I had a conversation previously with Icenowy [0] about the e24 on the
jh7100 that didn't really come to a conclusion about how to represent
it there - but looks like you've decided that it should be a remoteproc
for the jh7100?

Is this another situation where peripherals appear at different
addresses for the e24 compared to the u74s? Or has that changed for the
jh7100, and really the e24 should be described in the CPUs node? If it
is the latter, you can pick the first patch from [0] into your series.

0 - https://lore.kernel.org/linux-riscv/e8543838cd221ab6699da16c985eed7514daa786.camel@icenowy.me/

> +			reg = <0x0 0xc0110000 0x0 0xf0000>;
> +			no-map;
> +		};
> +
> +		xrp_reserved: xrpbuffer@f0000000 {

"Following the generic-names recommended practice, node names should
reflect the purpose of the node (ie. “framebuffer” or “dma-pool”)."

I tried googling around for an explanation for what the xrp was, and all
I could find was this out-of-tree text binding:
https://github.com/foss-xtensa/xrp/blob/master/xrp-kernel/cdns%2Cxrp-hw-simple%2Cv1.txt

Thanks,
Conor.

> +			reg = <0x0 0xf0000000 0x0 0x01ffffff>,
> +			      <0x0 0xf2000000 0x0 0x00001000>,
> +			      <0x0 0xf2001000 0x0 0x00fff000>,
> +			      <0x0 0xf3000000 0x0 0x00001000>;
> +		};
> +
> +	};
> +
> +	gpio-restart {
> +		compatible = "gpio-restart";
> +		gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
> +		priority = <224>;
> +	};
> +};
> +
> +&gpio {
> +	uart0_pins: uart0-pins {
> +		uart0-pins-tx {
> +			starfive,pins = <PAD_GPIO5>;
> +			starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
> +			starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
> +			starfive,pin-gpio-doen = <OEN_LOW>;
> +		};
> +
> +		uart0-pins-rx {
> +			starfive,pins = <PAD_GPIO6>;
> +			starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
> +			starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
> +			starfive,pin-gpio-doen = <OEN_HIGH>;
> +			starfive,pin-gpio-din =  <GPI_UART0_SIN>;
> +		};
> +	};
> +};
> +
> +&osc {
> +	clock-frequency = <24000000>;
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pins>;
> +	status = "okay";
> +};
> -- 
> 2.17.1
> 

Re: [PATCH v1 28/30] RISC-V: Add StarFive JH7110 VisionFive2 board device tree

[Hal Feng]

On Sat, 1 Oct 2022 12:14:49 +0100, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 03:53:53PM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> > 
> > Add a minimal device tree for StarFive JH7110 VisionFive2 board.
> > Support booting and basic clock/reset/pinctrl/uart drivers.
> >
> 
> I would like to see a link to the publicly available datasheet or
> documentation for the board (and for the SoC in patch 28) please.

All documents can be found at RVspace Documentation Center maintained
by StarFive. The related documents of JH7110 SoC and VisionFive2 board
are as follows.

StarFive JH7110 SoC:
https://doc-en.rvspace.org/Doc_Center/jh7110.html
StarFive VisionFive2 board:
https://doc-en.rvspace.org/Doc_Center/visionfive_2.html

> 
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> 
> Ditto from patch 28 re: the SoB chain.
> 
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> 
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > new file mode 100644
> > index 000000000000..6b9fe32c7eac
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > @@ -0,0 +1,91 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> > + */
> > +
> > +/dts-v1/;
> > +#include "jh7110.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> > +
> > +/ {
> > +	model = "StarFive VisionFive V2";
> > +	compatible = "starfive,visionfive-v2", "starfive,jh7110";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +	};
> 
> Should we also have a chosen node here?

Will add it. Thanks.

> 
> > +
> > +	cpus {
> > +		timebase-frequency = <4000000>;
> > +	};
> > +
> > +	memory@40000000 {
> > +		device_type = "memory";
> > +		reg = <0x0 0x40000000 0x1 0x0>;
> 
> What is going to happen to the 2 GB variant if they attempt to use this
> devicetree?

The VisionFive2 board now has 4GB version and 8GB version only. Before
linux startup, we will change this property in dtb through u-boot to
make sure the board can boot up with the correct memory size.

> 
> > +	};
> > +
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		linux,cma {
> > +			compatible = "shared-dma-pool";
> > +			reusable;
> > +			size = <0x0 0x20000000>;
> > +			alignment = <0x0 0x1000>;
> > +			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
> > +			linux,cma-default;
> > +		};
> > +
> > +		e24_mem: e24@c0000000 {
> 
> I had a conversation previously with Icenowy [0] about the e24 on the
> jh7100 that didn't really come to a conclusion about how to represent
> it there - but looks like you've decided that it should be a remoteproc
> for the jh7100?

Yes, we treat it as a remoteproc outside the cpus node. But after
communication with my colleagues, I found that all nodes in
"reserved-memory" are not used in the minimal support for VisionFive2
board. So for this series, I would like to remove "reserved-memory"
in v2.

> 
> Is this another situation where peripherals appear at different
> addresses for the e24 compared to the u74s? Or has that changed for the> jh7100, and really the e24 should be described in the CPUs node? If it
> is the latter, you can pick the first patch from [0] into your series.
> 
> 0 - https://lore.kernel.org/linux-riscv/e8543838cd221ab6699da16c985eed7514daa786.camel@icenowy.me> > +			reg = <0x0 0xc0110000 0x0 0xf0000>;
> > +			no-map;
> > +		};
> > +
> > +		xrp_reserved: xrpbuffer@f0000000 {
> 
> "Following the generic-names recommended practice, node names should
> reflect the purpose of the node (ie. “framebuffer” or “dma-pool”)."
> 
> I tried googling around for an explanation for what the xrp was, and all
> I could find was this out-of-tree text binding:
> https://github.com/foss-xtensa/xrp/blob/master/xrp-kernel/cdns%2Cxrp-hw-simple%2Cv1.txt

The name is from the device driver of HiFi4 DSP provided by Cadence,
which is not in the mainline. "xrp" is a short name of
"Xtensa Remote Processing".

Best regards,
Hal

[PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW

[Hal Feng]

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index aed332a9d4ea..0c44484cd3a4 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y
-- 
2.17.1

Re: [PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW

[Ben Dooks]

On 30/09/2022 10:06, Hal Feng wrote:
> Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> 
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>

That might be useful for other users at some point an I don't
think it adds much code.

> ---
>   arch/riscv/configs/defconfig | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index aed332a9d4ea..0c44484cd3a4 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
>   CONFIG_INPUT_MOUSEDEV=y
>   CONFIG_SERIAL_8250=y
>   CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_DW=y
>   CONFIG_SERIAL_OF_PLATFORM=y
>   CONFIG_VIRTIO_CONSOLE=y
>   CONFIG_HW_RANDOM=y

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW

[Conor Dooley]

On Fri, Sep 30, 2022 at 09:54:14PM +0100, Ben Dooks wrote:
> On 30/09/2022 10:06, Hal Feng wrote:
> > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> > 
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> 
> That might be useful for other users at some point an I don't
> think it adds much code.

Honestly I think this should be applied for 6.1, for parity with the
other SoCs that have their serial console enabled by default.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> 
> > ---
> >   arch/riscv/configs/defconfig | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index aed332a9d4ea..0c44484cd3a4 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
> >   CONFIG_INPUT_MOUSEDEV=y
> >   CONFIG_SERIAL_8250=y
> >   CONFIG_SERIAL_8250_CONSOLE=y
> > +CONFIG_SERIAL_8250_DW=y
> >   CONFIG_SERIAL_OF_PLATFORM=y
> >   CONFIG_VIRTIO_CONSOLE=y
> >   CONFIG_HW_RANDOM=y
> 
> -- 
> Ben Dooks				http://www.codethink.co.uk/
> Senior Engineer				Codethink - Providing Genius
> 
> https://www.codethink.co.uk/privacy.html
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW

[Hal Feng]

On Fri, 30 Sep 2022 22:41:23 +0100, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 09:54:14PM +0100, Ben Dooks wrote:
> > On 30/09/2022 10:06, Hal Feng wrote:
> > > Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for
> > > StarFive JH7110 and JH7100 SoCs to boot with serial ports.
> > > 
> > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > 
> > That might be useful for other users at some point an I don't
> > think it adds much code.
> 
> Honestly I think this should be applied for 6.1, for parity with the
> other SoCs that have their serial console enabled by default.
> 
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Could this patch be pulled out and applied for v6.1? So the JH7100
and the coming JH7110 can enable serial console by default when
booting. Thanks.

Best regards,
Hal

[PATCH v1 30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options

[Hal Feng]

Add Kconfig options to select the specified StarFive SoC. Select
necessary Kconfig options required by the specified SoC for booting.

Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
 arch/riscv/Kconfig.socs               | 27 ++++++++++++++++++++++++++-
 arch/riscv/boot/dts/starfive/Makefile |  4 ++--
 drivers/clk/starfive/Kconfig          | 14 ++++++--------
 drivers/pinctrl/starfive/Kconfig      |  6 ++----
 drivers/reset/Kconfig                 |  1 -
 5 files changed, 36 insertions(+), 16 deletions(-)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 10f68a4359f9..321c448e7b6f 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,10 +22,35 @@ config SOC_STARFIVE
 	bool "StarFive SoCs"
 	select PINCTRL
 	select RESET_CONTROLLER
+	select RESET_STARFIVE
+	help
+	  This enables support for StarFive SoC platform hardware.
+
+if SOC_STARFIVE
+
+config SOC_JH7100
+	bool "StarFive JH7100 SoC support"
+	depends on SOC_STARFIVE
 	select SIFIVE_L2
 	select SIFIVE_PLIC
+	select CLK_STARFIVE_JH7100
+	select PINCTRL_STARFIVE_JH7100
+	default SOC_STARFIVE
 	help
-	  This enables support for StarFive SoC platform hardware.
+	  This enables support for StarFive JH7100 SoC.
+
+config SOC_JH7110
+	bool "StarFive JH7110 SoC support"
+	depends on SOC_STARFIVE
+	select SIFIVE_L2
+	select SIFIVE_PLIC
+	select CLK_STARFIVE_JH7110_SYS
+	select PINCTRL_STARFIVE_JH7110
+	default SOC_STARFIVE
+	help
+	  This enables support for StarFive JH7110 SoC.
+
+endif
 
 config SOC_VIRT
 	bool "QEMU Virt Machine"
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index e1237dbc6aac..a6ecd3c2ec7d 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
-dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
+dtb-$(CONFIG_SOC_JH7100) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_JH7110) += jh7110-starfive-visionfive-v2.dtb
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 42aad3b553cb..d0490e9f42db 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -5,36 +5,34 @@ config CLK_STARFIVE
 
 config CLK_STARFIVE_JH7100
 	bool "StarFive JH7100 clock support"
-	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on SOC_JH7100 || COMPILE_TEST
 	select CLK_STARFIVE
-	default SOC_STARFIVE
 	help
 	  Say yes here to support the clock controller on the StarFive JH7100
 	  SoC.
 
 config CLK_STARFIVE_JH7100_AUDIO
 	tristate "StarFive JH7100 audio clock support"
-	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on SOC_JH7100 || COMPILE_TEST
 	select CLK_STARFIVE
-	default m if SOC_STARFIVE
+	default m if SOC_JH7100
 	help
 	  Say Y or M here to support the audio clocks on the StarFive JH7100
 	  SoC.
 
 config CLK_STARFIVE_JH7110_SYS
 	bool "StarFive JH7110 system clock support"
-	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on SOC_JH7110 || COMPILE_TEST
 	select CLK_STARFIVE
-	default SOC_STARFIVE
 	help
 	  Say yes here to support the system clock controller on the
 	  StarFive JH7110 SoC.
 
 config CLK_STARFIVE_JH7110_AON
 	tristate "StarFive JH7110 always-on clock support"
-	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on SOC_JH7110 || COMPILE_TEST
 	select CLK_STARFIVE
-	default m if SOC_STARFIVE
+	default m if SOC_JH7110
 	help
 	  Say yes here to support the always-on clock controller on the
 	  StarFive JH7110 SoC.
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index fde39f4a7922..d09bdf6d3029 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -2,7 +2,7 @@
 
 config PINCTRL_STARFIVE_JH7100
 	tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
-	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on SOC_JH7100 || COMPILE_TEST
 	depends on OF
 	select GENERIC_PINCTRL_GROUPS
 	select GENERIC_PINMUX_FUNCTIONS
@@ -10,7 +10,6 @@ config PINCTRL_STARFIVE_JH7100
 	select GPIOLIB
 	select GPIOLIB_IRQCHIP
 	select OF_GPIO
-	default SOC_STARFIVE
 	help
 	  Say yes here to support pin control on the StarFive JH7100 SoC.
 	  This also provides an interface to the GPIO pins not used by other
@@ -28,10 +27,9 @@ config PINCTRL_STARFIVE
 
 config PINCTRL_STARFIVE_JH7110
 	bool "Pinctrl and GPIO driver for the StarFive JH7110 SoC"
-	depends on SOC_STARFIVE || COMPILE_TEST
+	depends on SOC_JH7110 || COMPILE_TEST
 	depends on OF
 	select PINCTRL_STARFIVE
-	default SOC_STARFIVE
 	help
 	  Say yes here to support pin control on the StarFive JH7110 SoC.
 	  This also provides an interface to the GPIO pins not used by other
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 8121de5ecc3c..c001879bd890 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -228,7 +228,6 @@ config RESET_SOCFPGA
 config RESET_STARFIVE
 	bool "StarFive SoC Reset Driver"
 	depends on SOC_STARFIVE || COMPILE_TEST
-	default SOC_STARFIVE
 	help
 	  This enables the reset controller driver for the StarFive SoCs.
 
-- 
2.17.1

Re: [PATCH v1 30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options

[Conor Dooley]

On Fri, Sep 30, 2022 at 08:23:18PM +0800, Hal Feng wrote:
> Add Kconfig options to select the specified StarFive SoC. Select
> necessary Kconfig options required by the specified SoC for booting.
> 
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  arch/riscv/Kconfig.socs               | 27 ++++++++++++++++++++++++++-
>  arch/riscv/boot/dts/starfive/Makefile |  4 ++--
>  drivers/clk/starfive/Kconfig          | 14 ++++++--------
>  drivers/pinctrl/starfive/Kconfig      |  6 ++----
>  drivers/reset/Kconfig                 |  1 -

Firstly, you cannot change all of these files in one commit, sorry.

>  5 files changed, 36 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 10f68a4359f9..321c448e7b6f 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,10 +22,35 @@ config SOC_STARFIVE
>  	bool "StarFive SoCs"
>  	select PINCTRL
>  	select RESET_CONTROLLER
> +	select RESET_STARFIVE

Secondly, we are trying to get rid of selects in arch/riscv at the
moment, not add them. use "default SOC_STARFIVE" in
drivers/reset/kconfig instead please.

> +	help
> +	  This enables support for StarFive SoC platform hardware.
> +
> +if SOC_STARFIVE

I don't think we want to have per soc selection menus in arch code,
I think this should move to drivers/soc (a la Renesas) if you want to
have a per soc selection menu or else just do "default SOC_STARFIVE"
for both clock and pinctrl drivers in the clk and pinctrl Kconfig
entries.

Thanks,
Conor.

> +
> +config SOC_JH7100
> +	bool "StarFive JH7100 SoC support"
> +	depends on SOC_STARFIVE
>  	select SIFIVE_L2
>  	select SIFIVE_PLIC
> +	select CLK_STARFIVE_JH7100
> +	select PINCTRL_STARFIVE_JH7100
> +	default SOC_STARFIVE
>  	help
> -	  This enables support for StarFive SoC platform hardware.
> +	  This enables support for StarFive JH7100 SoC.
> +
> +config SOC_JH7110
> +	bool "StarFive JH7110 SoC support"
> +	depends on SOC_STARFIVE
> +	select SIFIVE_L2
> +	select SIFIVE_PLIC
> +	select CLK_STARFIVE_JH7110_SYS
> +	select PINCTRL_STARFIVE_JH7110
> +	default SOC_STARFIVE
> +	help
> +	  This enables support for StarFive JH7110 SoC.
> +
> +endif
>  
>  config SOC_VIRT
>  	bool "QEMU Virt Machine"
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index e1237dbc6aac..a6ecd3c2ec7d 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,3 +1,3 @@
>  # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb
> +dtb-$(CONFIG_SOC_JH7100) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_JH7110) += jh7110-starfive-visionfive-v2.dtb
> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> index 42aad3b553cb..d0490e9f42db 100644
> --- a/drivers/clk/starfive/Kconfig
> +++ b/drivers/clk/starfive/Kconfig
> @@ -5,36 +5,34 @@ config CLK_STARFIVE
>  
>  config CLK_STARFIVE_JH7100
>  	bool "StarFive JH7100 clock support"
> -	depends on SOC_STARFIVE || COMPILE_TEST
> +	depends on SOC_JH7100 || COMPILE_TEST
>  	select CLK_STARFIVE
> -	default SOC_STARFIVE
>  	help
>  	  Say yes here to support the clock controller on the StarFive JH7100
>  	  SoC.
>  
>  config CLK_STARFIVE_JH7100_AUDIO
>  	tristate "StarFive JH7100 audio clock support"
> -	depends on SOC_STARFIVE || COMPILE_TEST
> +	depends on SOC_JH7100 || COMPILE_TEST
>  	select CLK_STARFIVE
> -	default m if SOC_STARFIVE
> +	default m if SOC_JH7100
>  	help
>  	  Say Y or M here to support the audio clocks on the StarFive JH7100
>  	  SoC.
>  
>  config CLK_STARFIVE_JH7110_SYS
>  	bool "StarFive JH7110 system clock support"
> -	depends on SOC_STARFIVE || COMPILE_TEST
> +	depends on SOC_JH7110 || COMPILE_TEST
>  	select CLK_STARFIVE
> -	default SOC_STARFIVE
>  	help
>  	  Say yes here to support the system clock controller on the
>  	  StarFive JH7110 SoC.
>  
>  config CLK_STARFIVE_JH7110_AON
>  	tristate "StarFive JH7110 always-on clock support"
> -	depends on SOC_STARFIVE || COMPILE_TEST
> +	depends on SOC_JH7110 || COMPILE_TEST
>  	select CLK_STARFIVE
> -	default m if SOC_STARFIVE
> +	default m if SOC_JH7110
>  	help
>  	  Say yes here to support the always-on clock controller on the
>  	  StarFive JH7110 SoC.
> diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
> index fde39f4a7922..d09bdf6d3029 100644
> --- a/drivers/pinctrl/starfive/Kconfig
> +++ b/drivers/pinctrl/starfive/Kconfig
> @@ -2,7 +2,7 @@
>  
>  config PINCTRL_STARFIVE_JH7100
>  	tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
> -	depends on SOC_STARFIVE || COMPILE_TEST
> +	depends on SOC_JH7100 || COMPILE_TEST
>  	depends on OF
>  	select GENERIC_PINCTRL_GROUPS
>  	select GENERIC_PINMUX_FUNCTIONS
> @@ -10,7 +10,6 @@ config PINCTRL_STARFIVE_JH7100
>  	select GPIOLIB
>  	select GPIOLIB_IRQCHIP
>  	select OF_GPIO
> -	default SOC_STARFIVE
>  	help
>  	  Say yes here to support pin control on the StarFive JH7100 SoC.
>  	  This also provides an interface to the GPIO pins not used by other
> @@ -28,10 +27,9 @@ config PINCTRL_STARFIVE
>  
>  config PINCTRL_STARFIVE_JH7110
>  	bool "Pinctrl and GPIO driver for the StarFive JH7110 SoC"
> -	depends on SOC_STARFIVE || COMPILE_TEST
> +	depends on SOC_JH7110 || COMPILE_TEST
>  	depends on OF
>  	select PINCTRL_STARFIVE
> -	default SOC_STARFIVE
>  	help
>  	  Say yes here to support pin control on the StarFive JH7110 SoC.
>  	  This also provides an interface to the GPIO pins not used by other
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 8121de5ecc3c..c001879bd890 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -228,7 +228,6 @@ config RESET_SOCFPGA
>  config RESET_STARFIVE
>  	bool "StarFive SoC Reset Driver"
>  	depends on SOC_STARFIVE || COMPILE_TEST
> -	default SOC_STARFIVE
>  	help
>  	  This enables the reset controller driver for the StarFive SoCs.
>  
> -- 
> 2.17.1
> 

Re: [PATCH v1 30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options

[Hal Feng]

On Fri, 30 Sep 2022 13:37:28 +0100, Conor Dooley wrote:
> On Fri, Sep 30, 2022 at 08:23:18PM +0800, Hal Feng wrote:
> > Add Kconfig options to select the specified StarFive SoC. Select
> > necessary Kconfig options required by the specified SoC for booting.
> > 
> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> > ---
> >  arch/riscv/Kconfig.socs               | 27 ++++++++++++++++++++++++++-
> >  arch/riscv/boot/dts/starfive/Makefile |  4 ++--
> >  drivers/clk/starfive/Kconfig          | 14 ++++++--------
> >  drivers/pinctrl/starfive/Kconfig      |  6 ++----
> >  drivers/reset/Kconfig                 |  1 -
> 
> Firstly, you cannot change all of these files in one commit, sorry.
> 
> >  5 files changed, 36 insertions(+), 16 deletions(-)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 10f68a4359f9..321c448e7b6f 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -22,10 +22,35 @@ config SOC_STARFIVE
> >  	bool "StarFive SoCs"
> >  	select PINCTRL
> >  	select RESET_CONTROLLER
> > +	select RESET_STARFIVE
> 
> Secondly, we are trying to get rid of selects in arch/riscv at the
> moment, not add them. use "default SOC_STARFIVE" in
> drivers/reset/kconfig instead please.
> 
> > +	help
> > +	  This enables support for StarFive SoC platform hardware.
> > +
> > +if SOC_STARFIVE
> 
> I don't think we want to have per soc selection menus in arch code,
> I think this should move to drivers/soc (a la Renesas) if you want to
> have a per soc selection menu or else just do "default SOC_STARFIVE"
> for both clock and pinctrl drivers in the clk and pinctrl Kconfig
> entries.

Thanks for your helpful comments. I will drop this patch.

Best regards,
Hal

Re: [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support

[Emil Renner Berthing]

On Thu, 29 Sept 2022 at 16:34, Hal Feng <hal.feng@linux.starfivetech.com> wrote:
> This series adds basic support for the StarFive JH7110 RISC-V SoC to
> boot up and get a serial console. This series includes basic clock,
> reset, pinctrl and uart drivers, which are necessary for booting.
> It's should be noted that the reset and clock driver codes of JH7110
> are partly common with those of JH7100, so the common codes are
> factored out and can be reused by drivers of JH7110 and other more
> SoCs from StarFive.
>
> The JH7110 is the upgraded version of JH7100 and also the first official
> released version of JH71XX series SoCs from StarFive Technology Ltd.
> The VisionFive 2 boards equipped with JH7110 SoCs are launched
> recently [1]. More information and support can visit RVspace wiki [2].
>
> This series is also available at
> https://github.com/hal-feng/linux/commits/visionfive2-minimal
>
> [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> [2] https://wiki.rvspace.org/

Hi Hal,

Firstly thanks for working on this! And sorry about the late reply. On
the next version could you please cc
emil.renner.berthing@canonical.com since it seems to handle the
mailing list a bit better.

I see you've changed the clock/reset and pinctrl quite a bit, so I'll
comment on that separately.

/Emil

> Emil Renner Berthing (17):
>   dt-bindings: riscv: Add StarFive JH7110 bindings
>   dt-bindings: timer: Add StarFive JH7110 clint
>   dt-bindings: interrupt-controller: Add StarFive JH7110 plic
>   dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
>   soc: sifive: l2 cache: Convert to platform driver
>   soc: sifive: l2 cache: Add StarFive JH71x0 support
>   reset: starfive: jh7100: Use 32bit I/O on 32bit registers
>   dt-bindings: reset: Add StarFive JH7110 reset definitions
>   clk: starfive: Factor out common clock driver code
>   dt-bindings: clock: Add StarFive JH7110 system clock definitions
>   dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
>   clk: starfive: Add StarFive JH7110 system clock driver
>   dt-bindings: clock: Add StarFive JH7110 always-on definitions
>   dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
>   clk: starfive: Add StarFive JH7110 always-on clock driver
>   RISC-V: Add initial StarFive JH7110 device tree
>   RISC-V: Add StarFive JH7110 VisionFive2 board device tree
>
> Hal Feng (8):
>   reset: starfive: jh7100: Use regmap APIs to operate registers
>   reset: starfive: jh7100: Move necessary properties to device tree
>   reset: starfive: Rename 'reset-starfive-jh7100.c' to
>     'reset-starfive.c'
>   dt-bindings: reset: Add starfive,jh7110-reset bindings
>   reset: starfive: Add StarFive JH7110 SoC support
>   clk: starfive: Use regmap APIs to operate registers
>   RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW
>   RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options
>
> Jianlong Huang (5):
>   pinctrl: Create subdirectory for StarFive drivers
>   pinctrl: starfive: Rename "pinctrl-starfive" to
>     "pinctrl-starfive-jh7100"
>   dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
>   dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings
>   pinctrl: starfive: Add StarFive JH7110 driver
>
>  .../clock/starfive,jh7110-clkgen-aon.yaml     |  62 ++
>  .../clock/starfive,jh7110-clkgen-sys.yaml     |  69 ++
>  .../sifive,plic-1.0.0.yaml                    |   1 +
>  .../pinctrl/starfive,jh7100-pinctrl.yaml      |   2 +-
>  .../pinctrl/starfive,jh7110-pinctrl.yaml      | 202 ++++
>  .../bindings/reset/starfive,jh7100-reset.yaml |  20 +
>  .../bindings/reset/starfive,jh7110-reset.yaml |  54 +
>  .../bindings/riscv/sifive-l2-cache.yaml       |   4 +
>  .../devicetree/bindings/riscv/starfive.yaml   |   3 +
>  .../bindings/timer/sifive,clint.yaml          |   1 +
>  MAINTAINERS                                   |  27 +-
>  arch/riscv/Kconfig.socs                       |  28 +-
>  arch/riscv/boot/dts/starfive/Makefile         |   3 +-
>  .../dts/starfive/jh7100-beaglev-starlight.dts |   2 +-
>  arch/riscv/boot/dts/starfive/jh7100.dtsi      |   3 +
>  .../jh7110-starfive-visionfive-v2.dts         |  91 ++
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 449 +++++++++
>  arch/riscv/configs/defconfig                  |   1 +
>  drivers/clk/starfive/Kconfig                  |  29 +-
>  drivers/clk/starfive/Makefile                 |   6 +-
>  .../clk/starfive/clk-starfive-jh7100-audio.c  | 138 +--
>  drivers/clk/starfive/clk-starfive-jh7100.c    | 836 +++++-----------
>  drivers/clk/starfive/clk-starfive-jh7100.h    | 112 ---
>  .../clk/starfive/clk-starfive-jh7110-aon.c    | 161 +++
>  .../clk/starfive/clk-starfive-jh7110-sys.c    | 648 ++++++++++++
>  drivers/clk/starfive/clk-starfive.c           | 349 +++++++
>  drivers/clk/starfive/clk-starfive.h           | 112 +++
>  drivers/pinctrl/Kconfig                       |  18 +-
>  drivers/pinctrl/Makefile                      |   2 +-
>  drivers/pinctrl/starfive/Kconfig              |  37 +
>  drivers/pinctrl/starfive/Makefile             |   8 +
>  drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 718 ++++++++++++++
>  drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 925 +++++++++++++++++
>  .../pinctrl-starfive-jh7100.c}                |  10 +-
>  drivers/pinctrl/starfive/pinctrl-starfive.c   | 539 ++++++++++
>  drivers/pinctrl/starfive/pinctrl-starfive.h   | 131 +++
>  drivers/reset/Kconfig                         |   7 +-
>  drivers/reset/Makefile                        |   2 +-
>  drivers/reset/reset-starfive-jh7100.c         | 173 ----
>  drivers/reset/reset-starfive.c                | 218 ++++
>  drivers/soc/Makefile                          |   2 +-
>  drivers/soc/sifive/Kconfig                    |   2 +-
>  drivers/soc/sifive/sifive_l2_cache.c          |  86 +-
>  .../dt-bindings/clock/starfive-jh7110-aon.h   |  26 +
>  .../dt-bindings/clock/starfive-jh7110-sys.h   | 215 ++++
>  ...l-starfive.h => pinctrl-starfive-jh7100.h} |   6 +-
>  .../pinctrl/pinctrl-starfive-jh7110.h         | 931 ++++++++++++++++++
>  include/dt-bindings/reset/starfive-jh7110.h   | 154 +++
>  48 files changed, 6604 insertions(+), 1019 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
>  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
>  create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7110-reset.yaml
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>  delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
>  create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
>  create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
>  create mode 100644 drivers/clk/starfive/clk-starfive.c
>  create mode 100644 drivers/clk/starfive/clk-starfive.h
>  create mode 100644 drivers/pinctrl/starfive/Kconfig
>  create mode 100644 drivers/pinctrl/starfive/Makefile
>  create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
>  create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
>  rename drivers/pinctrl/{pinctrl-starfive.c => starfive/pinctrl-starfive-jh7100.c} (99%)
>  create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
>  create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
>  delete mode 100644 drivers/reset/reset-starfive-jh7100.c
>  create mode 100644 drivers/reset/reset-starfive.c
>  create mode 100644 include/dt-bindings/clock/starfive-jh7110-aon.h
>  create mode 100644 include/dt-bindings/clock/starfive-jh7110-sys.h
>  rename include/dt-bindings/pinctrl/{pinctrl-starfive.h => pinctrl-starfive-jh7100.h} (98%)
>  create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
>  create mode 100644 include/dt-bindings/reset/starfive-jh7110.h
>
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support

[Hal Feng]

On Wed, 5 Oct 2022 15:05:45 +0200, Emil Renner Berthing wrote:
> On Thu, 29 Sept 2022 at 16:34, Hal Feng <hal.feng@linux.starfivetech.com> wrote:
> > This series adds basic support for the StarFive JH7110 RISC-V SoC to
> > boot up and get a serial console. This series includes basic clock,
> > reset, pinctrl and uart drivers, which are necessary for booting.
> > It's should be noted that the reset and clock driver codes of JH7110
> > are partly common with those of JH7100, so the common codes are
> > factored out and can be reused by drivers of JH7110 and other more
> > SoCs from StarFive.
> >
> > The JH7110 is the upgraded version of JH7100 and also the first official
> > released version of JH71XX series SoCs from StarFive Technology Ltd.
> > The VisionFive 2 boards equipped with JH7110 SoCs are launched
> > recently [1]. More information and support can visit RVspace wiki [2].
> >
> > This series is also available at
> > https://github.com/hal-feng/linux/commits/visionfive2-minimal
> >
> > [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> > [2] https://wiki.rvspace.org/
> 
> Hi Hal,
> 
> Firstly thanks for working on this! And sorry about the late reply. On
> the next version could you please cc
> emil.renner.berthing@canonical.com since it seems to handle the
> mailing list a bit better.

OK, I will cc to your new email instead on v2.

Best Regards,
Hal

> I see you've changed the clock/reset and pinctrl quite a bit, so I'll
> comment on that separatel