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From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	"Davidlohr Bueso" <dave@stgolabs.net>,
	Robert Richter <rrichter@amd.com>
Subject: [PATCH v2 09/12] cxl: Extend devm_cxl_enumerate_ports() to support restricted devices (RCDs)
Date: Tue, 18 Oct 2022 15:23:37 +0200	[thread overview]
Message-ID: <20221018132341.76259-10-rrichter@amd.com> (raw)
In-Reply-To: <20221018132341.76259-1-rrichter@amd.com>

The PCIe Software View of an RCH and RCD is different to VH mode. An
RCD is paired with an RCH and shows up as RCiEP. Its downstream and
upstream ports are hidden to the PCI hierarchy. This different PCI
topology requires a different handling of RCHs.

Extend devm_cxl_enumerate_ports() to support restricted devices
(RCDs). If an RCD is detected all to do is to search its corresponding
RCH's port and attach the EP to it. Update cxl_mem_find_port() for
proper removal of the EP in delete_endpoint().

Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/cxl/core/port.c | 45 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 4b15481426f7..35f8fa98904e 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1384,16 +1384,56 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
 	return rc;
 }
 
+static inline bool is_cxl_restricted(struct cxl_memdev *cxlmd)
+{
+	struct device *parent = cxlmd->dev.parent;
+	if (!dev_is_pci(parent))
+		return false;
+	return pci_pcie_type(to_pci_dev(parent)) == PCI_EXP_TYPE_RC_END;
+}
+
+static int restricted_host_enumerate_port(struct cxl_memdev *cxlmd)
+{
+	struct device *dev, *dport_dev, *uport_dev;
+	int count;
+
+	if (!is_cxl_restricted(cxlmd))
+		return 0;
+
+	/*
+	 * The cxlmd is an RCD, the dport_dev of it is the PCI device
+	 * and the uport_dev is its host bridge which is the parent of
+	 * the PCI device.
+	 */
+	dev = &cxlmd->dev;			/* cxlmd */
+	dport_dev = dev->parent;		/* pci_dev */
+	uport_dev = dev->parent->parent;	/* pci_host_bridge */
+
+	count = find_port_attach_ep(cxlmd, uport_dev, dport_dev, dev);
+
+	/* If missing the host is not yet ready. */
+	if (!count)
+		return -EAGAIN;
+
+	return count;
+}
+
 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
 {
 	struct device *dev = &cxlmd->dev;
 	struct device *iter;
-	int rc;
+	int count, rc;
 
 	rc = devm_add_action_or_reset(&cxlmd->dev, cxl_detach_ep, cxlmd);
 	if (rc)
 		return rc;
 
+	count = restricted_host_enumerate_port(cxlmd);
+	if (count < 0)
+		return count;
+	if (count)
+		return 0;
+
 	/*
 	 * Scan for and add all cxl_ports in this device's ancestry.
 	 * Repeat until no more ports are added. Abort if a port add
@@ -1445,6 +1485,9 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, CXL);
 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
 				   struct cxl_dport **dport)
 {
+	if (is_cxl_restricted(cxlmd))
+		return find_cxl_port(cxlmd->dev.parent, dport);
+
 	return find_cxl_port(grandparent(&cxlmd->dev), dport);
 }
 EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL);
-- 
2.30.2


  parent reply	other threads:[~2022-10-18 13:25 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-18 13:23 [PATCH v2 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-10-18 13:23 ` [PATCH v2 01/12] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-10-20 23:56   ` Dan Williams
2022-10-21  8:54     ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 02/12] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-10-21  0:01   ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 03/12] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-10-21  0:20   ` Dan Williams
2022-10-21  8:57     ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 04/12] cxl: Unify debug messages when calling devm_cxl_add_dport() Robert Richter
2022-10-21  0:32   ` Dan Williams
2022-10-21  9:00     ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 05/12] cxl/acpi: Improve debug messages in cxl_acpi_probe() Robert Richter
2022-10-21  1:00   ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 06/12] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-10-18 13:31   ` Rafael J. Wysocki
2022-10-18 18:41     ` Robert Richter
2022-10-18 18:57       ` Rafael J. Wysocki
2022-10-19 10:46         ` Robert Richter
2022-10-21  5:17   ` Dan Williams
2022-10-24 21:04     ` Robert Richter
2022-10-24 21:24       ` Dan Williams
2022-10-24 22:37         ` Dan Williams
     [not found]           ` <63cd195a-f5d0-b016-d833-b3a9c86ff6ee@intel.com>
2022-10-24 23:50             ` Robert Richter
2022-10-24 23:57               ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 07/12] cxl: Remove dev_is_cxl_root_child() check in devm_cxl_enumerate_ports() Robert Richter
2022-10-21  5:38   ` Dan Williams
2022-10-21  6:32     ` Verma, Vishal L
2022-11-09 14:33       ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 08/12] cxl: Factor out code in devm_cxl_enumerate_ports() to find_port_attach_ep() Robert Richter
2022-10-18 13:23 ` Robert Richter [this message]
2022-10-18 13:23 ` [PATCH v2 10/12] cxl: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-10-18 13:23 ` [PATCH v2 11/12] cxl: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-10-18 13:23 ` [PATCH v2 12/12] cxl: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter

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