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From: Robert Richter <rrichter@amd.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>,
	<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>, Len Brown <lenb@kernel.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	"Terry Bowman" <terry.bowman@amd.com>
Subject: Re: [PATCH v2 06/12] cxl/acpi: Extract component registers of restricted hosts from RCRB
Date: Wed, 19 Oct 2022 12:46:28 +0200	[thread overview]
Message-ID: <Y0/VhNAzmZOcUT01@rric.localdomain> (raw)
In-Reply-To: <CAJZ5v0gtbzD9H9OEWS1X5OnFCntFTAnNbxwrU3FpZbnR5rQ6fQ@mail.gmail.com>

On 18.10.22 20:57:02, Rafael J. Wysocki wrote:
> On Tue, Oct 18, 2022 at 8:42 PM Robert Richter <rrichter@amd.com> wrote:
> >
> > On 18.10.22 15:31:16, Rafael J. Wysocki wrote:
> > > On Tue, Oct 18, 2022 at 3:24 PM Robert Richter <rrichter@amd.com> wrote:
> > > >
> > > > A downstream port must be connected to a component register block.
> > > > For restricted hosts the base address is determined from the RCRB. The
> > > > RCRB is provided by the host's CEDT CHBS entry. Rework CEDT parser to
> > > > get the RCRB and add code to extract the component register block from
> > > > it.
> > > >
> > > > RCRB's BAR[0..1] point to the component block containing CXL subsystem
> > > > component registers. MEMBAR extraction follows the PCI base spec here,
> > > > esp. 64 bit extraction and memory range alignment (6.0, 7.5.1.2.1).
> > > >
> > > > Note: Right now the component register block is used for HDM decoder
> > > > capability only which is optional for RCDs. If unsupported by the RCD,
> > > > the HDM init will fail. It is future work to bypass it in this case.
> > > >
> > > > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> > >
> > > What does this S-o-B mean?  If this person is your co-developer, you
> > > need to add a Co-developed-by tag to clarify that.
> > >
> > > > Signed-off-by: Robert Richter <rrichter@amd.com>
> >
> > I picked up an early patch and modified it significantly, so I just
> > left the S-o-B.
> 
> In that case the right thing to do is to mention the original author
> in the changelog instead of retaining the S-o-b.
> 
> > I could change this to a Co-developed-by tag.
> 
> Co-developed-by should be used in addition to and not instead of S-o-b
> when one of the authors is sending a patch.  However, all of the
> authors need to be familiar with the patch in the form in which it is
> being sent then.
> 
> > IMO, the S-o-B is ok, but could be wrong here.
> 
> It isn't, at least not without a Co-developed-by tag.
> 
> There are 3 cases in which S-o-b is OK AFAICS:
> 
> 1. When it matches the From: address.
> 2. When there is a matching Co-developed-by.
> 3. When maintainers pick up patches and add their own S-o-b.
> 
> This case is none of the above.

Will add a Co-developed-by tag in my next version. Thanks for pointing
that out.

-Robert

  reply	other threads:[~2022-10-19 11:26 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-18 13:23 [PATCH v2 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-10-18 13:23 ` [PATCH v2 01/12] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-10-20 23:56   ` Dan Williams
2022-10-21  8:54     ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 02/12] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-10-21  0:01   ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 03/12] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-10-21  0:20   ` Dan Williams
2022-10-21  8:57     ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 04/12] cxl: Unify debug messages when calling devm_cxl_add_dport() Robert Richter
2022-10-21  0:32   ` Dan Williams
2022-10-21  9:00     ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 05/12] cxl/acpi: Improve debug messages in cxl_acpi_probe() Robert Richter
2022-10-21  1:00   ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 06/12] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-10-18 13:31   ` Rafael J. Wysocki
2022-10-18 18:41     ` Robert Richter
2022-10-18 18:57       ` Rafael J. Wysocki
2022-10-19 10:46         ` Robert Richter [this message]
2022-10-21  5:17   ` Dan Williams
2022-10-24 21:04     ` Robert Richter
2022-10-24 21:24       ` Dan Williams
2022-10-24 22:37         ` Dan Williams
     [not found]           ` <63cd195a-f5d0-b016-d833-b3a9c86ff6ee@intel.com>
2022-10-24 23:50             ` Robert Richter
2022-10-24 23:57               ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 07/12] cxl: Remove dev_is_cxl_root_child() check in devm_cxl_enumerate_ports() Robert Richter
2022-10-21  5:38   ` Dan Williams
2022-10-21  6:32     ` Verma, Vishal L
2022-11-09 14:33       ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 08/12] cxl: Factor out code in devm_cxl_enumerate_ports() to find_port_attach_ep() Robert Richter
2022-10-18 13:23 ` [PATCH v2 09/12] cxl: Extend devm_cxl_enumerate_ports() to support restricted devices (RCDs) Robert Richter
2022-10-18 13:23 ` [PATCH v2 10/12] cxl: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-10-18 13:23 ` [PATCH v2 11/12] cxl: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-10-18 13:23 ` [PATCH v2 12/12] cxl: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter

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