From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
Robert Richter <rrichter@amd.com>
Subject: [PATCH v2 04/12] cxl: Unify debug messages when calling devm_cxl_add_dport()
Date: Tue, 18 Oct 2022 15:23:32 +0200 [thread overview]
Message-ID: <20221018132341.76259-5-rrichter@amd.com> (raw)
In-Reply-To: <20221018132341.76259-1-rrichter@amd.com>
CXL dports are added in a couple of code paths using devm_cxl_add_
dport(). Debug messages are individually generated, but are incomplete
and inconsistent. Change this by moving its generation to devm_cxl_
add_dport(). This unifies the messages and reduces code duplication.
Also, generate messages on failure. Use a __devm_cxl_add_dport()
wrapper to keep the readability of the error exits.
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/acpi.c | 7 ++----
drivers/cxl/core/pci.c | 2 --
drivers/cxl/core/port.c | 48 +++++++++++++++++++++++++-----------
tools/testing/cxl/test/cxl.c | 8 +-----
4 files changed, 37 insertions(+), 28 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 767a91f44221..31e104f0210f 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -282,12 +282,9 @@ static int add_host_bridge_dport(struct device *match, void *arg)
}
dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
- if (IS_ERR(dport)) {
- dev_err(host, "failed to add downstream port: %s\n",
- dev_name(match));
+ if (IS_ERR(dport))
return PTR_ERR(dport);
- }
- dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match));
+
return 0;
}
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 9240df53ed87..0dbbe8d39b07 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -62,8 +62,6 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
}
ctx->count++;
- dev_dbg(&port->dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
-
return 0;
}
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 9bfd01b4e5b5..0431ed860d8e 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -892,20 +892,10 @@ static void cxl_dport_unlink(void *data)
sysfs_remove_link(&port->dev.kobj, link_name);
}
-/**
- * devm_cxl_add_dport - append downstream port data to a cxl_port
- * @port: the cxl_port that references this dport
- * @dport_dev: firmware or PCI device representing the dport
- * @port_id: identifier for this dport in a decoder's target list
- * @component_reg_phys: optional location of CXL component registers
- *
- * Note that dports are appended to the devm release action's of the
- * either the port's host (for root ports), or the port itself (for
- * switch ports)
- */
-struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
- struct device *dport_dev, int port_id,
- resource_size_t component_reg_phys)
+static struct cxl_dport *__devm_cxl_add_dport(struct cxl_port *port,
+ struct device *dport_dev,
+ int port_id,
+ resource_size_t component_reg_phys)
{
char link_name[CXL_TARGET_STRLEN];
struct cxl_dport *dport;
@@ -957,6 +947,36 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
return dport;
}
+
+/**
+ * devm_cxl_add_dport - append downstream port data to a cxl_port
+ * @port: the cxl_port that references this dport
+ * @dport_dev: firmware or PCI device representing the dport
+ * @port_id: identifier for this dport in a decoder's target list
+ * @component_reg_phys: optional location of CXL component registers
+ *
+ * Note that dports are appended to the devm release action's of the
+ * either the port's host (for root ports), or the port itself (for
+ * switch ports)
+ */
+struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
+ struct device *dport_dev, int port_id,
+ resource_size_t component_reg_phys)
+{
+ struct cxl_dport *dport;
+
+ dport = __devm_cxl_add_dport(port, dport_dev, port_id,
+ component_reg_phys);
+ if (IS_ERR(dport)) {
+ dev_dbg(dport_dev, "failed to add dport to %s: %ld\n",
+ dev_name(&port->dev), PTR_ERR(dport));
+ } else {
+ dev_dbg(dport_dev, "dport added to %s\n",
+ dev_name(&port->dev));
+ }
+
+ return dport;
+}
EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, CXL);
static int add_ep(struct cxl_ep *new)
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index a072b2d3e726..c610625e8261 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -582,14 +582,8 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id,
CXL_RESOURCE_NONE);
- if (IS_ERR(dport)) {
- dev_err(dev, "failed to add dport: %s (%ld)\n",
- dev_name(&pdev->dev), PTR_ERR(dport));
+ if (IS_ERR(dport))
return PTR_ERR(dport);
- }
-
- dev_dbg(dev, "add dport%d: %s\n", pdev->id,
- dev_name(&pdev->dev));
}
return 0;
--
2.30.2
next prev parent reply other threads:[~2022-10-18 13:24 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 13:23 [PATCH v2 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-10-18 13:23 ` [PATCH v2 01/12] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-10-20 23:56 ` Dan Williams
2022-10-21 8:54 ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 02/12] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-10-21 0:01 ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 03/12] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-10-21 0:20 ` Dan Williams
2022-10-21 8:57 ` Robert Richter
2022-10-18 13:23 ` Robert Richter [this message]
2022-10-21 0:32 ` [PATCH v2 04/12] cxl: Unify debug messages when calling devm_cxl_add_dport() Dan Williams
2022-10-21 9:00 ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 05/12] cxl/acpi: Improve debug messages in cxl_acpi_probe() Robert Richter
2022-10-21 1:00 ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 06/12] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-10-18 13:31 ` Rafael J. Wysocki
2022-10-18 18:41 ` Robert Richter
2022-10-18 18:57 ` Rafael J. Wysocki
2022-10-19 10:46 ` Robert Richter
2022-10-21 5:17 ` Dan Williams
2022-10-24 21:04 ` Robert Richter
2022-10-24 21:24 ` Dan Williams
2022-10-24 22:37 ` Dan Williams
[not found] ` <63cd195a-f5d0-b016-d833-b3a9c86ff6ee@intel.com>
2022-10-24 23:50 ` Robert Richter
2022-10-24 23:57 ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 07/12] cxl: Remove dev_is_cxl_root_child() check in devm_cxl_enumerate_ports() Robert Richter
2022-10-21 5:38 ` Dan Williams
2022-10-21 6:32 ` Verma, Vishal L
2022-11-09 14:33 ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 08/12] cxl: Factor out code in devm_cxl_enumerate_ports() to find_port_attach_ep() Robert Richter
2022-10-18 13:23 ` [PATCH v2 09/12] cxl: Extend devm_cxl_enumerate_ports() to support restricted devices (RCDs) Robert Richter
2022-10-18 13:23 ` [PATCH v2 10/12] cxl: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-10-18 13:23 ` [PATCH v2 11/12] cxl: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-10-18 13:23 ` [PATCH v2 12/12] cxl: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
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