* [PATCH v5 1/8] dt-bindings: ufs: qcom: Add sm6115 binding [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> @ 2022-10-30 9:42 ` Iskren Chernev 2022-12-15 11:57 ` Bhupesh Sharma 2022-10-30 9:42 ` [PATCH v5 2/8] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Iskren Chernev ` (6 subsequent siblings) 7 siblings, 1 reply; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio, Alim Akhtar, Avri Altman, Bart Van Assche, Krzysztof Kozlowski, linux-scsi, linux-kernel Add SM6115 UFS to DT schema. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index f2d6298d926c..b517d76215e3 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -28,6 +28,7 @@ properties: - qcom,msm8998-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc + - qcom,sm6115-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - qcom,sm8250-ufshc @@ -178,6 +179,31 @@ allOf: minItems: 1 maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-ufshc + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: ice_core_clk + reg: + minItems: 2 + maxItems: 2 + # TODO: define clock bindings for qcom,msm8994-ufshc unevaluatedProperties: false -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 1/8] dt-bindings: ufs: qcom: Add sm6115 binding 2022-10-30 9:42 ` [PATCH v5 1/8] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev @ 2022-12-15 11:57 ` Bhupesh Sharma 0 siblings, 0 replies; 22+ messages in thread From: Bhupesh Sharma @ 2022-12-15 11:57 UTC (permalink / raw) To: Iskren Chernev, Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Andy Gross, Konrad Dybcio, Alim Akhtar, Avri Altman, Bart Van Assche, Krzysztof Kozlowski, linux-scsi, linux-kernel On 10/30/22 3:12 PM, Iskren Chernev wrote: > Add SM6115 UFS to DT schema. > > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > index f2d6298d926c..b517d76215e3 100644 > --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > @@ -28,6 +28,7 @@ properties: > - qcom,msm8998-ufshc > - qcom,sc8280xp-ufshc > - qcom,sdm845-ufshc > + - qcom,sm6115-ufshc > - qcom,sm6350-ufshc > - qcom,sm8150-ufshc > - qcom,sm8250-ufshc > @@ -178,6 +179,31 @@ allOf: > minItems: 1 > maxItems: 1 > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sm6115-ufshc > + then: > + properties: > + clocks: > + minItems: 8 > + maxItems: 8 > + clock-names: > + items: > + - const: core_clk > + - const: bus_aggr_clk > + - const: iface_clk > + - const: core_clk_unipro > + - const: ref_clk > + - const: tx_lane0_sync_clk > + - const: rx_lane0_sync_clk > + - const: ice_core_clk > + reg: > + minItems: 2 > + maxItems: 2 > + > # TODO: define clock bindings for qcom,msm8994-ufshc > > unevaluatedProperties: false Seems this hasn't made way to linux-next yet. Hence we get the following error with $ make dtbs_check: arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dtb: ufs@4804000: compatible:0: 'qcom,sm6115-ufshc' is not one of ['qcom,msm8994-ufshc', 'qcom,msm8996-ufshc', 'qcom,msm8998-ufshc', 'qcom,sc8280xp-ufshc', 'qcom,sdm845-ufshc', 'qcom,sm6350-ufshc', 'qcom,sm8150-ufshc', 'qcom,sm8250-ufshc', 'qcom,sm8350-ufshc', 'qcom,sm8450-ufshc'] From schema: Documentation/devicetree/bindings/ufs/qcom,ufs.yaml arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dtb: ufs@4804000: Unevaluated properties are not allowed ('compatible' was unexpected) From schema: Documentation/devicetree/bindings/ufs/qcom,ufs.yaml If, it helps to get the review / merge happen: Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> @Rob, @Krzysztof: Please help merge this. Thanks. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 2/8] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> 2022-10-30 9:42 ` [PATCH v5 1/8] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev @ 2022-10-30 9:42 ` Iskren Chernev 2022-10-30 9:42 ` [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 Iskren Chernev ` (5 subsequent siblings) 7 siblings, 0 replies; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Iskren Chernev, Caleb Connolly, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, linux-kernel oneplus,billie2 (OnePlus Nord N100) is based on QualComm Snapdragon SM4250 SoC. Add support for the same in dt-bindings. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Caleb Connolly <caleb@connolly.tech> --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 207e28260206..7048a1fd77a7 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -54,6 +54,8 @@ description: | sdm845 sdx55 sdx65 + sm4250 + sm6115 sm6125 sm6350 sm7225 @@ -708,6 +710,11 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - oneplus,billie2 + - const: qcom,sm4250 + - items: - enum: - sony,pdx201 -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> 2022-10-30 9:42 ` [PATCH v5 1/8] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev 2022-10-30 9:42 ` [PATCH v5 2/8] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Iskren Chernev @ 2022-10-30 9:42 ` Iskren Chernev 2022-10-31 21:44 ` Rob Herring 2022-11-04 14:45 ` Vinod Koul 2022-10-30 9:42 ` [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 Iskren Chernev ` (4 subsequent siblings) 7 siblings, 2 replies; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Iskren Chernev, Andy Gross, Konrad Dybcio, Vinod Koul, Krzysztof Kozlowski, dmaengine, linux-kernel From: Adam Skladowski <a39.skl@gmail.com> Document the compatible for GPI DMA controller on SM6115 SoC. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index 0c2894498845..232895fa1d8d 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - qcom,sc7280-gpi-dma + - qcom,sm6115-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 2022-10-30 9:42 ` [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 Iskren Chernev @ 2022-10-31 21:44 ` Rob Herring 2022-11-04 14:45 ` Vinod Koul 1 sibling, 0 replies; 22+ messages in thread From: Rob Herring @ 2022-10-31 21:44 UTC (permalink / raw) To: Iskren Chernev Cc: Adam Skladowski, Rob Herring, Bjorn Andersson, Konrad Dybcio, ~postmarketos/upstreaming, Andy Gross, phone-devel, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel, Krzysztof Kozlowski, Vinod Koul, dmaengine On Sun, 30 Oct 2022 11:42:53 +0200, Iskren Chernev wrote: > From: Adam Skladowski <a39.skl@gmail.com> > > Document the compatible for GPI DMA controller on SM6115 SoC. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > --- > Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 2022-10-30 9:42 ` [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 Iskren Chernev 2022-10-31 21:44 ` Rob Herring @ 2022-11-04 14:45 ` Vinod Koul 1 sibling, 0 replies; 22+ messages in thread From: Vinod Koul @ 2022-11-04 14:45 UTC (permalink / raw) To: Iskren Chernev Cc: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring, phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, dmaengine, linux-kernel On 30-10-22, 11:42, Iskren Chernev wrote: > From: Adam Skladowski <a39.skl@gmail.com> > > Document the compatible for GPI DMA controller on SM6115 SoC. Applied, thanks -- ~Vinod ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> ` (2 preceding siblings ...) 2022-10-30 9:42 ` [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 Iskren Chernev @ 2022-10-30 9:42 ` Iskren Chernev 2022-10-31 21:45 ` Rob Herring 2022-12-15 15:12 ` Dmitry Baryshkov 2022-10-30 9:42 ` [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support Iskren Chernev ` (3 subsequent siblings) 7 siblings, 2 replies; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Iskren Chernev, Will Deacon, Robin Murphy, Joerg Roedel, Krzysztof Kozlowski, linux-arm-kernel, iommu, linux-kernel From: Adam Skladowski <a39.skl@gmail.com> Add compatible for the Qualcomm SM6115 platform to the ARM SMMU DeviceTree binding. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..71f8f638a1f8 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -41,6 +41,7 @@ properties: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 + - qcom,sm6115-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8150-smmu-500 -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 2022-10-30 9:42 ` [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 Iskren Chernev @ 2022-10-31 21:45 ` Rob Herring 2022-12-15 15:12 ` Dmitry Baryshkov 1 sibling, 0 replies; 22+ messages in thread From: Rob Herring @ 2022-10-31 21:45 UTC (permalink / raw) To: Iskren Chernev Cc: iommu, Will Deacon, Joerg Roedel, Krzysztof Kozlowski, linux-arm-kernel, linux-kernel, linux-arm-msm, Robin Murphy, devicetree, Bjorn Andersson, Rob Herring, Adam Skladowski, Krzysztof Kozlowski, phone-devel, ~postmarketos/upstreaming On Sun, 30 Oct 2022 11:42:54 +0200, Iskren Chernev wrote: > From: Adam Skladowski <a39.skl@gmail.com> > > Add compatible for the Qualcomm SM6115 platform to the ARM SMMU > DeviceTree binding. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 2022-10-30 9:42 ` [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 Iskren Chernev 2022-10-31 21:45 ` Rob Herring @ 2022-12-15 15:12 ` Dmitry Baryshkov 1 sibling, 0 replies; 22+ messages in thread From: Dmitry Baryshkov @ 2022-12-15 15:12 UTC (permalink / raw) To: Iskren Chernev, Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Will Deacon, Robin Murphy, Joerg Roedel, Krzysztof Kozlowski, linux-arm-kernel, iommu, linux-kernel On 30/10/2022 11:42, Iskren Chernev wrote: > From: Adam Skladowski <a39.skl@gmail.com> > > Add compatible for the Qualcomm SM6115 platform to the ARM SMMU > DeviceTree binding. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 9066e6df1ba1..71f8f638a1f8 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -41,6 +41,7 @@ properties: > - qcom,sdm845-smmu-500 > - qcom,sdx55-smmu-500 > - qcom,sdx65-smmu-500 > + - qcom,sm6115-smmu-500 > - qcom,sm6350-smmu-500 > - qcom,sm6375-smmu-500 > - qcom,sm8150-smmu-500 Please rebase on top of linux-next and use a generic compatible + SoC specific compatible. -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> ` (3 preceding siblings ...) 2022-10-30 9:42 ` [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 Iskren Chernev @ 2022-10-30 9:42 ` Iskren Chernev 2022-12-15 15:10 ` Dmitry Baryshkov 2022-10-30 9:42 ` [PATCH v5 6/8] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev ` (2 subsequent siblings) 7 siblings, 1 reply; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Iskren Chernev, Will Deacon, Robin Murphy, Joerg Roedel, Konrad Dybcio, Sai Prakash Ranjan, Emma Anholt, Rob Clark, linux-arm-kernel, iommu, linux-kernel From: Adam Skladowski <a39.skl@gmail.com> Add the Qualcomm SM6115 platform to the list of compatible, this target uses MMU500 for both APSS and GPU. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b2708de25ea3..526fec79b4fe 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -432,6 +432,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,sc8280xp-smmu-500" }, { .compatible = "qcom,sdm630-smmu-v2" }, { .compatible = "qcom,sdm845-smmu-500" }, + { .compatible = "qcom,sm6115-smmu-500" }, { .compatible = "qcom,sm6125-smmu-500" }, { .compatible = "qcom,sm6350-smmu-500" }, { .compatible = "qcom,sm6375-smmu-500" }, -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support 2022-10-30 9:42 ` [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support Iskren Chernev @ 2022-12-15 15:10 ` Dmitry Baryshkov 2022-12-15 15:14 ` Dmitry Baryshkov 0 siblings, 1 reply; 22+ messages in thread From: Dmitry Baryshkov @ 2022-12-15 15:10 UTC (permalink / raw) To: Iskren Chernev, Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Will Deacon, Robin Murphy, Joerg Roedel, Konrad Dybcio, Sai Prakash Ranjan, Emma Anholt, Rob Clark, linux-arm-kernel, iommu, linux-kernel On 30/10/2022 11:42, Iskren Chernev wrote: > From: Adam Skladowski <a39.skl@gmail.com> > > Add the Qualcomm SM6115 platform to the list of compatible, > this target uses MMU500 for both APSS and GPU. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> This needs to rebased on linux-next (or 6.2-rc1 once it's out). > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index b2708de25ea3..526fec79b4fe 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -432,6 +432,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { > { .compatible = "qcom,sc8280xp-smmu-500" }, > { .compatible = "qcom,sdm630-smmu-v2" }, > { .compatible = "qcom,sdm845-smmu-500" }, > + { .compatible = "qcom,sm6115-smmu-500" }, > { .compatible = "qcom,sm6125-smmu-500" }, > { .compatible = "qcom,sm6350-smmu-500" }, > { .compatible = "qcom,sm6375-smmu-500" }, -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support 2022-12-15 15:10 ` Dmitry Baryshkov @ 2022-12-15 15:14 ` Dmitry Baryshkov 2022-12-19 10:01 ` Iskren Chernev 0 siblings, 1 reply; 22+ messages in thread From: Dmitry Baryshkov @ 2022-12-15 15:14 UTC (permalink / raw) To: Iskren Chernev, Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Will Deacon, Robin Murphy, Joerg Roedel, Konrad Dybcio, Sai Prakash Ranjan, Emma Anholt, Rob Clark, linux-arm-kernel, iommu, linux-kernel On 15/12/2022 17:10, Dmitry Baryshkov wrote: > On 30/10/2022 11:42, Iskren Chernev wrote: >> From: Adam Skladowski <a39.skl@gmail.com> >> >> Add the Qualcomm SM6115 platform to the list of compatible, >> this target uses MMU500 for both APSS and GPU. >> >> Signed-off-by: Adam Skladowski <a39.skl@gmail.com> >> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > > This needs to rebased on linux-next (or 6.2-rc1 once it's out). To add on top of that. linux-next has the following comment: /* * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need * special handling and can not be covered by the qcom,smmu-500 entry. */ So, hopefully you can skip this patch completely by depending on the generic "qcom,smmu-500" compatible. -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support 2022-12-15 15:14 ` Dmitry Baryshkov @ 2022-12-19 10:01 ` Iskren Chernev 2022-12-19 11:28 ` Dmitry Baryshkov 0 siblings, 1 reply; 22+ messages in thread From: Iskren Chernev @ 2022-12-19 10:01 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring, phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Will Deacon, Robin Murphy, Joerg Roedel, Konrad Dybcio, Sai Prakash Ranjan, Emma Anholt, Rob Clark, linux-arm-kernel, iommu, linux-kernel > So, hopefully you can skip this patch completely by depending on the > generic "qcom,smmu-500" compatible. To be clear -- I still need the qcom,SOC-smmu-500 compatible in DT and bindings, but not in the driver (i.e driver will pick generic)? Then this can indeed be dropped (but it is merged in linux-next ATM, 6.2-rc1 based next won't have it, I guess?). ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support 2022-12-19 10:01 ` Iskren Chernev @ 2022-12-19 11:28 ` Dmitry Baryshkov 0 siblings, 0 replies; 22+ messages in thread From: Dmitry Baryshkov @ 2022-12-19 11:28 UTC (permalink / raw) To: Iskren Chernev Cc: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring, phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Adam Skladowski, Will Deacon, Robin Murphy, Joerg Roedel, Konrad Dybcio, Sai Prakash Ranjan, Emma Anholt, Rob Clark, linux-arm-kernel, iommu, linux-kernel Hi, On Mon, 19 Dec 2022 at 12:01, Iskren Chernev <iskren.chernev@gmail.com> wrote: > > > So, hopefully you can skip this patch completely by depending on the > > generic "qcom,smmu-500" compatible. > > To be clear -- I still need the qcom,SOC-smmu-500 compatible in DT and > bindings, but not in the driver (i.e driver will pick generic)? > > Then this can indeed be dropped (but it is merged in linux-next ATM, > 6.2-rc1 based next won't have it, I guess?). The thread got bumped in my email client, so I replied with my review as if these patches were brand new. However I failed to notice that the patches were already accepted by Will Deacon. And that my rework happened already on top of your patches. So, you don't have to do anything, the IOMMU part will be a part of 6.3. Please excuse me for the noise. -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 6/8] arm64: dts: qcom: sm6115: Add basic soc dtsi [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> ` (4 preceding siblings ...) 2022-10-30 9:42 ` [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support Iskren Chernev @ 2022-10-30 9:42 ` Iskren Chernev 2022-10-31 21:17 ` Konrad Dybcio 2022-10-30 9:42 ` [PATCH v5 7/8] arm64: dts: qcom: sm4250: Add " Iskren Chernev 2022-10-30 9:42 ` [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev 7 siblings, 1 reply; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, linux-kernel Add support for Qualcomm SM6115 SoC. This includes: - GCC - Pinctrl - RPM (CC+PD) - USB - MMC - UFS Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 854 +++++++++++++++++++++++++++ 1 file changed, 854 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi new file mode 100644 index 000000000000..0340ed21be05 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> + */ + +#include <dt-bindings/clock/qcom,gcc-sm6115.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: memory@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@46000000 { + compatible = "qcom,smem"; + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + cdsp_sec_mem: memory@46200000 { + reg = <0x0 0x46200000 0x0 0x1e00000>; + no-map; + }; + + pil_modem_mem: memory@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: memory@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: memory@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_cdsp_mem: memory@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_mem: memory@53800000 { + reg = <0x0 0x53800000 0x0 0x2800000>; + no-map; + }; + + pil_ipa_fw_mem: memory@56100000 { + reg = <0x0 0x56100000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@56110000 { + reg = <0x0 0x56110000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: memory@56115000 { + reg = <0x0 0x56115000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: memory@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: memory@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: memory@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp5 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; + }; + }; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x00340000 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 121>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_1_hsphy: phy@1613000 { + compatible = "qcom,sm6115-qusb2-phy"; + reg = <0x01613000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + + status = "disabled"; + }; + + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x01b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x045f0000 0x7000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc"; + + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x100 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6115-qmp-ufs-phy"; + reg = <0x04807000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@4807400 { + reg = <0x4807400 0x098>, + <0x4807600 0x130>, + <0x4807c00 0x16c>; + #phy-cells = <0>; + }; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; + reg = <0x04ef8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x04e00000 0xcd00>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; + reg = <0x0c600000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,sm6115-apcs-hmss-global"; + reg = <0x0f111000 0x1000>; + + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0f120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <19200000>; + + frame@f121000 { + reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + frame@f123000 { + reg = <0x0f123000 0x1000>; + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f124000 { + reg = <0x0f124000 0x1000>; + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f125000 { + reg = <0x0f125000 0x1000>; + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f126000 { + reg = <0x0f126000 0x1000>; + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f127000 { + reg = <0x0f127000 0x1000>; + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f128000 { + reg = <0x0f128000 0x1000>; + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 6/8] arm64: dts: qcom: sm6115: Add basic soc dtsi 2022-10-30 9:42 ` [PATCH v5 6/8] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev @ 2022-10-31 21:17 ` Konrad Dybcio 0 siblings, 0 replies; 22+ messages in thread From: Konrad Dybcio @ 2022-10-31 21:17 UTC (permalink / raw) To: Iskren Chernev, Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Andy Gross, Krzysztof Kozlowski, linux-kernel On 30.10.2022 10:42, Iskren Chernev wrote: > Add support for Qualcomm SM6115 SoC. This includes: > - GCC > - Pinctrl > - RPM (CC+PD) > - USB > - MMC > - UFS > > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm64/boot/dts/qcom/sm6115.dtsi | 854 +++++++++++++++++++++++++++ > 1 file changed, 854 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > new file mode 100644 > index 000000000000..0340ed21be05 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -0,0 +1,854 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> > + */ > + > +#include <dt-bindings/clock/qcom,gcc-sm6115.h> > +#include <dt-bindings/clock/qcom,rpmcc.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/power/qcom-rpmpd.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + }; > + }; > + > + CPU1: cpu@1 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x1>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU2: cpu@2 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x2>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU3: cpu@3 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x3>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU4: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1638>; > + dynamic-power-coefficient = <282>; > + next-level-cache = <&L2_1>; > + L2_1: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + }; > + }; > + > + CPU5: cpu@101 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x101>; > + capacity-dmips-mhz = <1638>; > + dynamic-power-coefficient = <282>; > + enable-method = "psci"; > + next-level-cache = <&L2_1>; > + }; > + > + CPU6: cpu@102 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x102>; > + capacity-dmips-mhz = <1638>; > + dynamic-power-coefficient = <282>; > + enable-method = "psci"; > + next-level-cache = <&L2_1>; > + }; > + > + CPU7: cpu@103 { > + device_type = "cpu"; > + compatible = "qcom,kryo260"; > + reg = <0x0 0x103>; > + capacity-dmips-mhz = <1638>; > + dynamic-power-coefficient = <282>; > + enable-method = "psci"; > + next-level-cache = <&L2_1>; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&CPU4>; > + }; > + > + core1 { > + cpu = <&CPU5>; > + }; > + > + core2 { > + cpu = <&CPU6>; > + }; > + > + core3 { > + cpu = <&CPU7>; > + }; > + }; > + }; > + }; > + > + firmware { > + scm: scm { > + compatible = "qcom,scm-sm6115", "qcom,scm"; > + #reset-cells = <1>; > + }; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x80000000 0 0>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + hyp_mem: memory@45700000 { > + reg = <0x0 0x45700000 0x0 0x600000>; > + no-map; > + }; > + > + xbl_aop_mem: memory@45e00000 { > + reg = <0x0 0x45e00000 0x0 0x140000>; > + no-map; > + }; > + > + sec_apps_mem: memory@45fff000 { > + reg = <0x0 0x45fff000 0x0 0x1000>; > + no-map; > + }; > + > + smem_mem: memory@46000000 { > + compatible = "qcom,smem"; > + reg = <0x0 0x46000000 0x0 0x200000>; > + no-map; > + > + hwlocks = <&tcsr_mutex 3>; > + qcom,rpm-msg-ram = <&rpm_msg_ram>; > + }; > + > + cdsp_sec_mem: memory@46200000 { > + reg = <0x0 0x46200000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_modem_mem: memory@4ab00000 { > + reg = <0x0 0x4ab00000 0x0 0x6900000>; > + no-map; > + }; > + > + pil_video_mem: memory@51400000 { > + reg = <0x0 0x51400000 0x0 0x500000>; > + no-map; > + }; > + > + wlan_msa_mem: memory@51900000 { > + reg = <0x0 0x51900000 0x0 0x100000>; > + no-map; > + }; > + > + pil_cdsp_mem: memory@51a00000 { > + reg = <0x0 0x51a00000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_adsp_mem: memory@53800000 { > + reg = <0x0 0x53800000 0x0 0x2800000>; > + no-map; > + }; > + > + pil_ipa_fw_mem: memory@56100000 { > + reg = <0x0 0x56100000 0x0 0x10000>; > + no-map; > + }; > + > + pil_ipa_gsi_mem: memory@56110000 { > + reg = <0x0 0x56110000 0x0 0x5000>; > + no-map; > + }; > + > + pil_gpu_mem: memory@56115000 { > + reg = <0x0 0x56115000 0x0 0x2000>; > + no-map; > + }; > + > + cont_splash_memory: memory@5c000000 { > + reg = <0x0 0x5c000000 0x0 0x00f00000>; > + no-map; > + }; > + > + dfps_data_memory: memory@5cf00000 { > + reg = <0x0 0x5cf00000 0x0 0x0100000>; > + no-map; > + }; > + > + removed_mem: memory@60000000 { > + reg = <0x0 0x60000000 0x0 0x3900000>; > + no-map; > + }; > + }; > + > + rpm-glink { > + compatible = "qcom,glink-rpm"; > + > + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; > + qcom,rpm-msg-ram = <&rpm_msg_ram>; > + mboxes = <&apcs_glb 0>; > + > + rpm_requests: rpm-requests { > + compatible = "qcom,rpm-sm6115"; > + qcom,glink-channels = "rpm_requests"; > + > + rpmcc: clock-controller { > + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; > + #clock-cells = <1>; > + }; > + > + rpmpd: power-controller { > + compatible = "qcom,sm6115-rpmpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmpd_opp_table>; > + > + rpmpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmpd_opp_min_svs: opp1 { > + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; > + }; > + > + rpmpd_opp_low_svs: opp2 { > + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; > + }; > + > + rpmpd_opp_svs: opp3 { > + opp-level = <RPM_SMD_LEVEL_SVS>; > + }; > + > + rpmpd_opp_svs_plus: opp4 { > + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; > + }; > + > + rpmpd_opp_nom: opp5 { > + opp-level = <RPM_SMD_LEVEL_NOM>; > + }; > + > + rpmpd_opp_nom_plus: opp6 { > + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; > + }; > + > + rpmpd_opp_turbo: opp7 { > + opp-level = <RPM_SMD_LEVEL_TURBO>; > + }; > + > + rpmpd_opp_turbo_plus: opp8 { > + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; > + }; > + }; > + }; > + }; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0 0xffffffff>; > + > + tcsr_mutex: hwlock@340000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x00340000 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + tlmm: pinctrl@500000 { > + compatible = "qcom,sm6115-tlmm"; > + reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; > + reg-names = "west", "south", "east"; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + gpio-ranges = <&tlmm 0 0 121>; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + sdc1_state_on: sdc1-on-state { > + clk-pins { > + pins = "sdc1_clk"; > + bias-disable; > + drive-strength = <16>; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + rclk-pins { > + pins = "sdc1_rclk"; > + bias-pull-down; > + }; > + }; > + > + sdc1_state_off: sdc1-off-state { > + clk-pins { > + pins = "sdc1_clk"; > + bias-disable; > + drive-strength = <2>; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + > + rclk-pins { > + pins = "sdc1_rclk"; > + bias-pull-down; > + }; > + }; > + > + sdc2_state_on: sdc2-on-state { > + clk-pins { > + pins = "sdc2_clk"; > + bias-disable; > + drive-strength = <16>; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + sd-cd-pins { > + pins = "gpio88"; > + function = "gpio"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + }; > + > + sdc2_state_off: sdc2-off-state { > + clk-pins { > + pins = "sdc2_clk"; > + bias-disable; > + drive-strength = <2>; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + > + sd-cd-pins { > + pins = "gpio88"; > + function = "gpio"; > + bias-disable; > + drive-strength = <2>; > + }; > + }; > + }; > + > + gcc: clock-controller@1400000 { > + compatible = "qcom,gcc-sm6115"; > + reg = <0x01400000 0x1f0000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; > + clock-names = "bi_tcxo", "sleep_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + usb_1_hsphy: phy@1613000 { > + compatible = "qcom,sm6115-qusb2-phy"; > + reg = <0x01613000 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + nvmem-cells = <&qusb2_hstx_trim>; > + > + status = "disabled"; > + }; > + > + qfprom@1b40000 { > + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; > + reg = <0x01b40000 0x7000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qusb2_hstx_trim: hstx-trim@25b { > + reg = <0x25b 0x1>; > + bits = <1 4>; > + }; > + }; > + > + spmi_bus: spmi@1c40000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x01c40000 0x1100>, > + <0x01e00000 0x2000000>, > + <0x03e00000 0x100000>, > + <0x03f00000 0xa0000>, > + <0x01c0a000 0x26000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > + interrupt-names = "periph_irq"; > + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; > + qcom,ee = <0>; > + qcom,channel = <0>; > + #address-cells = <2>; > + #size-cells = <0>; > + interrupt-controller; > + #interrupt-cells = <4>; > + }; > + > + rpm_msg_ram: sram@45f0000 { > + compatible = "qcom,rpm-msg-ram"; > + reg = <0x045f0000 0x7000>; > + }; > + > + sdhc_1: mmc@4744000 { > + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; > + reg-names = "hc", "cqhci", "ice"; > + > + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > + <&xo_board>, > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > + clock-names = "iface", "core", "xo", "ice"; > + > + pinctrl-0 = <&sdc1_state_on>; > + pinctrl-1 = <&sdc1_state_off>; > + pinctrl-names = "default", "sleep"; > + > + bus-width = <8>; > + status = "disabled"; > + }; > + > + sdhc_2: mmc@4784000 { > + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x04784000 0x1000>; > + reg-names = "hc"; > + > + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; > + clock-names = "iface", "core", "xo"; > + > + pinctrl-0 = <&sdc2_state_on>; > + pinctrl-1 = <&sdc2_state_off>; > + pinctrl-names = "default", "sleep"; > + > + power-domains = <&rpmpd SM6115_VDDCX>; > + operating-points-v2 = <&sdhc2_opp_table>; > + iommus = <&apps_smmu 0x00a0 0x0>; > + resets = <&gcc GCC_SDCC2_BCR>; > + > + bus-width = <4>; > + qcom,dll-config = <0x0007642c>; > + qcom,ddr-config = <0x80040868>; > + status = "disabled"; > + > + sdhc2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmpd_opp_low_svs>; > + }; > + > + opp-202000000 { > + opp-hz = /bits/ 64 <202000000>; > + required-opps = <&rpmpd_opp_nom>; > + }; > + }; > + }; > + > + ufs_mem_hc: ufs@4804000 { > + compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&ufs_mem_phy_lanes>; > + phy-names = "ufsphy"; > + lanes-per-direction = <1>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + iommus = <&apps_smmu 0x100 0>; > + > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "ice_core_clk"; > + > + freq-table-hz = <50000000 200000000>, > + <0 0>, > + <0 0>, > + <37500000 150000000>, > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <0 0>; > + > + status = "disabled"; > + }; > + > + ufs_mem_phy: phy@4807000 { > + compatible = "qcom,sm6115-qmp-ufs-phy"; > + reg = <0x04807000 0x1c4>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > + clock-names = "ref", "ref_aux"; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + status = "disabled"; > + > + ufs_mem_phy_lanes: phy@4807400 { > + reg = <0x4807400 0x098>, > + <0x4807600 0x130>, > + <0x4807c00 0x16c>; > + #phy-cells = <0>; > + }; > + }; > + > + usb_1: usb@4ef8800 { > + compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; > + reg = <0x04ef8800 0x400>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; > + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <66666667>; > + > + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "ss_phy_irq"; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + qcom,select-utmi-as-pipe-clk; > + status = "disabled"; > + > + usb_1_dwc3: usb@4e00000 { > + compatible = "snps,dwc3"; > + reg = <0x04e00000 0xcd00>; > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb_1_hsphy>; > + phy-names = "usb2-phy"; > + iommus = <&apps_smmu 0x120 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + snps,has-lpm-erratum; > + snps,hird-threshold = /bits/ 8 <0x10>; > + snps,usb3_lpm_capable; > + maximum-speed = "high-speed"; > + dr_mode = "peripheral"; > + }; > + }; > + > + apps_smmu: iommu@c600000 { > + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; > + reg = <0x0c600000 0x80000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + apcs_glb: mailbox@f111000 { > + compatible = "qcom,sm6115-apcs-hmss-global"; > + reg = <0x0f111000 0x1000>; > + > + #mbox-cells = <1>; > + }; > + > + timer@f120000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0f120000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clock-frequency = <19200000>; > + > + frame@f121000 { > + reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; > + frame-number = <0>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + frame@f123000 { > + reg = <0x0f123000 0x1000>; > + frame-number = <1>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@f124000 { > + reg = <0x0f124000 0x1000>; > + frame-number = <2>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@f125000 { > + reg = <0x0f125000 0x1000>; > + frame-number = <3>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@f126000 { > + reg = <0x0f126000 0x1000>; > + frame-number = <4>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@f127000 { > + reg = <0x0f127000 0x1000>; > + frame-number = <5>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@f128000 { > + reg = <0x0f128000 0x1000>; > + frame-number = <6>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + }; > + > + intc: interrupt-controller@f200000 { > + compatible = "arm,gic-v3"; > + reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupt-parent = <&intc>; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + }; > +}; ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 7/8] arm64: dts: qcom: sm4250: Add soc dtsi [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> ` (5 preceding siblings ...) 2022-10-30 9:42 ` [PATCH v5 6/8] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev @ 2022-10-30 9:42 ` Iskren Chernev 2022-10-31 21:18 ` Konrad Dybcio 2022-10-30 9:42 ` [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev 7 siblings, 1 reply; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, linux-kernel The SM4250 is a downclocked version of the SM6115. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi new file mode 100644 index 000000000000..c5add8f44fc0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> + */ + +#include "sm6115.dtsi" + +&CPU0 { + compatible = "qcom,kryo240"; +}; + +&CPU1 { + compatible = "qcom,kryo240"; +}; + +&CPU2 { + compatible = "qcom,kryo240"; +}; + +&CPU3 { + compatible = "qcom,kryo240"; +}; + +&CPU4 { + compatible = "qcom,kryo240"; +}; + +&CPU5 { + compatible = "qcom,kryo240"; +}; + +&CPU6 { + compatible = "qcom,kryo240"; +}; + +&CPU7 { + compatible = "qcom,kryo240"; +}; -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 7/8] arm64: dts: qcom: sm4250: Add soc dtsi 2022-10-30 9:42 ` [PATCH v5 7/8] arm64: dts: qcom: sm4250: Add " Iskren Chernev @ 2022-10-31 21:18 ` Konrad Dybcio 0 siblings, 0 replies; 22+ messages in thread From: Konrad Dybcio @ 2022-10-31 21:18 UTC (permalink / raw) To: Iskren Chernev, Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Andy Gross, Krzysztof Kozlowski, linux-kernel On 30.10.2022 10:42, Iskren Chernev wrote: > The SM4250 is a downclocked version of the SM6115. > > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi > new file mode 100644 > index 000000000000..c5add8f44fc0 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi > @@ -0,0 +1,38 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> > + */ > + > +#include "sm6115.dtsi" > + > +&CPU0 { > + compatible = "qcom,kryo240"; > +}; > + > +&CPU1 { > + compatible = "qcom,kryo240"; > +}; > + > +&CPU2 { > + compatible = "qcom,kryo240"; > +}; > + > +&CPU3 { > + compatible = "qcom,kryo240"; > +}; > + > +&CPU4 { > + compatible = "qcom,kryo240"; > +}; > + > +&CPU5 { > + compatible = "qcom,kryo240"; > +}; > + > +&CPU6 { > + compatible = "qcom,kryo240"; > +}; > + > +&CPU7 { > + compatible = "qcom,kryo240"; > +}; ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 [not found] <20221030094258.486428-1-iskren.chernev@gmail.com> ` (6 preceding siblings ...) 2022-10-30 9:42 ` [PATCH v5 7/8] arm64: dts: qcom: sm4250: Add " Iskren Chernev @ 2022-10-30 9:42 ` Iskren Chernev 2022-10-31 21:21 ` Konrad Dybcio 2022-11-04 19:17 ` Krzysztof Kozlowski 7 siblings, 2 replies; 22+ messages in thread From: Iskren Chernev @ 2022-10-30 9:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Iskren Chernev, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, Kees Cook, Tony Luck, Guilherme G. Piccoli, linux-kernel, linux-hardening Add initial support for OnePlus Nord N100, based on SM4250. Currently working: - boots - usb - built-in flash storage (UFS) - SD card reader Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..eb2a58b8af5f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts new file mode 100644 index 000000000000..a3f1c7c41fd7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> + */ + +/dts-v1/; + +#include "sm4250.dtsi" + +/ { + model = "OnePlus Nord N100"; + compatible = "oneplus,billie2", "qcom,sm4250"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; + qcom,board-id = <0x1000b 0x00>; + + aliases { + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (1600 * 720 * 4)>; + width = <720>; + height = <1600>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; +}; + +&reserved_memory { + bootloader_log_mem: memory@5fff7000 { + reg = <0x0 0x5fff7000 0x0 0x8000>; + no-map; + }; + + ramoops@cbe00000 { + compatible = "ramoops"; + reg = <0x0 0xcbe00000 0x0 0x400000>; + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + }; + + param_mem: memory@cc200000 { + reg = <0x0 0xcc200000 0x0 0x100000>; + no-map; + }; + + mtp_mem: memory@cc300000 { + reg = <0x00 0xcc300000 0x00 0xb00000>; + no-map; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1456000>; + }; + + vreg_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vddp-ref-clk-supply = <&vreg_l18a>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; -- 2.38.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 2022-10-30 9:42 ` [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev @ 2022-10-31 21:21 ` Konrad Dybcio 2022-11-04 19:17 ` Krzysztof Kozlowski 1 sibling, 0 replies; 22+ messages in thread From: Konrad Dybcio @ 2022-10-31 21:21 UTC (permalink / raw) To: Iskren Chernev, Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Andy Gross, Krzysztof Kozlowski, Kees Cook, Tony Luck, Guilherme G. Piccoli, linux-kernel, linux-hardening On 30.10.2022 10:42, Iskren Chernev wrote: > Add initial support for OnePlus Nord N100, based on SM4250. Currently > working: > - boots > - usb > - built-in flash storage (UFS) > - SD card reader > > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ > 2 files changed, 242 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index b0558d3389e5..eb2a58b8af5f 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb > diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > new file mode 100644 > index 000000000000..a3f1c7c41fd7 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > @@ -0,0 +1,241 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> > + */ > + > +/dts-v1/; > + > +#include "sm4250.dtsi" > + > +/ { > + model = "OnePlus Nord N100"; > + compatible = "oneplus,billie2", "qcom,sm4250"; > + > + /* required for bootloader to select correct board */ > + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; > + qcom,board-id = <0x1000b 0x00>; > + > + aliases { > + }; > + > + chosen { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + stdout-path = "framebuffer0"; > + > + framebuffer0: framebuffer@9d400000 { > + compatible = "simple-framebuffer"; > + reg = <0 0x5c000000 0 (1600 * 720 * 4)>; > + width = <720>; > + height = <1600>; > + stride = <(720 * 4)>; > + format = "a8r8g8b8"; > + }; > + }; > +}; > + > +&reserved_memory { > + bootloader_log_mem: memory@5fff7000 { > + reg = <0x0 0x5fff7000 0x0 0x8000>; > + no-map; > + }; > + > + ramoops@cbe00000 { > + compatible = "ramoops"; > + reg = <0x0 0xcbe00000 0x0 0x400000>; > + record-size = <0x40000>; > + pmsg-size = <0x200000>; > + console-size = <0x40000>; > + ftrace-size = <0x40000>; > + }; > + > + param_mem: memory@cc200000 { > + reg = <0x0 0xcc200000 0x0 0x100000>; > + no-map; > + }; > + > + mtp_mem: memory@cc300000 { > + reg = <0x00 0xcc300000 0x00 0xb00000>; 0x00 -> 0x0 for consistency? Other than that, lgtm Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > + no-map; > + }; > +}; > + > +&rpm_requests { > + regulators-0 { > + compatible = "qcom,rpm-pm6125-regulators"; > + > + vreg_s6a: s6 { > + regulator-min-microvolt = <320000>; > + regulator-max-microvolt = <1456000>; > + }; > + > + vreg_s7a: s7 { > + regulator-min-microvolt = <1280000>; > + regulator-max-microvolt = <2040000>; > + }; > + > + vreg_s8a: s8 { > + regulator-min-microvolt = <1064000>; > + regulator-max-microvolt = <1304000>; > + }; > + > + vreg_l1a: l1 { > + regulator-min-microvolt = <952000>; > + regulator-max-microvolt = <1152000>; > + }; > + > + vreg_l4a: l4 { > + regulator-min-microvolt = <488000>; > + regulator-max-microvolt = <1000000>; > + }; > + > + vreg_l5a: l5 { > + regulator-min-microvolt = <1648000>; > + regulator-max-microvolt = <3056000>; > + }; > + > + vreg_l6a: l6 { > + regulator-min-microvolt = <576000>; > + regulator-max-microvolt = <656000>; > + }; > + > + vreg_l7a: l7 { > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1304000>; > + }; > + > + vreg_l8a: l8 { > + regulator-min-microvolt = <400000>; > + regulator-max-microvolt = <728000>; > + }; > + > + vreg_l9a: l9 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <2000000>; > + }; > + > + vreg_l10a: l10 { > + regulator-min-microvolt = <1704000>; > + regulator-max-microvolt = <1904000>; > + }; > + > + vreg_l11a: l11 { > + regulator-min-microvolt = <1704000>; > + regulator-max-microvolt = <1952000>; > + }; > + > + vreg_l12a: l12 { > + regulator-min-microvolt = <1624000>; > + regulator-max-microvolt = <1984000>; > + }; > + > + vreg_l13a: l13 { > + regulator-min-microvolt = <1504000>; > + regulator-max-microvolt = <1952000>; > + }; > + > + vreg_l14a: l14 { > + regulator-min-microvolt = <1704000>; > + regulator-max-microvolt = <1904000>; > + }; > + > + vreg_l15a: l15 { > + regulator-min-microvolt = <2920000>; > + regulator-max-microvolt = <3232000>; > + }; > + > + vreg_l16a: l16 { > + regulator-min-microvolt = <1704000>; > + regulator-max-microvolt = <1904000>; > + }; > + > + vreg_l17a: l17 { > + regulator-min-microvolt = <1152000>; > + regulator-max-microvolt = <1304000>; > + }; > + > + vreg_l18a: l18 { > + regulator-min-microvolt = <1104000>; > + regulator-max-microvolt = <1304000>; > + }; > + > + vreg_l19a: l19 { > + regulator-min-microvolt = <1624000>; > + regulator-max-microvolt = <3304000>; > + }; > + > + vreg_l20a: l20 { > + regulator-min-microvolt = <1624000>; > + regulator-max-microvolt = <3304000>; > + }; > + > + vreg_l21a: l21 { > + regulator-min-microvolt = <2400000>; > + regulator-max-microvolt = <3544000>; > + }; > + > + vreg_l22a: l22 { > + regulator-min-microvolt = <2952000>; > + regulator-max-microvolt = <3304000>; > + }; > + > + vreg_l23a: l23 { > + regulator-min-microvolt = <3296000>; > + regulator-max-microvolt = <3304000>; > + }; > + > + vreg_l24a: l24 { > + regulator-min-microvolt = <2704000>; > + regulator-max-microvolt = <3544000>; > + }; > + }; > +}; > + > +&sleep_clk { > + clock-frequency = <32764>; > +}; > + > +&sdhc_2 { > + vmmc-supply = <&vreg_l22a>; > + vqmmc-supply = <&vreg_l5a>; > + > + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; > + > + status = "okay"; > +}; > + > +&tlmm { > + gpio-reserved-ranges = <14 4>; > +}; > + > +&ufs_mem_hc { > + vcc-supply = <&vreg_l24a>; > + vcc-max-microamp = <600000>; > + vccq2-supply = <&vreg_l11a>; > + vccq2-max-microamp = <600000>; > + status = "okay"; > +}; > + > +&ufs_mem_phy { > + vdda-phy-supply = <&vreg_l4a>; > + vdda-pll-supply = <&vreg_l12a>; > + vddp-ref-clk-supply = <&vreg_l18a>; > + status = "okay"; > +}; > + > +&usb_1 { > + status = "okay"; > +}; > + > +&usb_1_hsphy { > + vdd-supply = <&vreg_l4a>; > + vdda-pll-supply = <&vreg_l12a>; > + vdda-phy-dpdm-supply = <&vreg_l15a>; > + status = "okay"; > +}; > + > +&xo_board { > + clock-frequency = <19200000>; > +}; ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 2022-10-30 9:42 ` [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev 2022-10-31 21:21 ` Konrad Dybcio @ 2022-11-04 19:17 ` Krzysztof Kozlowski 2022-11-07 9:01 ` Iskren Chernev 1 sibling, 1 reply; 22+ messages in thread From: Krzysztof Kozlowski @ 2022-11-04 19:17 UTC (permalink / raw) To: Iskren Chernev, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, Kees Cook, Tony Luck, Guilherme G. Piccoli, linux-kernel, linux-hardening On 30/10/2022 05:42, Iskren Chernev wrote: > Add initial support for OnePlus Nord N100, based on SM4250. Currently > working: > - boots > - usb > - built-in flash storage (UFS) > - SD card reader > > Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ > 2 files changed, 242 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index b0558d3389e5..eb2a58b8af5f 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb > diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > new file mode 100644 > index 000000000000..a3f1c7c41fd7 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts > @@ -0,0 +1,241 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> > + */ > + > +/dts-v1/; > + > +#include "sm4250.dtsi" > + > +/ { > + model = "OnePlus Nord N100"; > + compatible = "oneplus,billie2", "qcom,sm4250"; > + > + /* required for bootloader to select correct board */ > + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; > + qcom,board-id = <0x1000b 0x00>; These are currently not allowed for SM4250. If there are really needed, please justify it and update Documentation/devicetree/bindings/arm/qcom.yaml. Then also update include/dt-bindings/arm/qcom,ids.h and socinfo driver. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 2022-11-04 19:17 ` Krzysztof Kozlowski @ 2022-11-07 9:01 ` Iskren Chernev 0 siblings, 0 replies; 22+ messages in thread From: Iskren Chernev @ 2022-11-07 9:01 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Rob Herring Cc: phone-devel, ~postmarketos/upstreaming, linux-arm-msm, devicetree, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, Kees Cook, Tony Luck, Guilherme G. Piccoli, linux-kernel, linux-hardening On 11/4/22 21:17, Krzysztof Kozlowski wrote: > On 30/10/2022 05:42, Iskren Chernev wrote: >> Add initial support for OnePlus Nord N100, based on SM4250. Currently >> working: >> - boots >> - usb >> - built-in flash storage (UFS) >> - SD card reader >> >> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ >> 2 files changed, 242 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >> index b0558d3389e5..eb2a58b8af5f 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb >> diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts >> new file mode 100644 >> index 000000000000..a3f1c7c41fd7 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts >> @@ -0,0 +1,241 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) >> +/* >> + * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> >> + */ >> + >> +/dts-v1/; >> + >> +#include "sm4250.dtsi" >> + >> +/ { >> + model = "OnePlus Nord N100"; >> + compatible = "oneplus,billie2", "qcom,sm4250"; >> + >> + /* required for bootloader to select correct board */ >> + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; >> + qcom,board-id = <0x1000b 0x00>; > > These are currently not allowed for SM4250. If there are really needed, > please justify it and update > Documentation/devicetree/bindings/arm/qcom.yaml. Then also update > include/dt-bindings/arm/qcom,ids.h and socinfo driver. I'm having some trouble with testing this ATM. If this is the only patch with remaining complaints, the rest can be merged (because there is other work prepped for 4250/6115 that depends on it), and once billie2 is figured out it could be merged separately. > Best regards, > Krzysztof Regards, Iskren ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2022-12-19 11:28 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <20221030094258.486428-1-iskren.chernev@gmail.com>
2022-10-30 9:42 ` [PATCH v5 1/8] dt-bindings: ufs: qcom: Add sm6115 binding Iskren Chernev
2022-12-15 11:57 ` Bhupesh Sharma
2022-10-30 9:42 ` [PATCH v5 2/8] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Iskren Chernev
2022-10-30 9:42 ` [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 Iskren Chernev
2022-10-31 21:44 ` Rob Herring
2022-11-04 14:45 ` Vinod Koul
2022-10-30 9:42 ` [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 Iskren Chernev
2022-10-31 21:45 ` Rob Herring
2022-12-15 15:12 ` Dmitry Baryshkov
2022-10-30 9:42 ` [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support Iskren Chernev
2022-12-15 15:10 ` Dmitry Baryshkov
2022-12-15 15:14 ` Dmitry Baryshkov
2022-12-19 10:01 ` Iskren Chernev
2022-12-19 11:28 ` Dmitry Baryshkov
2022-10-30 9:42 ` [PATCH v5 6/8] arm64: dts: qcom: sm6115: Add basic soc dtsi Iskren Chernev
2022-10-31 21:17 ` Konrad Dybcio
2022-10-30 9:42 ` [PATCH v5 7/8] arm64: dts: qcom: sm4250: Add " Iskren Chernev
2022-10-31 21:18 ` Konrad Dybcio
2022-10-30 9:42 ` [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Iskren Chernev
2022-10-31 21:21 ` Konrad Dybcio
2022-11-04 19:17 ` Krzysztof Kozlowski
2022-11-07 9:01 ` Iskren Chernev
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