* [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk @ 2022-10-30 14:23 Shazad Hussain 2022-10-31 11:22 ` Brian Masney ` (2 more replies) 0 siblings, 3 replies; 13+ messages in thread From: Shazad Hussain @ 2022-10-30 14:23 UTC (permalink / raw) To: andersson Cc: bmasney, Shazad Hussain, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")' we need to explicitly make cxo as parent to gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> --- drivers/clk/qcom/gcc-sc8280xp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index a18ed88f3b82..72b545121c57 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -5848,6 +5848,8 @@ static struct clk_branch gcc_ufs_ref_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_ref_clkref_clk", + .parent_data = &gcc_parent_data_tcxo, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, -- 2.38.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-10-30 14:23 [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk Shazad Hussain @ 2022-10-31 11:22 ` Brian Masney 2022-11-01 18:23 ` Stephen Boyd 2022-11-03 2:54 ` Bjorn Andersson 2 siblings, 0 replies; 13+ messages in thread From: Brian Masney @ 2022-10-31 11:22 UTC (permalink / raw) To: Shazad Hussain Cc: andersson, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel On Sun, Oct 30, 2022 at 07:53:33PM +0530, Shazad Hussain wrote: > Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref > clock for ufs_mem_phy")' we need to explicitly make cxo as parent to > gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. > > Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> I verified that the QDrive3 still boots normally with this patch. Tested-by: Brian Masney <bmasney@redhat.com> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-10-30 14:23 [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk Shazad Hussain 2022-10-31 11:22 ` Brian Masney @ 2022-11-01 18:23 ` Stephen Boyd 2022-11-02 7:16 ` Johan Hovold 2022-11-03 2:54 ` Bjorn Andersson 2 siblings, 1 reply; 13+ messages in thread From: Stephen Boyd @ 2022-11-01 18:23 UTC (permalink / raw) To: Shazad Hussain, andersson Cc: bmasney, Shazad Hussain, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel Quoting Shazad Hussain (2022-10-30 07:23:33) > Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref So we should have a Fixes tag for this commit? Or really back to the beginning of the driver? > clock for ufs_mem_phy")' we need to explicitly make cxo as parent to > gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-01 18:23 ` Stephen Boyd @ 2022-11-02 7:16 ` Johan Hovold 2022-11-02 7:58 ` Shazad Hussain 0 siblings, 1 reply; 13+ messages in thread From: Johan Hovold @ 2022-11-02 7:16 UTC (permalink / raw) To: Stephen Boyd Cc: Shazad Hussain, andersson, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On Tue, Nov 01, 2022 at 11:23:59AM -0700, Stephen Boyd wrote: > Quoting Shazad Hussain (2022-10-30 07:23:33) > > Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref > > So we should have a Fixes tag for this commit? Or really back to the > beginning of the driver? > > > clock for ufs_mem_phy")' we need to explicitly make cxo as parent to > > gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. The commit message is slightly misleading as this affects the other UFS PHY as well. If CX is indeed a parent of this clock then the issue has been there since the clock driver was added. (And otherwise, the PHY binding may need to be amended instead.) Johan ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-02 7:16 ` Johan Hovold @ 2022-11-02 7:58 ` Shazad Hussain 2022-11-02 8:13 ` Johan Hovold 0 siblings, 1 reply; 13+ messages in thread From: Shazad Hussain @ 2022-11-02 7:58 UTC (permalink / raw) To: Johan Hovold, Stephen Boyd Cc: andersson, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On 11/2/2022 12:46 PM, Johan Hovold wrote: > On Tue, Nov 01, 2022 at 11:23:59AM -0700, Stephen Boyd wrote: >> Quoting Shazad Hussain (2022-10-30 07:23:33) >>> Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref >> >> So we should have a Fixes tag for this commit? Or really back to the >> beginning of the driver? >> >>> clock for ufs_mem_phy")' we need to explicitly make cxo as parent to >>> gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. > > The commit message is slightly misleading as this affects the other UFS > PHY as well. > > If CX is indeed a parent of this clock then the issue has been there > since the clock driver was added. (And otherwise, the PHY binding may > need to be amended instead.) > > Johan CX is not the actual parent of this clk. GCC_UFS_REF_CLKREF_CLK is an external clk to the device, which needs to be voted. If we use the GCC_UFS_REF_CLKREF_CLK as ref clk, we don't have explicit vote for CX from ufs_mem_phy. If no client votes for CX,(very unlikely) then it's won't be ON for ufs_mem_phy as well right ! So to maintain the voting to CX, we make this as parent to ref clk. Shazad ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-02 7:58 ` Shazad Hussain @ 2022-11-02 8:13 ` Johan Hovold 2022-11-02 8:45 ` Shazad Hussain 0 siblings, 1 reply; 13+ messages in thread From: Johan Hovold @ 2022-11-02 8:13 UTC (permalink / raw) To: Shazad Hussain Cc: Stephen Boyd, andersson, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On Wed, Nov 02, 2022 at 01:28:48PM +0530, Shazad Hussain wrote: > On 11/2/2022 12:46 PM, Johan Hovold wrote: > > On Tue, Nov 01, 2022 at 11:23:59AM -0700, Stephen Boyd wrote: > >> Quoting Shazad Hussain (2022-10-30 07:23:33) > >>> Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref > >> > >> So we should have a Fixes tag for this commit? Or really back to the > >> beginning of the driver? > >> > >>> clock for ufs_mem_phy")' we need to explicitly make cxo as parent to > >>> gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. > > > > The commit message is slightly misleading as this affects the other UFS > > PHY as well. > > > > If CX is indeed a parent of this clock then the issue has been there > > since the clock driver was added. (And otherwise, the PHY binding may > > need to be amended instead.) > CX is not the actual parent of this clk. GCC_UFS_REF_CLKREF_CLK is an > external clk to the device, which needs to be voted. If we use the > GCC_UFS_REF_CLKREF_CLK as ref clk, we don't have explicit vote for CX > from ufs_mem_phy. > > If no client votes for CX,(very unlikely) then it's won't be ON for > ufs_mem_phy as well right ! So to maintain the voting to CX, we make > this as parent to ref clk. Right, but if the PHYs really requires CX and it is not an ancestor of the refclk then this should be described by the binding (and not be hidden away in the clock driver). Johan ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-02 8:13 ` Johan Hovold @ 2022-11-02 8:45 ` Shazad Hussain 2022-11-02 9:26 ` Johan Hovold 0 siblings, 1 reply; 13+ messages in thread From: Shazad Hussain @ 2022-11-02 8:45 UTC (permalink / raw) To: Johan Hovold Cc: Stephen Boyd, andersson, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On 11/2/2022 1:43 PM, Johan Hovold wrote: > On Wed, Nov 02, 2022 at 01:28:48PM +0530, Shazad Hussain wrote: >> On 11/2/2022 12:46 PM, Johan Hovold wrote: >>> On Tue, Nov 01, 2022 at 11:23:59AM -0700, Stephen Boyd wrote: >>>> Quoting Shazad Hussain (2022-10-30 07:23:33) >>>>> Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref >>>> >>>> So we should have a Fixes tag for this commit? Or really back to the >>>> beginning of the driver? >>>> >>>>> clock for ufs_mem_phy")' we need to explicitly make cxo as parent to >>>>> gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. >>> >>> The commit message is slightly misleading as this affects the other UFS >>> PHY as well. >>> >>> If CX is indeed a parent of this clock then the issue has been there >>> since the clock driver was added. (And otherwise, the PHY binding may >>> need to be amended instead.) > >> CX is not the actual parent of this clk. GCC_UFS_REF_CLKREF_CLK is an >> external clk to the device, which needs to be voted. If we use the >> GCC_UFS_REF_CLKREF_CLK as ref clk, we don't have explicit vote for CX >> from ufs_mem_phy. >> >> If no client votes for CX,(very unlikely) then it's won't be ON for >> ufs_mem_phy as well right ! So to maintain the voting to CX, we make >> this as parent to ref clk. > > Right, but if the PHYs really requires CX and it is not an ancestor of > the refclk then this should be described by the binding (and not be > hidden away in the clock driver). > > Johan This makes sense, will be posting v2 post for the same. I assume this should use the Fixes tag then ! Shazad ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-02 8:45 ` Shazad Hussain @ 2022-11-02 9:26 ` Johan Hovold 2022-11-03 2:49 ` Bjorn Andersson 0 siblings, 1 reply; 13+ messages in thread From: Johan Hovold @ 2022-11-02 9:26 UTC (permalink / raw) To: Shazad Hussain Cc: Stephen Boyd, andersson, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On Wed, Nov 02, 2022 at 02:15:26PM +0530, Shazad Hussain wrote: > On 11/2/2022 1:43 PM, Johan Hovold wrote: > > Right, but if the PHYs really requires CX and it is not an ancestor of > > the refclk then this should be described by the binding (and not be > > hidden away in the clock driver). > This makes sense, will be posting v2 post for the same. > I assume this should use the Fixes tag then ! Yeah, I guess to you can add a fixes tag for the commits adding support for sc8280xp to the UFS PHY binding and driver. But please do check with the hardware documentation first so we get this right this time. I've already asked Bjorn to see what he can dig out as it is still not clear how the two "card" refclocks (GCC_UFS_CARD_CLKREF_CLK and GCC_UFS_1_CARD_CLKREF_CLK) are supposed to be used. Johan ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-02 9:26 ` Johan Hovold @ 2022-11-03 2:49 ` Bjorn Andersson 2022-11-03 9:06 ` Johan Hovold 0 siblings, 1 reply; 13+ messages in thread From: Bjorn Andersson @ 2022-11-03 2:49 UTC (permalink / raw) To: Johan Hovold, Shazad Hussain Cc: Stephen Boyd, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On Wed, Nov 02, 2022 at 10:26:13AM +0100, Johan Hovold wrote: > On Wed, Nov 02, 2022 at 02:15:26PM +0530, Shazad Hussain wrote: > > On 11/2/2022 1:43 PM, Johan Hovold wrote: > > > > Right, but if the PHYs really requires CX and it is not an ancestor of > > > the refclk then this should be described by the binding (and not be > > > hidden away in the clock driver). > > > This makes sense, will be posting v2 post for the same. > > I assume this should use the Fixes tag then ! > > Yeah, I guess to you can add a fixes tag for the commits adding support > for sc8280xp to the UFS PHY binding and driver. > > But please do check with the hardware documentation first so we get this > right this time. > > I've already asked Bjorn to see what he can dig out as it is still not > clear how the two "card" refclocks (GCC_UFS_CARD_CLKREF_CLK and > GCC_UFS_1_CARD_CLKREF_CLK) are supposed to be used. > We've come full circle and Shazad's patch came from that discussion :) In line with the downstream dts, we have GCC_UFS{,_1}_CARD_CLKREF_CLK providing a reference clock to the two phys. Then GCC_UFS_REF_CLKREF_CLK feeds the UFS refclock pads (both of them), which connect to the memory device(s). In other words, GCC_UFS{,_1}_CARD_CLKREF_CLK should be "ref" in respective phy. GCC_UFS_REF_CLKREF_CLK is the clock to the devices, but as we don't represent the memory device explicitly it seems suitable to use as "ref_clk" in the ufshc nodes - which would then match the special handling of the "link clock" in the UFS driver. All three clocks are sourced off the CXO pad, so I would like this patch to cover at least all of these. And Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") seems to be in order for such patch. @Johan, would you mind writing a dts patch flipping the clocks around and Shazad can update this patch? Regards, Bjorn ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-03 2:49 ` Bjorn Andersson @ 2022-11-03 9:06 ` Johan Hovold 2022-11-03 15:23 ` Bjorn Andersson 0 siblings, 1 reply; 13+ messages in thread From: Johan Hovold @ 2022-11-03 9:06 UTC (permalink / raw) To: Bjorn Andersson Cc: Shazad Hussain, Stephen Boyd, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On Wed, Nov 02, 2022 at 09:49:49PM -0500, Bjorn Andersson wrote: > On Wed, Nov 02, 2022 at 10:26:13AM +0100, Johan Hovold wrote: > > On Wed, Nov 02, 2022 at 02:15:26PM +0530, Shazad Hussain wrote: > > > On 11/2/2022 1:43 PM, Johan Hovold wrote: > > > > > > Right, but if the PHYs really requires CX and it is not an ancestor of > > > > the refclk then this should be described by the binding (and not be > > > > hidden away in the clock driver). > > > > > This makes sense, will be posting v2 post for the same. > > > I assume this should use the Fixes tag then ! > > > > Yeah, I guess to you can add a fixes tag for the commits adding support > > for sc8280xp to the UFS PHY binding and driver. > > > > But please do check with the hardware documentation first so we get this > > right this time. > > > > I've already asked Bjorn to see what he can dig out as it is still not > > clear how the two "card" refclocks (GCC_UFS_CARD_CLKREF_CLK and > > GCC_UFS_1_CARD_CLKREF_CLK) are supposed to be used. > > > > We've come full circle and Shazad's patch came from that discussion :) Ah, good. :) > In line with the downstream dts, we have GCC_UFS{,_1}_CARD_CLKREF_CLK > providing a reference clock to the two phys. Then GCC_UFS_REF_CLKREF_CLK > feeds the UFS refclock pads (both of them), which connect to the memory > device(s). > > In other words, GCC_UFS{,_1}_CARD_CLKREF_CLK should be "ref" in > respective phy. > > GCC_UFS_REF_CLKREF_CLK is the clock to the devices, but as we don't > represent the memory device explicitly it seems suitable to use as > "ref_clk" in the ufshc nodes - which would then match the special > handling of the "link clock" in the UFS driver. Thanks for clearing that up. Using GCC_UFS_REF_CLKREF_CLK as ref_clk for the controller sounds reasonable. I guess the only missing piece is which "card" ref clock is used by which PHY. The ADP dts uses: phy ref clock phy@1d87000 (UFS_PHY) GCC_UFS_CARD_CLKREF_CLK phy@1da7000 (UFS_CARD) GCC_UFS_1_CARD_CLKREF_CLK but that is not what the firmware on ADP and CRD seem to enable. Both the ADP and CRD fw leaves GCC_UFS_1_CARD_CLKREF_CLK enabled, while GCC_UFS_CARD_CLKREF_CLK is only enabled on ADP (which unlike the CRD also uses the UFS_CARD controller). Does the ADP dts have these clocks switched or is the firmware confused? (Also note that experiments suggest that neither refclock appears to has to be explicitly enabled for the controllers to function.) > All three clocks are sourced off the CXO pad, so I would like this patch > to cover at least all of these. And > > Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") > > seems to be in order for such patch. > > > @Johan, would you mind writing a dts patch flipping the clocks around > and Shazad can update this patch? I'll do so, but I'll wait with posting until you can confirm which clkref is which. Johan ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-03 9:06 ` Johan Hovold @ 2022-11-03 15:23 ` Bjorn Andersson 2022-11-04 9:29 ` Johan Hovold 0 siblings, 1 reply; 13+ messages in thread From: Bjorn Andersson @ 2022-11-03 15:23 UTC (permalink / raw) To: Johan Hovold Cc: Shazad Hussain, Stephen Boyd, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On Thu, Nov 03, 2022 at 10:06:20AM +0100, Johan Hovold wrote: > On Wed, Nov 02, 2022 at 09:49:49PM -0500, Bjorn Andersson wrote: > > On Wed, Nov 02, 2022 at 10:26:13AM +0100, Johan Hovold wrote: > > > On Wed, Nov 02, 2022 at 02:15:26PM +0530, Shazad Hussain wrote: > > > > On 11/2/2022 1:43 PM, Johan Hovold wrote: > > > > > > > > Right, but if the PHYs really requires CX and it is not an ancestor of > > > > > the refclk then this should be described by the binding (and not be > > > > > hidden away in the clock driver). > > > > > > > This makes sense, will be posting v2 post for the same. > > > > I assume this should use the Fixes tag then ! > > > > > > Yeah, I guess to you can add a fixes tag for the commits adding support > > > for sc8280xp to the UFS PHY binding and driver. > > > > > > But please do check with the hardware documentation first so we get this > > > right this time. > > > > > > I've already asked Bjorn to see what he can dig out as it is still not > > > clear how the two "card" refclocks (GCC_UFS_CARD_CLKREF_CLK and > > > GCC_UFS_1_CARD_CLKREF_CLK) are supposed to be used. > > > > > > > We've come full circle and Shazad's patch came from that discussion :) > > Ah, good. :) > > > In line with the downstream dts, we have GCC_UFS{,_1}_CARD_CLKREF_CLK > > providing a reference clock to the two phys. Then GCC_UFS_REF_CLKREF_CLK > > feeds the UFS refclock pads (both of them), which connect to the memory > > device(s). > > > > In other words, GCC_UFS{,_1}_CARD_CLKREF_CLK should be "ref" in > > respective phy. > > > > GCC_UFS_REF_CLKREF_CLK is the clock to the devices, but as we don't > > represent the memory device explicitly it seems suitable to use as > > "ref_clk" in the ufshc nodes - which would then match the special > > handling of the "link clock" in the UFS driver. > > Thanks for clearing that up. Using GCC_UFS_REF_CLKREF_CLK as ref_clk for > the controller sounds reasonable. > > I guess the only missing piece is which "card" ref clock is used by > which PHY. > > The ADP dts uses: > > phy ref clock > > phy@1d87000 (UFS_PHY) GCC_UFS_CARD_CLKREF_CLK > phy@1da7000 (UFS_CARD) GCC_UFS_1_CARD_CLKREF_CLK > This matches the documentation. Regards, Bjorn > but that is not what the firmware on ADP and CRD seem to enable. > > Both the ADP and CRD fw leaves GCC_UFS_1_CARD_CLKREF_CLK enabled, while > GCC_UFS_CARD_CLKREF_CLK is only enabled on ADP (which unlike the CRD > also uses the UFS_CARD controller). > > Does the ADP dts have these clocks switched or is the firmware confused? > > (Also note that experiments suggest that neither refclock appears to > has to be explicitly enabled for the controllers to function.) > > > All three clocks are sourced off the CXO pad, so I would like this patch > > to cover at least all of these. And > > > > Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") > > > > seems to be in order for such patch. > > > > > > @Johan, would you mind writing a dts patch flipping the clocks around > > and Shazad can update this patch? > > I'll do so, but I'll wait with posting until you can confirm which > clkref is which. > > Johan ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-11-03 15:23 ` Bjorn Andersson @ 2022-11-04 9:29 ` Johan Hovold 0 siblings, 0 replies; 13+ messages in thread From: Johan Hovold @ 2022-11-04 9:29 UTC (permalink / raw) To: Bjorn Andersson Cc: Shazad Hussain, Stephen Boyd, bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, linux-arm-msm, linux-clk, linux-kernel On Thu, Nov 03, 2022 at 10:23:55AM -0500, Bjorn Andersson wrote: > On Thu, Nov 03, 2022 at 10:06:20AM +0100, Johan Hovold wrote: > > On Wed, Nov 02, 2022 at 09:49:49PM -0500, Bjorn Andersson wrote: > > > In line with the downstream dts, we have GCC_UFS{,_1}_CARD_CLKREF_CLK > > > providing a reference clock to the two phys. Then GCC_UFS_REF_CLKREF_CLK > > > feeds the UFS refclock pads (both of them), which connect to the memory > > > device(s). > > > > > > In other words, GCC_UFS{,_1}_CARD_CLKREF_CLK should be "ref" in > > > respective phy. > > > > > > GCC_UFS_REF_CLKREF_CLK is the clock to the devices, but as we don't > > > represent the memory device explicitly it seems suitable to use as > > > "ref_clk" in the ufshc nodes - which would then match the special > > > handling of the "link clock" in the UFS driver. > > > > Thanks for clearing that up. Using GCC_UFS_REF_CLKREF_CLK as ref_clk for > > the controller sounds reasonable. > > > > I guess the only missing piece is which "card" ref clock is used by > > which PHY. > > > > The ADP dts uses: > > > > phy ref clock > > > > phy@1d87000 (UFS_PHY) GCC_UFS_CARD_CLKREF_CLK > > phy@1da7000 (UFS_CARD) GCC_UFS_1_CARD_CLKREF_CLK > > > > This matches the documentation. Thanks for checking. > > > All three clocks are sourced off the CXO pad, so I would like this patch > > > to cover at least all of these. And > > > > > > Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") > > > > > > seems to be in order for such patch. > > > > > > > > > @Johan, would you mind writing a dts patch flipping the clocks around > > > and Shazad can update this patch? > > > > I'll do so, but I'll wait with posting until you can confirm which > > clkref is which. I've know posted a patch fixing the devicetree here: https://lore.kernel.org/lkml/20221104092045.17410-1-johan+linaro@kernel.org/ Note that we need to get Shazad's clock driver fix in first as the UFS controller driver expects a valid frequency for the device ref clock. Johan ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk 2022-10-30 14:23 [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk Shazad Hussain 2022-10-31 11:22 ` Brian Masney 2022-11-01 18:23 ` Stephen Boyd @ 2022-11-03 2:54 ` Bjorn Andersson 2 siblings, 0 replies; 13+ messages in thread From: Bjorn Andersson @ 2022-11-03 2:54 UTC (permalink / raw) To: Shazad Hussain Cc: bmasney, Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel On Sun, Oct 30, 2022 at 07:53:33PM +0530, Shazad Hussain wrote: > Since 'commit f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref > clock for ufs_mem_phy")' we need to explicitly make cxo as parent to > gcc_ufs_ref_clkref_clk to have an independent vote from ufs_mem_phy. > Prior to that change we relied on both cxo and gcc_ufs_ref_clkref_clk being voted for. So I think the reasoning for this patch should simply be to express the fact that the clkref is fed from CXO. Regards, Bjorn > Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> > --- > drivers/clk/qcom/gcc-sc8280xp.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c > index a18ed88f3b82..72b545121c57 100644 > --- a/drivers/clk/qcom/gcc-sc8280xp.c > +++ b/drivers/clk/qcom/gcc-sc8280xp.c > @@ -5848,6 +5848,8 @@ static struct clk_branch gcc_ufs_ref_clkref_clk = { > .enable_mask = BIT(0), > .hw.init = &(const struct clk_init_data) { > .name = "gcc_ufs_ref_clkref_clk", > + .parent_data = &gcc_parent_data_tcxo, > + .num_parents = 1, > .ops = &clk_branch2_ops, > }, > }, > -- > 2.38.0 > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-11-04 9:30 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-10-30 14:23 [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk Shazad Hussain 2022-10-31 11:22 ` Brian Masney 2022-11-01 18:23 ` Stephen Boyd 2022-11-02 7:16 ` Johan Hovold 2022-11-02 7:58 ` Shazad Hussain 2022-11-02 8:13 ` Johan Hovold 2022-11-02 8:45 ` Shazad Hussain 2022-11-02 9:26 ` Johan Hovold 2022-11-03 2:49 ` Bjorn Andersson 2022-11-03 9:06 ` Johan Hovold 2022-11-03 15:23 ` Bjorn Andersson 2022-11-04 9:29 ` Johan Hovold 2022-11-03 2:54 ` Bjorn Andersson
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