From: Kim Phillips <kim.phillips@amd.com>
To: <x86@kernel.org>
Cc: Kim Phillips <kim.phillips@amd.com>,
Babu Moger <Babu.Moger@amd.com>, Borislav Petkov <bp@alien8.de>,
Borislav Petkov <bp@suse.de>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Joao Martins <joao.m.martins@oracle.com>,
Jonathan Corbet <corbet@lwn.net>,
"Konrad Rzeszutek Wilk" <konrad.wilk@oracle.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
David Woodhouse <dwmw@amazon.co.uk>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Juergen Gross <jgross@suse.com>,
Peter Zijlstra <peterz@infradead.org>,
Tony Luck <tony.luck@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Alexey Kardashevskiy <aik@amd.com>, <kvm@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v4 2/7] x86/cpu: Define a scattered Null Selector Clears Base feature bit
Date: Wed, 30 Nov 2022 19:49:58 -0600 [thread overview]
Message-ID: <20221201015003.295769-3-kim.phillips@amd.com> (raw)
In-Reply-To: <20221201015003.295769-1-kim.phillips@amd.com>
It's a part of the CPUID 0x80000021 leaf, and this allows us to
group this and other CPUID 0x80000021 EAX feature bits to being
propagated via kvm_set_cpu_caps() instead of open-coding them in
__do_cpuid_func().
Also use the feature bit definition in check_null_seg_clears_base()
instead of open-coding it.
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/common.c | 3 +--
arch/x86/kernel/cpu/scattered.c | 1 +
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index b16fdcedc2b5..5ddde18c1ae8 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -308,6 +308,7 @@
#define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
#define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
#define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */
+#define X86_FEATURE_NULL_SEL_CLR_BASE (11*32+22) /* "" AMD Null Selector Clears Base */
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 73cc546e024d..8d28cd7c9072 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1683,8 +1683,7 @@ void check_null_seg_clears_base(struct cpuinfo_x86 *c)
return;
/* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */
- if (c->extended_cpuid_level >= 0x80000021 &&
- cpuid_eax(0x80000021) & BIT(6))
+ if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
return;
/*
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 079e253e1049..d0734cc19d37 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -46,6 +46,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
{ X86_FEATURE_NO_NESTED_DATA_BP,CPUID_EAX, 0, 0x80000021, 0 },
+ { X86_FEATURE_NULL_SEL_CLR_BASE,CPUID_EAX, 6, 0x80000021, 0 },
{ X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
{ X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
{ 0, 0, 0, 0, 0 }
--
2.34.1
next prev parent reply other threads:[~2022-12-01 1:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 1:49 [PATCH v4 0/7] x86/cpu, kvm: Support AMD Automatic IBRS Kim Phillips
2022-12-01 1:49 ` [PATCH v4 1/7] x86/cpu: Define a scattered No Nested Data Breakpoints feature bit Kim Phillips
2022-12-05 10:23 ` Borislav Petkov
2022-12-05 17:32 ` Kim Phillips
2022-12-05 20:20 ` Borislav Petkov
2022-12-05 22:05 ` Kim Phillips
2022-12-01 1:49 ` Kim Phillips [this message]
2022-12-01 1:49 ` [PATCH v4 3/7] x86/cpu: Make X86_FEATURE_LFENCE_RDTSC a scattered " Kim Phillips
2022-12-01 1:50 ` [PATCH v4 4/7] x86/cpu, kvm: Move CPUID 0x80000021 EAX feature bits propagation to kvm_set_cpu_caps() Kim Phillips
2022-12-01 1:50 ` [PATCH v4 5/7] x86/cpu: Define a scattered AMD Automatic IBRS feature bit Kim Phillips
2022-12-01 1:50 ` [PATCH v4 6/7] x86/cpu: Support AMD Automatic IBRS Kim Phillips
2022-12-02 16:31 ` Pawan Gupta
2022-12-02 17:40 ` Dave Hansen
2022-12-01 1:50 ` [PATCH v4 7/7] x86/cpu, kvm: Propagate the AMD Automatic IBRS feature to the guest Kim Phillips
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