From: Kim Phillips <kim.phillips@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org, Babu Moger <Babu.Moger@amd.com>,
Borislav Petkov <bp@suse.de>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Joao Martins <joao.m.martins@oracle.com>,
Jonathan Corbet <corbet@lwn.net>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
David Woodhouse <dwmw@amazon.co.uk>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Juergen Gross <jgross@suse.com>,
Peter Zijlstra <peterz@infradead.org>,
Tony Luck <tony.luck@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Alexey Kardashevskiy <aik@amd.com>,
kvm@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/7] x86/cpu: Define a scattered No Nested Data Breakpoints feature bit
Date: Mon, 5 Dec 2022 11:32:01 -0600 [thread overview]
Message-ID: <53393726-5a8a-1a13-c620-32c65872278c@amd.com> (raw)
In-Reply-To: <Y43GpD9fgnOGNEcu@zn.tnic>
On 12/5/22 4:23 AM, Borislav Petkov wrote:
> On Wed, Nov 30, 2022 at 07:49:57PM -0600, Kim Phillips wrote:
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -307,6 +307,7 @@
>> #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
>> #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
>> #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
>> +#define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */
>
> Right, what is the use of this bit in a KVM guest? Running perf tool in
> a guest would use that bit how?
This is starting to get off-topic. Propagating that bit to
the guest was originally added by:
commit 58b3d12c0a860cda34ed9d2378078ea5134e6812
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: Thu Oct 28 13:26:38 2021 -0400
KVM: x86: add support for CPUID leaf 0x80000021
In the future, it will be used by:
https://lore.kernel.org/lkml/20221201021948.9259-1-aik@amd.com/
to allow hardware swapping of debug registers.
If it can't be used in the nested VM case, I can remove the
guest propagation code for it from PATCH 4/7 with a Fixes: for
the above commit, but this 1/7 PATCH will remain.
Thanks,
Kim
next prev parent reply other threads:[~2022-12-05 17:32 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 1:49 [PATCH v4 0/7] x86/cpu, kvm: Support AMD Automatic IBRS Kim Phillips
2022-12-01 1:49 ` [PATCH v4 1/7] x86/cpu: Define a scattered No Nested Data Breakpoints feature bit Kim Phillips
2022-12-05 10:23 ` Borislav Petkov
2022-12-05 17:32 ` Kim Phillips [this message]
2022-12-05 20:20 ` Borislav Petkov
2022-12-05 22:05 ` Kim Phillips
2022-12-01 1:49 ` [PATCH v4 2/7] x86/cpu: Define a scattered Null Selector Clears Base " Kim Phillips
2022-12-01 1:49 ` [PATCH v4 3/7] x86/cpu: Make X86_FEATURE_LFENCE_RDTSC a scattered " Kim Phillips
2022-12-01 1:50 ` [PATCH v4 4/7] x86/cpu, kvm: Move CPUID 0x80000021 EAX feature bits propagation to kvm_set_cpu_caps() Kim Phillips
2022-12-01 1:50 ` [PATCH v4 5/7] x86/cpu: Define a scattered AMD Automatic IBRS feature bit Kim Phillips
2022-12-01 1:50 ` [PATCH v4 6/7] x86/cpu: Support AMD Automatic IBRS Kim Phillips
2022-12-02 16:31 ` Pawan Gupta
2022-12-02 17:40 ` Dave Hansen
2022-12-01 1:50 ` [PATCH v4 7/7] x86/cpu, kvm: Propagate the AMD Automatic IBRS feature to the guest Kim Phillips
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