* [PATCH v2 01/14] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 02/14] ARM: dts: aspeed: yosemite4: Enable adc15 Delphine CC Chiu
` (12 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise Yosemite 4 devicetree for devices behind i2c-mux
- Add gpio and eeprom behind i2c-mux
- Remove redundant idle-state setting for i2c-mux
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 381 ++++++++++++++++--
1 file changed, 347 insertions(+), 34 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 64075cc41d92..a5b4585e81e6 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -17,6 +17,25 @@ aliases {
serial6 = &uart7;
serial7 = &uart8;
serial8 = &uart9;
+
+ i2c16 = &imux16;
+ i2c17 = &imux17;
+ i2c18 = &imux18;
+ i2c19 = &imux19;
+ i2c20 = &imux20;
+ i2c21 = &imux21;
+ i2c22 = &imux22;
+ i2c23 = &imux23;
+ i2c24 = &imux24;
+ i2c25 = &imux25;
+ i2c26 = &imux26;
+ i2c27 = &imux27;
+ i2c28 = &imux28;
+ i2c29 = &imux29;
+ i2c30 = &imux30;
+ i2c31 = &imux31;
+ i2c32 = &imux32;
+ i2c33 = &imux33;
};
chosen {
@@ -259,9 +278,109 @@ &i2c8 {
bus-frequency = <400000>;
i2c-mux@70 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x70>;
+
+ imux16: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux17: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux18: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux19: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
};
};
@@ -270,15 +389,174 @@ &i2c9 {
bus-frequency = <400000>;
i2c-mux@71 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x71>;
+
+ imux20: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux21: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux22: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux23: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
};
};
&i2c10 {
status = "okay";
bus-frequency = <400000>;
+ i2c-mux@74 {
+ compatible = "nxp,pca9544";
+ i2c-mux-idle-disconnect;
+ reg = <0x74>;
+
+ imux28: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "","","","",
+ "NIC0_MAIN_PWR_EN","NIC1_MAIN_PWR_EN",
+ "NIC2_MAIN_PWR_EN","NIC3_MAIN_PWR_EN",
+ "","","","","","","","",
+ "","","","","","","","",
+ "","","","","","","","";
+ };
+ };
+
+ imux29: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
&i2c11 {
@@ -433,16 +711,14 @@ eeprom@51 {
reg = <0x51>;
};
- i2c-mux@71 {
- compatible = "nxp,pca9846";
+ i2c-mux@74 {
+ compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
-
- idle-state = <0>;
i2c-mux-idle-disconnect;
- reg = <0x71>;
+ reg = <0x74>;
- i2c@0 {
+ imux30: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -450,26 +726,26 @@ i2c@0 {
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
pwm@20{
- compatible = "max31790";
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
- pwm@23{
- compatible = "max31790";
- reg = <0x23>;
- #address-cells = <1>;
- #size-cells = <0>;
+ pwm@2f{
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
+ reg = <0x2f>;
};
adc@33 {
@@ -492,34 +768,34 @@ gpio@61 {
};
};
- i2c@1 {
+ imux31: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <1>;
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
pwm@20{
- compatible = "max31790";
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
- pwm@23{
- compatible = "max31790";
- reg = <0x23>;
- #address-cells = <1>;
- #size-cells = <0>;
+ pwm@2f{
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
+ reg = <0x2f>;
};
adc@33 {
@@ -547,12 +823,10 @@ i2c-mux@73 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
-
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x73>;
- i2c@0 {
+ imux32: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -563,10 +837,10 @@ adc@35 {
};
};
- i2c@1 {
+ imux33: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <1>;
adc@35 {
compatible = "maxim,max11617";
@@ -589,9 +863,48 @@ mctp@10 {
i2c-mux@72 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x72>;
+
+ imux24: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux25: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux26: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux27: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 02/14] ARM: dts: aspeed: yosemite4: Enable adc15
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 01/14] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 03/14] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting Delphine CC Chiu
` (11 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Enable Yosemite 4 adc15 config
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index a5b4585e81e6..c32736fbaf70 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -51,7 +51,7 @@ iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
- <&adc1 0>, <&adc1 1>;
+ <&adc1 0>, <&adc1 1>, <&adc1 7>;
};
};
@@ -920,10 +920,10 @@ &pinctrl_adc4_default &pinctrl_adc5_default
&adc1 {
ref_voltage = <2500>;
status = "okay";
- pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
+ pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+ &pinctrl_adc15_default>;
};
-
&ehci0 {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 03/14] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 01/14] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 02/14] ARM: dts: aspeed: yosemite4: Enable adc15 Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 04/14] ARM: dts: aspeed: yosemite4: Enable watchdog2 Delphine CC Chiu
` (10 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
enable spi-gpio setting for spi flash
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index c32736fbaf70..0449a7e36ff6 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -53,6 +53,24 @@ iio-hwmon {
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 0>, <&adc1 1>, <&adc1 7>;
};
+
+ spi_gpio: spi-gpio {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
+ gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
+
+ tpmdev@0 {
+ compatible = "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
};
&uart1 {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 04/14] ARM: dts: aspeed: yosemite4: Enable watchdog2
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (2 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 03/14] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 05/14] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Delphine CC Chiu
` (9 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
enable watchdog2 setting
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 0449a7e36ff6..0e9095c83a59 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -120,6 +120,13 @@ &wdt1 {
aspeed,ext-pulse-duration = <256>;
};
+&wdt2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst2_default>;
+ aspeed,reset-type = "system";
+};
+
&mac2 {
status = "okay";
pinctrl-names = "default";
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 05/14] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (3 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 04/14] ARM: dts: aspeed: yosemite4: Enable watchdog2 Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 06/14] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change Delphine CC Chiu
` (8 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise quad mode to dual mode to avoid WP pin influnece the SPI
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 0e9095c83a59..7fe80ad271aa 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -149,15 +149,17 @@ flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
- spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-64.dtsi"
+#include "openbmc-flash-layout-128.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
- spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 06/14] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (4 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 05/14] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 07/14] ARM: dts: aspeed: yosemite4: Add gpio pca9506 Delphine CC Chiu
` (7 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise power sensor adm1281 for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 ++++++++++++-------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 7fe80ad271aa..7f0134fcee57 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -176,8 +176,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -193,8 +194,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -210,8 +212,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -227,8 +230,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -244,8 +248,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -261,8 +266,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -278,8 +284,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -295,8 +302,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 07/14] ARM: dts: aspeed: yosemite4: Add gpio pca9506
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (5 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 06/14] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 08/14] ARM: dts: aspeed: yosemite4: Revise i2c11 and i2c12 schematic change Delphine CC Chiu
` (6 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Add gpio pca9506 I/O expander for yv4 use
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 251 ++++++++++++++++++
1 file changed, 251 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 7f0134fcee57..da413325ce30 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -175,6 +175,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -193,6 +221,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -211,6 +267,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -229,6 +313,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -247,6 +359,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -265,6 +405,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -283,6 +451,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -301,6 +497,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -683,6 +907,33 @@ rtc@6f {
&i2c13 {
status = "okay";
bus-frequency = <400000>;
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&i2c14 {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 08/14] ARM: dts: aspeed: yosemite4: Revise i2c11 and i2c12 schematic change
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (6 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 07/14] ARM: dts: aspeed: yosemite4: Add gpio pca9506 Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 8:04 ` Krzysztof Kozlowski
2023-12-11 2:49 ` [PATCH v2 09/14] ARM: dts: aspeed: yosemite4: Revise i2c14 and i2c15 " Delphine CC Chiu
` (5 subsequent siblings)
13 siblings, 1 reply; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise i2c11 and i2c12 schematic change:
- remove space for adm1272 compatible
- enable interrupt setting for pca9555
- add eeprom for yosemite4 medusa board/BSM use
- remove temperature sensor for yosemite4 schematic change
- add power sensor for power module reading
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 118 ++++++++++++++----
1 file changed, 93 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index da413325ce30..ccb5ecd8d9a6 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -821,41 +821,94 @@ imux29: i2c@1 {
&i2c11 {
status = "okay";
power-sensor@10 {
- compatible = "adi, adm1272";
+ compatible = "adi,adm1272";
reg = <0x10>;
};
power-sensor@12 {
- compatible = "adi, adm1272";
+ compatible = "adi,adm1272";
reg = <0x12>;
};
- gpio@20 {
+ gpio_ext1: pca9555@20 {
compatible = "nxp,pca9555";
- reg = <0x20>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
- };
-
- gpio@21 {
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <94 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "P48V_OCP_GPIO1","P48V_OCP_GPIO2",
+ "P48V_OCP_GPIO3","FAN_BOARD_0_REVISION_0_R",
+ "FAN_BOARD_0_REVISION_1_R","FAN_BOARD_1_REVISION_0_R",
+ "FAN_BOARD_1_REVISION_1_R","RST_MUX_R_N",
+ "RST_LED_CONTROL_FAN_BOARD_0_N","RST_LED_CONTROL_FAN_BOARD_1_N",
+ "RST_IOEXP_FAN_BOARD_0_N","RST_IOEXP_FAN_BOARD_1_N",
+ "PWRGD_LOAD_SWITCH_FAN_BOARD_0_R","PWRGD_LOAD_SWITCH_FAN_BOARD_1_R",
+ "","";
+ };
+
+ gpio_ext2: pca9555@21 {
compatible = "nxp,pca9555";
- reg = <0x21>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
- };
-
- gpio@22 {
+ reg = <0x21>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <94 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "DELTA_MODULE_TYPE","VSENSE_ERR_VDROP_R",
+ "EN_P48V_AUX_0","EN_P48V_AUX_1",
+ "MEDUSA_BOARD_REV_0","MEDUSA_BOARD_REV_1",
+ "MEDUSA_BOARD_REV_2","MEDUSA_BOARD_TYPE",
+ "HSC_OCP_SLOT_ODD_GPIO1","HSC_OCP_SLOT_ODD_GPIO2",
+ "HSC_OCP_SLOT_ODD_GPIO3","HSC_OCP_SLOT_EVEN_GPIO1",
+ "HSC_OCP_SLOT_EVEN_GPIO2","HSC_OCP_SLOT_EVEN_GPIO3",
+ "ADC_TYPE_0_R","ADC_TYPE_1_R";
+ };
+
+ gpio_ext3: pca9555@22 {
compatible = "nxp,pca9555";
- reg = <0x22>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
- };
-
- gpio@23 {
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <94 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "CARD_TYPE_SLOT1","CARD_TYPE_SLOT2",
+ "CARD_TYPE_SLOT3","CARD_TYPE_SLOT4",
+ "CARD_TYPE_SLOT5","CARD_TYPE_SLOT6",
+ "CARD_TYPE_SLOT7","CARD_TYPE_SLOT8",
+ "OC_P48V_HSC_0_N","FLT_P48V_HSC_0_N",
+ "PWRGD_P12V_AUX_1","OC_P48V_HSC_1_N",
+ "FLT_P48V_HSC_1_N","PWRGD_P12V_AUX_1",
+ "MEDUSA_ADC_EFUSE_TYPE_R","P12V_HSC_TYPE";
+ };
+
+ gpio_ext4: pca9555@23 {
compatible = "nxp,pca9555";
- reg = <0x23>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x23>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <94 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "HSC1_ALERT1_R_N","HSC2_ALERT1_R_N",
+ "HSC3_ALERT1_R_N","HSC4_ALERT1_R_N",
+ "HSC5_ALERT1_R_N","HSC6_ALERT1_R_N",
+ "HSC7_ALERT1_R_N","HSC8_ALERT1_R_N",
+ "HSC1_ALERT2_R_N","HSC2_ALERT2_R_N",
+ "HSC3_ALERT2_R_N","HSC4_ALERT2_R_N",
+ "HSC5_ALERT2_R_N","HSC6_ALERT2_R_N",
+ "HSC7_ALERT2_R_N","HSC8_ALERT2_R_N";
+ };
+
+ power-sensor@40 {
+ compatible = "mps,mp5023";
+ reg = <0x40>;
};
temperature-sensor@48 {
@@ -868,19 +921,29 @@ temperature-sensor@49 {
reg = <0x49>;
};
- temperature-sensor@4a {
- compatible = "ti,tmp75";
- reg = <0x4a>;
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
};
- temperature-sensor@4b {
- compatible = "ti,tmp75";
- reg = <0x4b>;
+ power-sensor@62 {
+ compatible = "pmbus";
+ reg = <0x62>;
};
- eeprom@54 {
- compatible = "atmel,24c256";
- reg = <0x54>;
+ power-sensor@64 {
+ compatible = "pmbus";
+ reg = <0x64>;
+ };
+
+ power-sensor@65 {
+ compatible = "pmbus";
+ reg = <0x65>;
+ };
+
+ power-sensor@68 {
+ compatible = "pmbus";
+ reg = <0x68>;
};
};
@@ -898,6 +961,11 @@ eeprom@50 {
reg = <0x50>;
};
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
rtc@6f {
compatible = "nuvoton,nct3018y";
reg = <0x6f>;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 08/14] ARM: dts: aspeed: yosemite4: Revise i2c11 and i2c12 schematic change
2023-12-11 2:49 ` [PATCH v2 08/14] ARM: dts: aspeed: yosemite4: Revise i2c11 and i2c12 schematic change Delphine CC Chiu
@ 2023-12-11 8:04 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-11 8:04 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On 11/12/2023 03:49, Delphine CC Chiu wrote:
> Revise i2c11 and i2c12 schematic change:
> - remove space for adm1272 compatible
> - enable interrupt setting for pca9555
> - add eeprom for yosemite4 medusa board/BSM use
> - remove temperature sensor for yosemite4 schematic change
> - add power sensor for power module reading
You should split your patch into several, per one logical change.
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> .../aspeed/aspeed-bmc-facebook-yosemite4.dts | 118 ++++++++++++++----
> 1 file changed, 93 insertions(+), 25 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index da413325ce30..ccb5ecd8d9a6 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -821,41 +821,94 @@ imux29: i2c@1 {
> &i2c11 {
> status = "okay";
> power-sensor@10 {
> - compatible = "adi, adm1272";
> + compatible = "adi,adm1272";
> reg = <0x10>;
> };
>
> power-sensor@12 {
> - compatible = "adi, adm1272";
> + compatible = "adi,adm1272";
> reg = <0x12>;
> };
>
> - gpio@20 {
> + gpio_ext1: pca9555@20 {
That's not a correct change. You replace good code with bad.
> compatible = "nxp,pca9555";
> - reg = <0x20>;
> + pinctrl-names = "default";
> gpio-controller;
> #gpio-cells = <2>;
> - };
> -
> - gpio@21 {
> + reg = <0x20>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <94 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "P48V_OCP_GPIO1","P48V_OCP_GPIO2",
> + "P48V_OCP_GPIO3","FAN_BOARD_0_REVISION_0_R",
> + "FAN_BOARD_0_REVISION_1_R","FAN_BOARD_1_REVISION_0_R",
> + "FAN_BOARD_1_REVISION_1_R","RST_MUX_R_N",
> + "RST_LED_CONTROL_FAN_BOARD_0_N","RST_LED_CONTROL_FAN_BOARD_1_N",
> + "RST_IOEXP_FAN_BOARD_0_N","RST_IOEXP_FAN_BOARD_1_N",
> + "PWRGD_LOAD_SWITCH_FAN_BOARD_0_R","PWRGD_LOAD_SWITCH_FAN_BOARD_1_R",
> + "","";
> + };
> +
> + gpio_ext2: pca9555@21 {
Nope
> compatible = "nxp,pca9555";
> - reg = <0x21>;
> + pinctrl-names = "default";
> gpio-controller;
> #gpio-cells = <2>;
> - };
> -
> - gpio@22 {
> + reg = <0x21>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <94 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "DELTA_MODULE_TYPE","VSENSE_ERR_VDROP_R",
> + "EN_P48V_AUX_0","EN_P48V_AUX_1",
> + "MEDUSA_BOARD_REV_0","MEDUSA_BOARD_REV_1",
> + "MEDUSA_BOARD_REV_2","MEDUSA_BOARD_TYPE",
> + "HSC_OCP_SLOT_ODD_GPIO1","HSC_OCP_SLOT_ODD_GPIO2",
> + "HSC_OCP_SLOT_ODD_GPIO3","HSC_OCP_SLOT_EVEN_GPIO1",
> + "HSC_OCP_SLOT_EVEN_GPIO2","HSC_OCP_SLOT_EVEN_GPIO3",
> + "ADC_TYPE_0_R","ADC_TYPE_1_R";
> + };
> +
> + gpio_ext3: pca9555@22 {
Nope
> compatible = "nxp,pca9555";
> - reg = <0x22>;
> + pinctrl-names = "default";
> gpio-controller;
> #gpio-cells = <2>;
> - };
> -
> - gpio@23 {
> + reg = <0x22>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <94 IRQ_TYPE_LEVEL_LOW>;
> + gpio-line-names =
> + "CARD_TYPE_SLOT1","CARD_TYPE_SLOT2",
> + "CARD_TYPE_SLOT3","CARD_TYPE_SLOT4",
> + "CARD_TYPE_SLOT5","CARD_TYPE_SLOT6",
> + "CARD_TYPE_SLOT7","CARD_TYPE_SLOT8",
> + "OC_P48V_HSC_0_N","FLT_P48V_HSC_0_N",
> + "PWRGD_P12V_AUX_1","OC_P48V_HSC_1_N",
> + "FLT_P48V_HSC_1_N","PWRGD_P12V_AUX_1",
> + "MEDUSA_ADC_EFUSE_TYPE_R","P12V_HSC_TYPE";
> + };
> +
> + gpio_ext4: pca9555@23 {
Nope
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 09/14] ARM: dts: aspeed: yosemite4: Revise i2c14 and i2c15 schematic change
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (7 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 08/14] ARM: dts: aspeed: yosemite4: Revise i2c11 and i2c12 schematic change Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 10/14] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Delphine CC Chiu
` (4 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise i2c14 and i2c15 schematic change:
- Revise adc128d818 adc mode for yosemite4 schematic change
- Revise ina233 for yosemite4 schematic change
- Remove idle state setting for yosemite4 NIC connection
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 31 ++++++++++++-------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index ccb5ecd8d9a6..ed2b1200603d 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1010,44 +1010,54 @@ &i2c14 {
adc@1d {
compatible = "ti,adc128d818";
reg = <0x1d>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
- adc@35 {
+ adc@36 {
compatible = "ti,adc128d818";
- reg = <0x35>;
- ti,mode = /bits/ 8 <2>;
+ reg = <0x36>;
+ ti,mode = /bits/ 8 <1>;
};
adc@37 {
compatible = "ti,adc128d818";
reg = <0x37>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
power-sensor@40 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x40>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@41 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x41>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@42 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x42>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@43 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x43>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@44 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x44>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
temperature-sensor@4e {
@@ -1217,7 +1227,6 @@ mctp@10 {
i2c-mux@72 {
compatible = "nxp,pca9544";
- i2c-mux-idle-disconnect;
reg = <0x72>;
imux24: i2c@0 {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 10/14] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (8 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 09/14] ARM: dts: aspeed: yosemite4: Revise i2c14 and i2c15 " Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 8:05 ` Krzysztof Kozlowski
2023-12-11 2:49 ` [PATCH v2 11/14] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config Delphine CC Chiu
` (3 subsequent siblings)
13 siblings, 1 reply; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Initialize bmc gpio state
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 195 ++++++++++++++++++
1 file changed, 195 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index ed2b1200603d..eb3687bfd632 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1271,6 +1271,7 @@ temperature-sensor@1f {
};
};
+
&adc0 {
ref_voltage = <2500>;
status = "okay";
@@ -1298,3 +1299,197 @@ &ehci1 {
&uhci {
status = "okay";
};
+
+&sgpiom0 {
+ status = "okay";
+ ngpios = <128>;
+ bus-frequency = <48000>;
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiu2_default &pinctrl_gpiu3_default
+ &pinctrl_gpiu4_default &pinctrl_gpiu5_default
+ &pinctrl_gpiu6_default>;
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "FLT_HSC_SERVER_SLOT8_N","AC_ON_OFF_BTN_CPLD_SLOT5_N",
+ "PWRGD_SLOT1_STBY","PWRGD_SLOT2_STBY",
+ "PWRGD_SLOT3_STBY","PWRGD_SLOT4_STBY","","",
+ /*C0-C7*/ "PRSNT_NIC3_N","","","","FM_NIC0_WAKE_N",
+ "FM_NIC1_WAKE_N","","RST_PCIE_SLOT2_N",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "PRSNT_NIC1_N","PRSNT_NIC2_N","","RST_PCIE_SLOT1_N",
+ "","","","",
+ /*F0-F7*/ "FM_RESBTN_SLOT1_BMC_N","FM_RESBTN_SLOT2_BMC_N",
+ "FM_RESBTN_SLOT3_BMC_N","FM_RESBTN_SLOT4_BMC_N",
+ "PRSNT_SB_SLOT1_N","PRSNT_SB_SLOT2_N",
+ "PRSNT_SB_SLOT3_N","PRSNT_SB_SLOT4_N",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","ALT_MEDUSA_ADC_N",
+ "ALT_SMB_BMC_CPLD2_N",
+ "INT_SPIDER_ADC_R_N",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","ALT_MEDUSA_P12V_EFUSE_N","",
+ /*M0-M7*/ "EN_NIC0_POWER_BMC_R","EN_NIC1_POWER_BMC_R",
+ "INT_MEDUSA_IOEXP_TEMP_N","FLT_P12V_NIC0_N",
+ "INT_SMB_BMC_SLOT1_4_BMC_N",
+ "AC_ON_OFF_BTN_CPLD_SLOT6_N","","",
+ /*N0-N7*/ "FLT_HSC_SERVER_SLOT1_N","FLT_HSC_SERVER_SLOT2_N",
+ "FLT_HSC_SERVER_SLOT3_N","FLT_HSC_SERVER_SLOT4_N",
+ "FM_BMC_READY_R2","FLT_P12V_STBY_BMC_N","","",
+ /*O0-O7*/ "AC_ON_OFF_BTN_CPLD_SLOT8_N","RST_SMB_NIC1_R_N",
+ "RST_SMB_NIC2_R_N","RST_SMB_NIC3_R_N",
+ "FLT_P3V3_NIC2_N","FLT_P3V3_NIC3_N",
+ "","",
+ /*P0-P7*/ "ALT_SMB_BMC_CPLD1_N","'BTN_BMC_R2_N",
+ "EN_P3V_BAT_SCALED_R","PWRGD_P5V_USB_BMC",
+ "FM_BMC_RTCRST_R","RST_USB_HUB_R_N",
+ "FLAG_P5V_USB_BMC_N","",
+ /*Q0-Q7*/ "AC_ON_OFF_BTN_CPLD_SLOT1_N","AC_ON_OFF_BTN_CPLD_SLOT2_N",
+ "AC_ON_OFF_BTN_CPLD_SLOT3_N","AC_ON_OFF_BTN_CPLD_SLOT4_N",
+ "PRSNT_SB_SLOT5_N","PRSNT_SB_SLOT6_N",
+ "PRSNT_SB_SLOT7_N","PRSNT_SB_SLOT8_N",
+ /*R0-R7*/ "AC_ON_OFF_BTN_CPLD_SLOT7_N","INT_SMB_BMC_SLOT5_8_BMC_N",
+ "FM_PWRBRK_NIC_BMC_R2","RST_PCIE_SLOT4_N",
+ "RST_PCIE_SLOT5_N","RST_PCIE_SLOT6_N",
+ "RST_PCIE_SLOT7_N","RST_PCIE_SLOT8_N",
+ /*S0-S7*/ "FM_NIC2_WAKE_N","FM_NIC3_WAKE_N",
+ "EN_NIC3_POWER_BMC_R","SEL_BMC_JTAG_MUX_R",
+ "","ALT_P12V_AUX_N","FAST_PROCHOT_N",
+ "SPI_WP_DISABLE_STATUS_R_N",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","FLT_P3V3_NIC1_N","FLT_P12V_NIC1_N",
+ "FLT_P12V_NIC2_N","FLT_P12V_NIC3_N",
+ "FLT_P3V3_NIC0_N","",
+ /*V0-V7*/ "FM_RESBTN_SLOT5_BMC_N","FM_RESBTN_SLOT6_BMC_N",
+ "FM_RESBTN_SLOT7_BMC_N","FM_RESBTN_SLOT8_BMC_N",
+ "","","","",
+ /*W0-W7*/ "PRSNT_TPM_BMC_N","PRSNT_OCP_DEBUG_BMC_N","ALT_TEMP_BMC_N","ALT_RTC_BMC_N",
+ "","","","",
+ /*X0-X7*/ "","LT_HSC_SERVER_SLOT6_N","FLT_HSC_SERVER_SLOT7_N","","","",
+ "PWRGD_SLOT5_STBY","PWRGD_SLOT6_STBY",
+ /*Y0-Y7*/ "","","SPI_LOCK_REQ_BMC_N","PWRGD_SLOT7_STBY",
+ "","","EN_NIC2_POWER_BMC_R","",
+ /*Z0-Z7*/ "EN_P5V_USB_CPLD_R","'FLT_HSC_SERVER_SLOT5_N",
+ "PWRGD_SLOT8_STBY","","","","","";
+
+ pin_gpio_b4 {
+ gpios = <ASPEED_GPIO(B, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_b5 {
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_f0 {
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f1 {
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f2 {
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f3 {
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f4 {
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f5 {
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f6 {
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f7 {
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l6 {
+ gpios = <ASPEED_GPIO(L, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l7 {
+ gpios = <ASPEED_GPIO(L, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s0 {
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s1 {
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v0 {
+ gpios = <ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v1 {
+ gpios = <ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v2 {
+ gpios = <ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v3 {
+ gpios = <ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w0 {
+ gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w1 {
+ gpios = <ASPEED_GPIO(W, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w2 {
+ gpios = <ASPEED_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w3 {
+ gpios = <ASPEED_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w4 {
+ gpios = <ASPEED_GPIO(W, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w5 {
+ gpios = <ASPEED_GPIO(W, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w6 {
+ gpios = <ASPEED_GPIO(W, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w7 {
+ gpios = <ASPEED_GPIO(W, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z3 {
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z4 {
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z5 {
+ gpios = <ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 10/14] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
2023-12-11 2:49 ` [PATCH v2 10/14] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Delphine CC Chiu
@ 2023-12-11 8:05 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-11 8:05 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On 11/12/2023 03:49, Delphine CC Chiu wrote:
> Initialize bmc gpio state
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> .../aspeed/aspeed-bmc-facebook-yosemite4.dts | 195 ++++++++++++++++++
> 1 file changed, 195 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index ed2b1200603d..eb3687bfd632 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -1271,6 +1271,7 @@ temperature-sensor@1f {
> };
> };
>
> +
Drop
> &adc0 {
> ref_voltage = <2500>;
> status = "okay";
> @@ -1298,3 +1299,197 @@ &ehci1 {
> &uhci {
> status = "okay";
> };
> +
> +&sgpiom0 {
> + status = "okay";
> + ngpios = <128>;
> + bus-frequency = <48000>;
> +};
> +
> +&gpio0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpiu2_default &pinctrl_gpiu3_default
> + &pinctrl_gpiu4_default &pinctrl_gpiu5_default
> + &pinctrl_gpiu6_default>;
> + gpio-line-names =
> + /*A0-A7*/ "","","","","","","","",
> + /*B0-B7*/ "FLT_HSC_SERVER_SLOT8_N","AC_ON_OFF_BTN_CPLD_SLOT5_N",
> + "PWRGD_SLOT1_STBY","PWRGD_SLOT2_STBY",
> + "PWRGD_SLOT3_STBY","PWRGD_SLOT4_STBY","","",
> + /*C0-C7*/ "PRSNT_NIC3_N","","","","FM_NIC0_WAKE_N",
> + "FM_NIC1_WAKE_N","","RST_PCIE_SLOT2_N",
> + /*D0-D7*/ "","","","","","","","",
> + /*E0-E7*/ "PRSNT_NIC1_N","PRSNT_NIC2_N","","RST_PCIE_SLOT1_N",
> + "","","","",
> + /*F0-F7*/ "FM_RESBTN_SLOT1_BMC_N","FM_RESBTN_SLOT2_BMC_N",
> + "FM_RESBTN_SLOT3_BMC_N","FM_RESBTN_SLOT4_BMC_N",
> + "PRSNT_SB_SLOT1_N","PRSNT_SB_SLOT2_N",
> + "PRSNT_SB_SLOT3_N","PRSNT_SB_SLOT4_N",
> + /*G0-G7*/ "","","","","","","","",
> + /*H0-H7*/ "","","","","","","","",
> + /*I0-I7*/ "","","","","","ALT_MEDUSA_ADC_N",
> + "ALT_SMB_BMC_CPLD2_N",
> + "INT_SPIDER_ADC_R_N",
> + /*J0-J7*/ "","","","","","","","",
> + /*K0-K7*/ "","","","","","","","",
> + /*L0-L7*/ "","","","","","","ALT_MEDUSA_P12V_EFUSE_N","",
> + /*M0-M7*/ "EN_NIC0_POWER_BMC_R","EN_NIC1_POWER_BMC_R",
> + "INT_MEDUSA_IOEXP_TEMP_N","FLT_P12V_NIC0_N",
> + "INT_SMB_BMC_SLOT1_4_BMC_N",
> + "AC_ON_OFF_BTN_CPLD_SLOT6_N","","",
> + /*N0-N7*/ "FLT_HSC_SERVER_SLOT1_N","FLT_HSC_SERVER_SLOT2_N",
> + "FLT_HSC_SERVER_SLOT3_N","FLT_HSC_SERVER_SLOT4_N",
> + "FM_BMC_READY_R2","FLT_P12V_STBY_BMC_N","","",
> + /*O0-O7*/ "AC_ON_OFF_BTN_CPLD_SLOT8_N","RST_SMB_NIC1_R_N",
> + "RST_SMB_NIC2_R_N","RST_SMB_NIC3_R_N",
> + "FLT_P3V3_NIC2_N","FLT_P3V3_NIC3_N",
> + "","",
> + /*P0-P7*/ "ALT_SMB_BMC_CPLD1_N","'BTN_BMC_R2_N",
> + "EN_P3V_BAT_SCALED_R","PWRGD_P5V_USB_BMC",
> + "FM_BMC_RTCRST_R","RST_USB_HUB_R_N",
> + "FLAG_P5V_USB_BMC_N","",
> + /*Q0-Q7*/ "AC_ON_OFF_BTN_CPLD_SLOT1_N","AC_ON_OFF_BTN_CPLD_SLOT2_N",
> + "AC_ON_OFF_BTN_CPLD_SLOT3_N","AC_ON_OFF_BTN_CPLD_SLOT4_N",
> + "PRSNT_SB_SLOT5_N","PRSNT_SB_SLOT6_N",
> + "PRSNT_SB_SLOT7_N","PRSNT_SB_SLOT8_N",
> + /*R0-R7*/ "AC_ON_OFF_BTN_CPLD_SLOT7_N","INT_SMB_BMC_SLOT5_8_BMC_N",
> + "FM_PWRBRK_NIC_BMC_R2","RST_PCIE_SLOT4_N",
> + "RST_PCIE_SLOT5_N","RST_PCIE_SLOT6_N",
> + "RST_PCIE_SLOT7_N","RST_PCIE_SLOT8_N",
> + /*S0-S7*/ "FM_NIC2_WAKE_N","FM_NIC3_WAKE_N",
> + "EN_NIC3_POWER_BMC_R","SEL_BMC_JTAG_MUX_R",
> + "","ALT_P12V_AUX_N","FAST_PROCHOT_N",
> + "SPI_WP_DISABLE_STATUS_R_N",
> + /*T0-T7*/ "","","","","","","","",
> + /*U0-U7*/ "","","FLT_P3V3_NIC1_N","FLT_P12V_NIC1_N",
> + "FLT_P12V_NIC2_N","FLT_P12V_NIC3_N",
> + "FLT_P3V3_NIC0_N","",
> + /*V0-V7*/ "FM_RESBTN_SLOT5_BMC_N","FM_RESBTN_SLOT6_BMC_N",
> + "FM_RESBTN_SLOT7_BMC_N","FM_RESBTN_SLOT8_BMC_N",
> + "","","","",
> + /*W0-W7*/ "PRSNT_TPM_BMC_N","PRSNT_OCP_DEBUG_BMC_N","ALT_TEMP_BMC_N","ALT_RTC_BMC_N",
> + "","","","",
> + /*X0-X7*/ "","LT_HSC_SERVER_SLOT6_N","FLT_HSC_SERVER_SLOT7_N","","","",
> + "PWRGD_SLOT5_STBY","PWRGD_SLOT6_STBY",
> + /*Y0-Y7*/ "","","SPI_LOCK_REQ_BMC_N","PWRGD_SLOT7_STBY",
> + "","","EN_NIC2_POWER_BMC_R","",
> + /*Z0-Z7*/ "EN_P5V_USB_CPLD_R","'FLT_HSC_SERVER_SLOT5_N",
> + "PWRGD_SLOT8_STBY","","","","","";
> +
> + pin_gpio_b4 {
No underscores in node names.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 11/14] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (9 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 10/14] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 12/14] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
` (2 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise fan tach config for max31790 driver change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 48 +++++++++++++++++--
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index eb3687bfd632..073f27f1e35f 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1095,8 +1095,18 @@ adc@1f {
pwm@20{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x20>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
gpio@22{
@@ -1108,8 +1118,18 @@ gpio@22{
pwm@2f{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x2f>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
adc@33 {
@@ -1145,8 +1165,18 @@ adc@1f {
pwm@20{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x20>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
gpio@22{
@@ -1158,8 +1188,18 @@ gpio@22{
pwm@2f{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x2f>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
adc@33 {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 12/14] ARM: dts: aspeed: yosemite4: add mctp config for NIC
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (10 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 11/14] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 8:05 ` Krzysztof Kozlowski
2023-12-11 2:49 ` [PATCH v2 13/14] ARM: dts: aspeed: yosemite4: support mux to cpld Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 14/14] ARM: dts: aspeed: yosemite4: Revise gpio name Delphine CC Chiu
13 siblings, 1 reply; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
add mctp config for NIC
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 073f27f1e35f..c8e3a85b7a11 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1273,40 +1273,64 @@ imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ emc1403@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ emc1403@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ emc1403@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ emc1403@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 12/14] ARM: dts: aspeed: yosemite4: add mctp config for NIC
2023-12-11 2:49 ` [PATCH v2 12/14] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
@ 2023-12-11 8:05 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2023-12-11 8:05 UTC (permalink / raw)
To: Delphine CC Chiu, patrick, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
On 11/12/2023 03:49, Delphine CC Chiu wrote:
> add mctp config for NIC
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
> .../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index 073f27f1e35f..c8e3a85b7a11 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -1273,40 +1273,64 @@ imux24: i2c@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0>;
> + mctp-controller;
> temperature-sensor@1f {
> compatible = "ti,tmp421";
> reg = <0x1f>;
> };
> +
> + emc1403@3c {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "smsc,emc1403";
> + reg = <0x3c>;
> + };
> };
>
> imux25: i2c@1 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <1>;
> + mctp-controller;
> temperature-sensor@1f {
> compatible = "ti,tmp421";
> reg = <0x1f>;
> };
> +
> + emc1403@3c {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
In other places as well.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 13/14] ARM: dts: aspeed: yosemite4: support mux to cpld
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (11 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 12/14] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
2023-12-11 2:49 ` [PATCH v2 14/14] ARM: dts: aspeed: yosemite4: Revise gpio name Delphine CC Chiu
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Mux pca9544 to cpld was added on EVT HW schematic design,
so add dts setting for devices behind mux pca9544 to cpld
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 64 ++++++++++++++-----
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index c8e3a85b7a11..fdc33bffd467 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -36,6 +36,10 @@ aliases {
i2c31 = &imux31;
i2c32 = &imux32;
i2c33 = &imux33;
+ i2c34 = &imux34;
+ i2c35 = &imux35;
+ i2c36 = &imux36;
+ i2c37 = &imux37;
};
chosen {
@@ -951,24 +955,54 @@ &i2c12 {
status = "okay";
bus-frequency = <400000>;
- temperature-sensor@48 {
- compatible = "ti,tmp75";
- reg = <0x48>;
- };
+ i2c-mux@70 {
+ compatible = "nxp,pca9544";
+ i2c-mux-idle-disconnect;
+ reg = <0x70>;
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
+ imux34: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
- eeprom@54 {
- compatible = "atmel,24c64";
- reg = <0x54>;
- };
+ temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
- rtc@6f {
- compatible = "nuvoton,nct3018y";
- reg = <0x6f>;
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
+ rtc@6f {
+ compatible = "nuvoton,nct3018y";
+ reg = <0x6f>;
+ };
+ };
+
+ imux35: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux36: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux37: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 14/14] ARM: dts: aspeed: yosemite4: Revise gpio name
2023-12-11 2:49 [PATCH v2 00/14] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
` (12 preceding siblings ...)
2023-12-11 2:49 ` [PATCH v2 13/14] ARM: dts: aspeed: yosemite4: support mux to cpld Delphine CC Chiu
@ 2023-12-11 2:49 ` Delphine CC Chiu
13 siblings, 0 replies; 18+ messages in thread
From: Delphine CC Chiu @ 2023-12-11 2:49 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
Revise gpio name for EVT schematic changes
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index fdc33bffd467..8c0ee53c8bee 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1414,7 +1414,7 @@ &pinctrl_gpiu4_default &pinctrl_gpiu5_default
/*B0-B7*/ "FLT_HSC_SERVER_SLOT8_N","AC_ON_OFF_BTN_CPLD_SLOT5_N",
"PWRGD_SLOT1_STBY","PWRGD_SLOT2_STBY",
"PWRGD_SLOT3_STBY","PWRGD_SLOT4_STBY","","",
- /*C0-C7*/ "PRSNT_NIC3_N","","","","FM_NIC0_WAKE_N",
+ /*C0-C7*/ "","","","","FM_NIC0_WAKE_N",
"FM_NIC1_WAKE_N","","RST_PCIE_SLOT2_N",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "PRSNT_NIC1_N","PRSNT_NIC2_N","","RST_PCIE_SLOT1_N",
@@ -1432,16 +1432,15 @@ &pinctrl_gpiu4_default &pinctrl_gpiu5_default
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","ALT_MEDUSA_P12V_EFUSE_N","",
/*M0-M7*/ "EN_NIC0_POWER_BMC_R","EN_NIC1_POWER_BMC_R",
- "INT_MEDUSA_IOEXP_TEMP_N","FLT_P12V_NIC0_N",
+ "INT_MEDUSA_IOEXP_TEMP_N","PRSNT_NIC3_N",
"INT_SMB_BMC_SLOT1_4_BMC_N",
"AC_ON_OFF_BTN_CPLD_SLOT6_N","","",
/*N0-N7*/ "FLT_HSC_SERVER_SLOT1_N","FLT_HSC_SERVER_SLOT2_N",
"FLT_HSC_SERVER_SLOT3_N","FLT_HSC_SERVER_SLOT4_N",
- "FM_BMC_READY_R2","FLT_P12V_STBY_BMC_N","","",
+ "FM_BMC_READY_R2","RST_SMB_NIC0_R_N","","",
/*O0-O7*/ "AC_ON_OFF_BTN_CPLD_SLOT8_N","RST_SMB_NIC1_R_N",
"RST_SMB_NIC2_R_N","RST_SMB_NIC3_R_N",
- "FLT_P3V3_NIC2_N","FLT_P3V3_NIC3_N",
- "","",
+ "","","","",
/*P0-P7*/ "ALT_SMB_BMC_CPLD1_N","'BTN_BMC_R2_N",
"EN_P3V_BAT_SCALED_R","PWRGD_P5V_USB_BMC",
"FM_BMC_RTCRST_R","RST_USB_HUB_R_N",
@@ -1459,9 +1458,8 @@ &pinctrl_gpiu4_default &pinctrl_gpiu5_default
"","ALT_P12V_AUX_N","FAST_PROCHOT_N",
"SPI_WP_DISABLE_STATUS_R_N",
/*T0-T7*/ "","","","","","","","",
- /*U0-U7*/ "","","FLT_P3V3_NIC1_N","FLT_P12V_NIC1_N",
- "FLT_P12V_NIC2_N","FLT_P12V_NIC3_N",
- "FLT_P3V3_NIC0_N","",
+ /*U0-U7*/ "","","RST_PCIE_SLOT3_N","",
+ "","PRSNT_NIC0_N","",""
/*V0-V7*/ "FM_RESBTN_SLOT5_BMC_N","FM_RESBTN_SLOT6_BMC_N",
"FM_RESBTN_SLOT7_BMC_N","FM_RESBTN_SLOT8_BMC_N",
"","","","",
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread