From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
To: Borislav Petkov <bp@suse.de>,
"Jason A. Donenfeld" <Jason@zx2c4.com>,
kitsunyan <kitsunyan@airmail.cc>,
"Brown, Len" <len.brown@intel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/msr: do not warn on writes to OC_MAILBOX
Date: Tue, 08 Sep 2020 10:10:17 -0700 [thread overview]
Message-ID: <22617e57e541e460fac09db04fdb370f8e96e8ef.camel@linux.intel.com> (raw)
In-Reply-To: <20200907100647.GB10657@zn.tnic>
On Mon, 2020-09-07 at 12:06 +0200, Borislav Petkov wrote:
> + Srinivas.
> + kitsunyan.
>
> On Mon, Sep 07, 2020 at 11:48:43AM +0200, Jason A. Donenfeld wrote:
> > Popular tools, like intel-undervolt, use MSR 0x150 to control the
> > CPU
> > voltage offset. In fact, evidently the intel_turbo_max_3 driver in-
> > tree
> > also uses this MSR. So, teach the kernel's MSR list about this, so
> > that
> > intel-undervolt and other such tools don't spew warnings to dmesg,
> > while
> > unifying the constant used throughout the kernel.
> >
[...]
> > - if (reg == MSR_IA32_ENERGY_PERF_BIAS)
> > + switch (reg) {
> > + case MSR_IA32_ENERGY_PERF_BIAS:
There is already sysfs interface for it.
> > + case MSR_IA32_OC_MAILBOX:
> > return 0;
> > + }
> >
[...]
> Actually, we added the filtering to catch exactly such misuses and,
> lemme check what is the proper word now... /me checks, aha, adding
> new
> MSRs to the "passlist" is the wrong thing to do.
>
> Srinivas, can you pls convert this in-tree driver to use a proper
> sysfs
> interface for that mailbox MSR and also work with the intel-undervolt
> author - I hope I have the right person CCed from the git repo on
> github
> - to come up with a proper interface so that we can drop this MSR use
> too.
Overclocking is not architectural I/F and is supported by some special
CPU skews. I can't find any public document to specify the commands
which can be used via this OC mailbox. I have to check internally to
see if there is any. To add a proper sysfs interface we have to make
sure that we are not allowing some random commands to hardware and
crash the system.
Thanks,
Srinivas
next prev parent reply other threads:[~2020-09-08 17:10 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 9:48 [PATCH] x86/msr: do not warn on writes to OC_MAILBOX Jason A. Donenfeld
2020-09-07 10:06 ` Borislav Petkov
2020-09-07 10:46 ` Jason A. Donenfeld
2020-09-07 11:11 ` Borislav Petkov
2020-09-07 11:15 ` Jason A. Donenfeld
2020-09-07 11:23 ` Borislav Petkov
2020-09-08 17:10 ` Srinivas Pandruvada [this message]
2020-09-08 17:12 ` Jason A. Donenfeld
2020-09-08 17:25 ` Borislav Petkov
2020-09-08 17:29 ` Jason A. Donenfeld
2020-09-08 17:36 ` Borislav Petkov
2020-09-08 17:42 ` Jason A. Donenfeld
2020-09-08 18:01 ` Borislav Petkov
2020-09-08 19:07 ` Jason A. Donenfeld
2020-09-08 19:18 ` Sultan Alsawaf
2020-09-08 19:30 ` Borislav Petkov
2020-09-08 20:35 ` Andy Lutomirski
2020-09-08 22:32 ` Matthew Garrett
2020-09-09 23:56 ` Andy Lutomirski
2020-09-09 1:02 ` Srinivas Pandruvada
2020-09-10 0:08 ` Andy Lutomirski
2020-10-19 17:15 ` Borislav Petkov
2020-10-20 17:21 ` Srinivas Pandruvada
2020-10-20 17:47 ` Borislav Petkov
2020-10-20 18:40 ` Srinivas Pandruvada
2020-10-20 19:40 ` Dave Hansen
2020-10-21 13:11 ` Srinivas Pandruvada
2020-10-22 19:28 ` Borislav Petkov
2020-10-21 13:24 ` Peter Zijlstra
2020-09-08 17:31 ` Borislav Petkov
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