Re: [PATCH] x86/msr: do not warn on writes to OC_MAILBOX

["Jason A. Donenfeld" <Jason@zx2c4.com>]

Hi Borislav,


On Mon, Sep 7, 2020 at 12:06 PM Borislav Petkov <bp@suse.de> wrote:
>
> + Srinivas.
> + kitsunyan.
>
> On Mon, Sep 07, 2020 at 11:48:43AM +0200, Jason A. Donenfeld wrote:
> > Popular tools, like intel-undervolt, use MSR 0x150 to control the CPU
> > voltage offset. In fact, evidently the intel_turbo_max_3 driver in-tree
> > also uses this MSR. So, teach the kernel's MSR list about this, so that
> > intel-undervolt and other such tools don't spew warnings to dmesg, while
> > unifying the constant used throughout the kernel.
> >
> > Fixes: a7e1f67ed29f ("x86/msr: Filter MSR writes")
> > Cc: Borislav Petkov <bp@suse.de>
> > Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
> > ---
> >  arch/x86/include/asm/msr-index.h         | 2 ++
> >  arch/x86/kernel/msr.c                    | 5 ++++-
> >  drivers/platform/x86/intel_turbo_max_3.c | 6 +++---
> >  3 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> > -     if (reg == MSR_IA32_ENERGY_PERF_BIAS)
> > +     switch (reg) {
> > +     case MSR_IA32_ENERGY_PERF_BIAS:
> > +     case MSR_IA32_OC_MAILBOX:
> >               return 0;
> > +     }
> Actually, we added the filtering to catch exactly such misuses and,

Are you sure that intel-undervolt using OC_MAILBOX from userspace is
actually a "misuse"? Should the kernel or kernel drivers actually be
involved with the task of underclocking? This seems pretty squarely in
the realm of "hobbyists poking and prodding at their CPUs" rather than
something made for a kernel driver, right? Also, what was the
justification for whitelisting MSR_IA32_ENERGY_PERF_BIAS?

Jason