[PATCH v3 00/10] x86/microcode: Early load microcode

[PATCH v3 00/10] x86/microcode: Early load microcode

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

The problem in current microcode loading method is that we load a microcode way,
way too late; ideally we should load it before turning paging on.  This may only
be practical on 32 bits since we can't get to 64-bit mode without paging on,
but we should still do it as early as at all possible.

Similarly, we should load the microcode update as early as possible during AP
bringup and when processors are brought back online after hotplug or S3/S4.

In order to do that, the microcode patch needs to be permanently present in
kernel memory.  Each individual patch is fairly small, so that is OK, but the
entire blob with support for each CPU is too big. Since only CPU's with same
model can be in the same platform, we store microcode with the same model as
BSP. Later on APs can upload microcode from the saved microcodep patches.

Note, however, that Linux users have gotten used to being able to install a
microcode patch in the field without having a reboot; we support that model too.

v3: Change .hex to .bin in 01/10 and 05/10 patches. Fix some compilation
warnings. In x86_32 mode, access global varialbes by __pa_symobl() and fix
static string issue in x86_vendor(). Call load_ucode_ap() in real mode as well.
Add debug info.

v2: Detect vendor before loading microcode. Move some functions from
microcode_intel_early.c to microcode_intel_lib.c. Change some early loading
microcode dependencies in Kconfig. Reword doc.

Fenghua Yu (10):
  Documentation/x86: Early load microcode
  x86/microcode_intel.h: Define functions and macros for early loading
    ucode
  x86/common.c: Make have_cpuid_p() a global function
  x86/microcode_core_early.c: Define interfaces for early loading ucode
  x86/microcode_intel_lib.c: Early update ucode on Intel's CPU
  x86/microcode_intel_early.c: Early update ucode on Intel's CPU
  x86/head_32.S: Early update ucode in 32-bit
  x86/head64.c: Early update ucode in 64-bit
  x86/mm/init.c: Copy ucode from initrd image to memory
  x86/Kconfig: Configurations to enable/disable the feature

 Documentation/x86/early-microcode.txt   |  43 ++
 arch/x86/Kconfig                        |  18 +
 arch/x86/include/asm/microcode.h        |  11 +
 arch/x86/include/asm/microcode_intel.h  |  82 ++++
 arch/x86/include/asm/processor.h        |   8 +
 arch/x86/kernel/Makefile                |   3 +
 arch/x86/kernel/cpu/common.c            |  17 +-
 arch/x86/kernel/head64.c                |   6 +
 arch/x86/kernel/head_32.S               |  12 +
 arch/x86/kernel/microcode_core.c        |   7 +-
 arch/x86/kernel/microcode_core_early.c  |  77 ++++
 arch/x86/kernel/microcode_intel.c       | 198 ++------
 arch/x86/kernel/microcode_intel_early.c | 775 ++++++++++++++++++++++++++++++++
 arch/x86/kernel/microcode_intel_lib.c   | 174 +++++++
 arch/x86/mm/init.c                      |  10 +
 15 files changed, 1264 insertions(+), 177 deletions(-)
 create mode 100644 Documentation/x86/early-microcode.txt
 create mode 100644 arch/x86/include/asm/microcode_intel.h
 create mode 100644 arch/x86/kernel/microcode_core_early.c
 create mode 100644 arch/x86/kernel/microcode_intel_early.c
 create mode 100644 arch/x86/kernel/microcode_intel_lib.c

-- 
1.8.0.1

[PATCH v3 01/10] Documentation/x86: Early load microcode

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

Documenation for early loading microcode methodology.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 Documentation/x86/early-microcode.txt | 43 +++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/x86/early-microcode.txt

diff --git a/Documentation/x86/early-microcode.txt b/Documentation/x86/early-microcode.txt
new file mode 100644
index 0000000..4aaf0df
--- /dev/null
+++ b/Documentation/x86/early-microcode.txt
@@ -0,0 +1,43 @@
+Early load microcode
+====================
+By Fenghua Yu <fenghua.yu@intel.com>
+
+Kernel can update microcode in early phase of boot time. Loading microcode early
+can fix CPU issues before they are observed during kernel boot time.
+
+Microcode is stored in an initrd file. The microcode is read from the initrd
+file and loaded to CPUs during boot time.
+
+The format of the combined initrd image is microcode in cpio format followed by
+the initrd image (maybe compressed). Kernel parses the combined initrd image
+during boot time. The microcode file in cpio name space is:
+kernel/x86/microcode/GenuineIntel.bin
+
+During BSP boot (before SMP starts), if the kernel finds the microcode file in
+the initrd file, it parses the microcode and saves matching microcode in memory.
+If matching microcode is found, it will be uploaded in BSP and later on in all
+APs.
+
+The cached microcode patch is applied when CPUs resume from a sleep state.
+
+There are two legacy user space interfaces to load microcode, either through
+/dev/cpu/microcode or through /sys/devices/system/cpu/microcode/reload file
+in sysfs.
+
+In addition to these two legacy methods, the early loading method described
+here is the third method with which microcode can be uploaded to a system's
+CPUs.
+
+The following example script shows how to generate a new combined initrd file in
+/boot/initrd-3.5.0.ucode.img with original microcode microcode.bin and
+original initrd image /boot/initrd-3.5.0.img.
+
+mkdir initrd
+cd initrd
+mkdir kernel
+mkdir kernel/x86
+mkdir kernel/x86/microcode
+cp ../microcode.bin kernel/x86/microcode/GenuineIntel.bin
+find .|cpio -oc >../ucode.cpio
+cd ..
+cat ucode.cpio /boot/initrd-3.5.0.img >/boot/initrd-3.5.0.ucode.img
-- 
1.8.0.1

[PATCH v3 02/10] x86/microcode_intel.h: Define functions and macros for early loading ucode

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

Define some functions and macros that will be used in early loading ucode. Some
of them are moved from microcode_intel.c driver in order to be called in early
boot phase before module can be called.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/include/asm/microcode_intel.h |  82 ++++++++++++++
 arch/x86/kernel/Makefile               |   3 +
 arch/x86/kernel/microcode_core.c       |   7 +-
 arch/x86/kernel/microcode_intel.c      | 198 +++++----------------------------
 4 files changed, 119 insertions(+), 171 deletions(-)
 create mode 100644 arch/x86/include/asm/microcode_intel.h

diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h
new file mode 100644
index 0000000..d1d517b
--- /dev/null
+++ b/arch/x86/include/asm/microcode_intel.h
@@ -0,0 +1,82 @@
+#ifndef _ASM_X86_MICROCODE_INTEL_H
+#define _ASM_X86_MICROCODE_INTEL_H
+
+#include <asm/microcode.h>
+
+struct microcode_header_intel {
+	unsigned int            hdrver;
+	unsigned int            rev;
+	unsigned int            date;
+	unsigned int            sig;
+	unsigned int            cksum;
+	unsigned int            ldrver;
+	unsigned int            pf;
+	unsigned int            datasize;
+	unsigned int            totalsize;
+	unsigned int            reserved[3];
+};
+
+struct microcode_intel {
+	struct microcode_header_intel hdr;
+	unsigned int            bits[0];
+};
+
+/* microcode format is extended from prescott processors */
+struct extended_signature {
+	unsigned int            sig;
+	unsigned int            pf;
+	unsigned int            cksum;
+};
+
+struct extended_sigtable {
+	unsigned int            count;
+	unsigned int            cksum;
+	unsigned int            reserved[3];
+	struct extended_signature sigs[0];
+};
+
+#define DEFAULT_UCODE_DATASIZE	(2000)
+#define MC_HEADER_SIZE		(sizeof(struct microcode_header_intel))
+#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
+#define EXT_HEADER_SIZE		(sizeof(struct extended_sigtable))
+#define EXT_SIGNATURE_SIZE	(sizeof(struct extended_signature))
+#define DWSIZE			(sizeof(u32))
+
+#define get_totalsize(mc) \
+	(((struct microcode_intel *)mc)->hdr.totalsize ? \
+	 ((struct microcode_intel *)mc)->hdr.totalsize : \
+	 DEFAULT_UCODE_TOTALSIZE)
+
+#define get_datasize(mc) \
+	(((struct microcode_intel *)mc)->hdr.datasize ? \
+	 ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
+
+#define sigmatch(s1, s2, p1, p2) \
+	(((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))
+
+#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
+
+extern int
+get_matching_microcode(unsigned int csig, int cpf, void *mc, int rev);
+extern int microcode_sanity_check(void *mc, int print_err);
+extern int get_matching_sig(unsigned int csig, int cpf, void *mc, int rev);
+extern int
+update_match_revision(struct microcode_header_intel *mc_header, int rev);
+
+#ifdef CONFIG_MICROCODE_INTEL_EARLY
+extern void __init load_ucode_intel_bsp(char *real_mode_data);
+extern void __cpuinit load_ucode_intel_ap(void);
+extern void show_ucode_info_early(void);
+#else
+static inline __init void load_ucode_intel_bsp(char *real_mode_data) {}
+static inline __cpuinit void load_ucode_intel_ap(void) {}
+static inline void show_ucode_info_early(void) {}
+#endif
+
+#if defined(CONFIG_MICROCODE_INTEL_EARLY) && defined(CONFIG_HOTPLUG_CPU)
+extern int save_mc_for_early(u8 *mc);
+#else
+static inline int save_mc_for_early(u8 *mc) {}
+#endif
+
+#endif /* _ASM_X86_MICROCODE_INTEL_H */
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 34e923a..052abee 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -88,6 +88,9 @@ obj-$(CONFIG_PARAVIRT_CLOCK)	+= pvclock.o
 
 obj-$(CONFIG_PCSPKR_PLATFORM)	+= pcspeaker.o
 
+obj-$(CONFIG_MICROCODE_EARLY)		+= microcode_core_early.o
+obj-$(CONFIG_MICROCODE_INTEL_EARLY)	+= microcode_intel_early.o
+obj-$(CONFIG_MICROCODE_INTEL_LIB)	+= microcode_intel_lib.o
 microcode-y				:= microcode_core.o
 microcode-$(CONFIG_MICROCODE_INTEL)	+= microcode_intel.o
 microcode-$(CONFIG_MICROCODE_AMD)	+= microcode_amd.o
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 3a04b22..22db92b 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -364,10 +364,7 @@ static struct attribute_group mc_attr_group = {
 
 static void microcode_fini_cpu(int cpu)
 {
-	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
-
 	microcode_ops->microcode_fini_cpu(cpu);
-	uci->valid = 0;
 }
 
 static enum ucode_state microcode_resume_cpu(int cpu)
@@ -383,6 +380,10 @@ static enum ucode_state microcode_resume_cpu(int cpu)
 static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw)
 {
 	enum ucode_state ustate;
+	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
+
+	if (uci && uci->valid)
+		return UCODE_OK;
 
 	if (collect_cpu_info(cpu))
 		return UCODE_ERROR;
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 3544aed..5fb2ceb 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -79,7 +79,7 @@
 #include <linux/module.h>
 #include <linux/vmalloc.h>
 
-#include <asm/microcode.h>
+#include <asm/microcode_intel.h>
 #include <asm/processor.h>
 #include <asm/msr.h>
 
@@ -87,59 +87,6 @@ MODULE_DESCRIPTION("Microcode Update Driver");
 MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
 MODULE_LICENSE("GPL");
 
-struct microcode_header_intel {
-	unsigned int            hdrver;
-	unsigned int            rev;
-	unsigned int            date;
-	unsigned int            sig;
-	unsigned int            cksum;
-	unsigned int            ldrver;
-	unsigned int            pf;
-	unsigned int            datasize;
-	unsigned int            totalsize;
-	unsigned int            reserved[3];
-};
-
-struct microcode_intel {
-	struct microcode_header_intel hdr;
-	unsigned int            bits[0];
-};
-
-/* microcode format is extended from prescott processors */
-struct extended_signature {
-	unsigned int            sig;
-	unsigned int            pf;
-	unsigned int            cksum;
-};
-
-struct extended_sigtable {
-	unsigned int            count;
-	unsigned int            cksum;
-	unsigned int            reserved[3];
-	struct extended_signature sigs[0];
-};
-
-#define DEFAULT_UCODE_DATASIZE	(2000)
-#define MC_HEADER_SIZE		(sizeof(struct microcode_header_intel))
-#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
-#define EXT_HEADER_SIZE		(sizeof(struct extended_sigtable))
-#define EXT_SIGNATURE_SIZE	(sizeof(struct extended_signature))
-#define DWSIZE			(sizeof(u32))
-
-#define get_totalsize(mc) \
-	(((struct microcode_intel *)mc)->hdr.totalsize ? \
-	 ((struct microcode_intel *)mc)->hdr.totalsize : \
-	 DEFAULT_UCODE_TOTALSIZE)
-
-#define get_datasize(mc) \
-	(((struct microcode_intel *)mc)->hdr.datasize ? \
-	 ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
-
-#define sigmatch(s1, s2, p1, p2) \
-	(((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))
-
-#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
-
 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 {
 	struct cpuinfo_x86 *c = &cpu_data(cpu_num);
@@ -162,128 +109,25 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 	return 0;
 }
 
-static inline int update_match_cpu(struct cpu_signature *csig, int sig, int pf)
-{
-	return (!sigmatch(sig, csig->sig, pf, csig->pf)) ? 0 : 1;
-}
-
-static inline int
-update_match_revision(struct microcode_header_intel *mc_header, int rev)
-{
-	return (mc_header->rev <= rev) ? 0 : 1;
-}
-
-static int microcode_sanity_check(void *mc)
-{
-	unsigned long total_size, data_size, ext_table_size;
-	struct microcode_header_intel *mc_header = mc;
-	struct extended_sigtable *ext_header = NULL;
-	int sum, orig_sum, ext_sigcount = 0, i;
-	struct extended_signature *ext_sig;
-
-	total_size = get_totalsize(mc_header);
-	data_size = get_datasize(mc_header);
-
-	if (data_size + MC_HEADER_SIZE > total_size) {
-		pr_err("error! Bad data size in microcode data file\n");
-		return -EINVAL;
-	}
-
-	if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
-		pr_err("error! Unknown microcode update format\n");
-		return -EINVAL;
-	}
-	ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
-	if (ext_table_size) {
-		if ((ext_table_size < EXT_HEADER_SIZE)
-		 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
-			pr_err("error! Small exttable size in microcode data file\n");
-			return -EINVAL;
-		}
-		ext_header = mc + MC_HEADER_SIZE + data_size;
-		if (ext_table_size != exttable_size(ext_header)) {
-			pr_err("error! Bad exttable size in microcode data file\n");
-			return -EFAULT;
-		}
-		ext_sigcount = ext_header->count;
-	}
-
-	/* check extended table checksum */
-	if (ext_table_size) {
-		int ext_table_sum = 0;
-		int *ext_tablep = (int *)ext_header;
-
-		i = ext_table_size / DWSIZE;
-		while (i--)
-			ext_table_sum += ext_tablep[i];
-		if (ext_table_sum) {
-			pr_warning("aborting, bad extended signature table checksum\n");
-			return -EINVAL;
-		}
-	}
-
-	/* calculate the checksum */
-	orig_sum = 0;
-	i = (MC_HEADER_SIZE + data_size) / DWSIZE;
-	while (i--)
-		orig_sum += ((int *)mc)[i];
-	if (orig_sum) {
-		pr_err("aborting, bad checksum\n");
-		return -EINVAL;
-	}
-	if (!ext_table_size)
-		return 0;
-	/* check extended signature checksum */
-	for (i = 0; i < ext_sigcount; i++) {
-		ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
-			  EXT_SIGNATURE_SIZE * i;
-		sum = orig_sum
-			- (mc_header->sig + mc_header->pf + mc_header->cksum)
-			+ (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
-		if (sum) {
-			pr_err("aborting, bad checksum\n");
-			return -EINVAL;
-		}
-	}
-	return 0;
-}
-
 /*
  * return 0 - no update found
  * return 1 - found update
  */
-static int
-get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev)
+static int get_matching_mc(struct microcode_intel *mc_intel, int cpu)
 {
-	struct microcode_header_intel *mc_header = mc;
-	struct extended_sigtable *ext_header;
-	unsigned long total_size = get_totalsize(mc_header);
-	int ext_sigcount, i;
-	struct extended_signature *ext_sig;
-
-	if (!update_match_revision(mc_header, rev))
-		return 0;
-
-	if (update_match_cpu(cpu_sig, mc_header->sig, mc_header->pf))
-		return 1;
+	struct cpu_signature cpu_sig;
+	unsigned int csig, cpf, crev;
 
-	/* Look for ext. headers: */
-	if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE)
-		return 0;
+	collect_cpu_info(cpu, &cpu_sig);
 
-	ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE;
-	ext_sigcount = ext_header->count;
-	ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
+	csig = cpu_sig.sig;
+	cpf = cpu_sig.pf;
+	crev = cpu_sig.rev;
 
-	for (i = 0; i < ext_sigcount; i++) {
-		if (update_match_cpu(cpu_sig, ext_sig->sig, ext_sig->pf))
-			return 1;
-		ext_sig++;
-	}
-	return 0;
+	return get_matching_microcode(csig, cpf, mc_intel, crev);
 }
 
-static int apply_microcode(int cpu)
+int apply_microcode(int cpu)
 {
 	struct microcode_intel *mc_intel;
 	struct ucode_cpu_info *uci;
@@ -300,6 +144,14 @@ static int apply_microcode(int cpu)
 	if (mc_intel == NULL)
 		return 0;
 
+	/*
+	 * Microcode on this CPU could be updated earlier. Only apply the
+	 * microcode patch in mc_intel when it is newer than the one on this
+	 * CPU.
+	 */
+	if (get_matching_mc(mc_intel, cpu) == 0)
+		return 0;
+
 	/* write microcode via MSR 0x79 */
 	wrmsr(MSR_IA32_UCODE_WRITE,
 	      (unsigned long) mc_intel->bits,
@@ -338,6 +190,7 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
 	unsigned int leftover = size;
 	enum ucode_state state = UCODE_OK;
 	unsigned int curr_mc_size = 0;
+	unsigned int csig, cpf;
 
 	while (leftover) {
 		struct microcode_header_intel mc_header;
@@ -362,11 +215,13 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
 		}
 
 		if (get_ucode_data(mc, ucode_ptr, mc_size) ||
-		    microcode_sanity_check(mc) < 0) {
+		    microcode_sanity_check(mc, 1) < 0) {
 			break;
 		}
 
-		if (get_matching_microcode(&uci->cpu_sig, mc, new_rev)) {
+		csig = uci->cpu_sig.sig;
+		cpf = uci->cpu_sig.pf;
+		if (get_matching_microcode(csig, cpf, mc, new_rev)) {
 			vfree(new_mc);
 			new_rev = mc_header.rev;
 			new_mc  = mc;
@@ -393,6 +248,13 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
 	vfree(uci->mc);
 	uci->mc = (struct microcode_intel *)new_mc;
 
+	/*
+	 * If early loading microcode is supported, save this mc into
+	 * permanent memory. So it will be loaded early when a CPU is hot added
+	 * or resumes.
+	 */
+	save_mc_for_early(new_mc);
+
 	pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
 		 cpu, new_rev, uci->cpu_sig.rev);
 out:
-- 
1.8.0.1

[PATCH v3 03/10] x86/common.c: Make have_cpuid_p() a global function

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

Remove static declaration in have_cpuid_p() to make it a global function. The
function will be called in early loading microcode.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/include/asm/processor.h |  8 ++++++++
 arch/x86/kernel/cpu/common.c     | 17 +++++++++++------
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 888184b..3d722fd 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -190,6 +190,14 @@ extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 extern void detect_ht(struct cpuinfo_x86 *c);
 
+#ifdef CONFIG_X86_32
+extern int have_cpuid_p(void);
+#else
+static inline int have_cpuid_p(void)
+{
+	return 1;
+}
+#endif
 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 				unsigned int *ecx, unsigned int *edx)
 {
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 9c3ab43..d814772 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -37,6 +37,8 @@
 #include <asm/mce.h>
 #include <asm/msr.h>
 #include <asm/pat.h>
+#include <asm/microcode.h>
+#include <asm/microcode_intel.h>
 
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/uv/uv.h>
@@ -213,7 +215,7 @@ static inline int flag_is_changeable_p(u32 flag)
 }
 
 /* Probe for the CPUID instruction */
-static int __cpuinit have_cpuid_p(void)
+int __cpuinit have_cpuid_p(void)
 {
 	return flag_is_changeable_p(X86_EFLAGS_ID);
 }
@@ -249,11 +251,6 @@ static inline int flag_is_changeable_p(u32 flag)
 {
 	return 1;
 }
-/* Probe for the CPUID instruction */
-static inline int have_cpuid_p(void)
-{
-	return 1;
-}
 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 {
 }
@@ -1223,6 +1220,12 @@ void __cpuinit cpu_init(void)
 	int cpu;
 	int i;
 
+	/*
+	 * Load microcode on this cpu if a valid microcode is available.
+	 * This is early microcode loading procedure.
+	 */
+	load_ucode_ap();
+
 	cpu = stack_smp_processor_id();
 	t = &per_cpu(init_tss, cpu);
 	oist = &per_cpu(orig_ist, cpu);
@@ -1314,6 +1317,8 @@ void __cpuinit cpu_init(void)
 	struct tss_struct *t = &per_cpu(init_tss, cpu);
 	struct thread_struct *thread = &curr->thread;
 
+	show_ucode_info_early();
+
 	if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
 		printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
 		for (;;)
-- 
1.8.0.1

[PATCH v3 04/10] x86/microcode_core_early.c: Define interfaces for early loading ucode

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

Define interfaces load_ucode_bsp() and load_ucode_ap() to load ucode on BSP and
AP in early boot time. These are generic interfaces. Internally they call
vendor specific implementations.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/include/asm/microcode.h       | 11 +++++
 arch/x86/kernel/microcode_core_early.c | 77 ++++++++++++++++++++++++++++++++++
 2 files changed, 88 insertions(+)
 create mode 100644 arch/x86/kernel/microcode_core_early.c

diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 43d921b..91ed643 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -57,4 +57,15 @@ static inline struct microcode_ops * __init init_amd_microcode(void)
 static inline void __exit exit_amd_microcode(void) {}
 #endif
 
+#ifdef CONFIG_MICROCODE_EARLY
+#define MAX_UCODE_COUNT 128
+extern void __init load_ucode_bsp(char *real_mode_data);
+extern __init void load_ucode_ap(void);
+extern int __init save_microcode_in_initrd(void);
+#else
+static inline void __init load_ucode_bsp(char *real_mode_data) {}
+static inline __init void load_ucode_ap(void) {}
+static inline int __init save_microcode_in_initrd(void) {}
+#endif
+
 #endif /* _ASM_X86_MICROCODE_H */
diff --git a/arch/x86/kernel/microcode_core_early.c b/arch/x86/kernel/microcode_core_early.c
new file mode 100644
index 0000000..458cf14
--- /dev/null
+++ b/arch/x86/kernel/microcode_core_early.c
@@ -0,0 +1,77 @@
+/*
+ *	X86 CPU microcode early update for Linux
+ *
+ *	Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
+ *			   H Peter Anvin" <hpa@zytor.com>
+ *
+ *	This driver allows to early upgrade microcode on Intel processors
+ *	belonging to IA-32 family - PentiumPro, Pentium II,
+ *	Pentium III, Xeon, Pentium 4, etc.
+ *
+ *	Reference: Section 9.11 of Volume 3, IA-32 Intel Architecture
+ *	Software Developer's Manual.
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <asm/microcode_intel.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+
+#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
+#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
+#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
+#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
+#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
+#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
+#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
+
+#define CPUID_IS(a, b, c) (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
+
+/*
+ * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
+ * x86_vendor() gets vendor id for BSP.
+ *
+ * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
+ * coding, we still use x86_vendor() to get vendor id for AP.
+ *
+ * x86_vendor() gets vendor information directly through cpuid.
+ */
+static int __cpuinit x86_vendor(void)
+{
+	u32 eax = 0x00000000;
+	u32 ebx, ecx = 0, edx;
+
+	if (!have_cpuid_p())
+		return X86_VENDOR_UNKNOWN;
+
+	native_cpuid(&eax, &ebx, &ecx, &edx);
+
+	if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3))
+		return X86_VENDOR_INTEL;
+
+	if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3))
+		return X86_VENDOR_AMD;
+
+	return X86_VENDOR_UNKNOWN;
+}
+
+void __init load_ucode_bsp(char *real_mode_data)
+{
+	int vendor = x86_vendor();
+
+	if (vendor == X86_VENDOR_INTEL)
+		load_ucode_intel_bsp(real_mode_data);
+}
+
+void __cpuinit load_ucode_ap(void)
+{
+	int vendor = x86_vendor();
+
+	if (vendor == X86_VENDOR_INTEL)
+		load_ucode_intel_ap();
+}
-- 
1.8.0.1

[PATCH v3 05/10] x86/microcode_intel_lib.c: Early update ucode on Intel's CPU

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

Define interfaces microcode_sanity_check() and get_matching_microcode(). They
are called both in early boot time and in microcode Intel driver.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/kernel/microcode_intel_lib.c | 174 ++++++++++++++++++++++++++++++++++
 1 file changed, 174 insertions(+)
 create mode 100644 arch/x86/kernel/microcode_intel_lib.c

diff --git a/arch/x86/kernel/microcode_intel_lib.c b/arch/x86/kernel/microcode_intel_lib.c
new file mode 100644
index 0000000..ce69320
--- /dev/null
+++ b/arch/x86/kernel/microcode_intel_lib.c
@@ -0,0 +1,174 @@
+/*
+ *	Intel CPU Microcode Update Driver for Linux
+ *
+ *	Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
+ *			   H Peter Anvin" <hpa@zytor.com>
+ *
+ *	This driver allows to upgrade microcode on Intel processors
+ *	belonging to IA-32 family - PentiumPro, Pentium II,
+ *	Pentium III, Xeon, Pentium 4, etc.
+ *
+ *	Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
+ *	Software Developer's Manual
+ *	Order Number 253668 or free download from:
+ *
+ *	http://developer.intel.com/Assets/PDF/manual/253668.pdf
+ *
+ *	For more information, go to http://www.urbanmyth.org/microcode
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ *
+ */
+#include <linux/firmware.h>
+#include <linux/uaccess.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/microcode_intel.h>
+#include <asm/processor.h>
+#include <asm/msr.h>
+
+static inline int
+update_match_cpu(unsigned int csig, unsigned int cpf,
+		 unsigned int sig, unsigned int pf)
+{
+	return (!sigmatch(sig, csig, pf, cpf)) ? 0 : 1;
+}
+
+int
+update_match_revision(struct microcode_header_intel *mc_header, int rev)
+{
+	return (mc_header->rev <= rev) ? 0 : 1;
+}
+
+int microcode_sanity_check(void *mc, int print_err)
+{
+	unsigned long total_size, data_size, ext_table_size;
+	struct microcode_header_intel *mc_header = mc;
+	struct extended_sigtable *ext_header = NULL;
+	int sum, orig_sum, ext_sigcount = 0, i;
+	struct extended_signature *ext_sig;
+
+	total_size = get_totalsize(mc_header);
+	data_size = get_datasize(mc_header);
+
+	if (data_size + MC_HEADER_SIZE > total_size) {
+		if (print_err)
+			pr_err("error! Bad data size in microcode data file\n");
+		return -EINVAL;
+	}
+
+	if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
+		if (print_err)
+			pr_err("error! Unknown microcode update format\n");
+		return -EINVAL;
+	}
+	ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
+	if (ext_table_size) {
+		if ((ext_table_size < EXT_HEADER_SIZE)
+		 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
+			if (print_err)
+				pr_err("error! Small exttable size in microcode data file\n");
+			return -EINVAL;
+		}
+		ext_header = mc + MC_HEADER_SIZE + data_size;
+		if (ext_table_size != exttable_size(ext_header)) {
+			if (print_err)
+				pr_err("error! Bad exttable size in microcode data file\n");
+			return -EFAULT;
+		}
+		ext_sigcount = ext_header->count;
+	}
+
+	/* check extended table checksum */
+	if (ext_table_size) {
+		int ext_table_sum = 0;
+		int *ext_tablep = (int *)ext_header;
+
+		i = ext_table_size / DWSIZE;
+		while (i--)
+			ext_table_sum += ext_tablep[i];
+		if (ext_table_sum) {
+			if (print_err)
+				pr_warn("aborting, bad extended signature table checksum\n");
+			return -EINVAL;
+		}
+	}
+
+	/* calculate the checksum */
+	orig_sum = 0;
+	i = (MC_HEADER_SIZE + data_size) / DWSIZE;
+	while (i--)
+		orig_sum += ((int *)mc)[i];
+	if (orig_sum) {
+		if (print_err)
+			pr_err("aborting, bad checksum\n");
+		return -EINVAL;
+	}
+	if (!ext_table_size)
+		return 0;
+	/* check extended signature checksum */
+	for (i = 0; i < ext_sigcount; i++) {
+		ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
+			  EXT_SIGNATURE_SIZE * i;
+		sum = orig_sum
+			- (mc_header->sig + mc_header->pf + mc_header->cksum)
+			+ (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
+		if (sum) {
+			if (print_err)
+				pr_err("aborting, bad checksum\n");
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+EXPORT_SYMBOL_GPL(microcode_sanity_check);
+
+/*
+ * return 0 - no update found
+ * return 1 - found update
+ */
+int get_matching_sig(unsigned int csig, int cpf, void *mc, int rev)
+{
+	struct microcode_header_intel *mc_header = mc;
+	struct extended_sigtable *ext_header;
+	unsigned long total_size = get_totalsize(mc_header);
+	int ext_sigcount, i;
+	struct extended_signature *ext_sig;
+
+	if (update_match_cpu(csig, cpf, mc_header->sig, mc_header->pf))
+		return 1;
+
+	/* Look for ext. headers: */
+	if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE)
+		return 0;
+
+	ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE;
+	ext_sigcount = ext_header->count;
+	ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
+
+	for (i = 0; i < ext_sigcount; i++) {
+		if (update_match_cpu(csig, cpf, ext_sig->sig, ext_sig->pf))
+			return 1;
+		ext_sig++;
+	}
+	return 0;
+}
+
+/*
+ * return 0 - no update found
+ * return 1 - found update
+ */
+int get_matching_microcode(unsigned int csig, int cpf, void *mc, int rev)
+{
+	struct microcode_header_intel *mc_header = mc;
+
+	if (!update_match_revision(mc_header, rev))
+		return 0;
+
+	return get_matching_sig(csig, cpf, mc, rev);
+}
+EXPORT_SYMBOL_GPL(get_matching_microcode);
-- 
1.8.0.1

[PATCH v3 06/10] x86/microcode_intel_early.c: Early update ucode on Intel's CPU

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

Implementation of early update ucode on Intel's CPU.

load_ucode_intel_bsp() scans ucode in initrd image file which is a cpio format
ucode followed by ordinary initrd image file. The binary ucode file is stored
in kernel/x86/microcode/GenuineIntel.bin in the cpio data. All ucode
patches with the same model as BSP are saved in memory. A matching ucode patch
is updated on BSP.

load_ucode_intel_ap() reads saved ucoded patches and updates ucode on AP.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/kernel/microcode_intel_early.c | 775 ++++++++++++++++++++++++++++++++
 1 file changed, 775 insertions(+)
 create mode 100644 arch/x86/kernel/microcode_intel_early.c

diff --git a/arch/x86/kernel/microcode_intel_early.c b/arch/x86/kernel/microcode_intel_early.c
new file mode 100644
index 0000000..6a8e04b
--- /dev/null
+++ b/arch/x86/kernel/microcode_intel_early.c
@@ -0,0 +1,775 @@
+/*
+ *	Intel CPU microcode early update for Linux
+ *
+ *	Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
+ *			   H Peter Anvin" <hpa@zytor.com>
+ *
+ *	This allows to early upgrade microcode on Intel processors
+ *	belonging to IA-32 family - PentiumPro, Pentium II,
+ *	Pentium III, Xeon, Pentium 4, etc.
+ *
+ *	Reference: Section 9.11 of Volume 3, IA-32 Intel Architecture
+ *	Software Developer's Manual.
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/earlycpio.h>
+#include <linux/initrd.h>
+#include <linux/cpu.h>
+#include <asm/msr.h>
+#include <asm/microcode_intel.h>
+#include <asm/processor.h>
+
+unsigned long mc_saved_in_initrd[MAX_UCODE_COUNT];
+struct mc_saved_data {
+	unsigned int mc_saved_count;
+	struct microcode_intel **mc_saved;
+} mc_saved_data;
+
+static enum ucode_state __cpuinit
+generic_load_microcode_early(struct microcode_intel **mc_saved_p,
+			     unsigned int mc_saved_count,
+			     struct ucode_cpu_info *uci)
+{
+	struct microcode_intel *ucode_ptr, *new_mc = NULL;
+	int new_rev = uci->cpu_sig.rev;
+	enum ucode_state state = UCODE_OK;
+	unsigned int mc_size;
+	struct microcode_header_intel *mc_header;
+	unsigned int csig = uci->cpu_sig.sig;
+	unsigned int cpf = uci->cpu_sig.pf;
+	int i;
+
+	for (i = 0; i < mc_saved_count; i++) {
+		ucode_ptr = mc_saved_p[i];
+
+		mc_header = (struct microcode_header_intel *)ucode_ptr;
+		mc_size = get_totalsize(mc_header);
+		if (get_matching_microcode(csig, cpf, ucode_ptr, new_rev)) {
+			new_rev = mc_header->rev;
+			new_mc  = ucode_ptr;
+		}
+	}
+
+	if (!new_mc) {
+		state = UCODE_NFOUND;
+		goto out;
+	}
+
+	uci->mc = (struct microcode_intel *)new_mc;
+out:
+	return state;
+}
+
+static void __cpuinit
+microcode_pointer(struct microcode_intel **mc_saved,
+		  unsigned long *mc_saved_in_initrd,
+		  unsigned long initrd_start, int mc_saved_count)
+{
+	int i;
+
+	for (i = 0; i < mc_saved_count; i++)
+		mc_saved[i] = (struct microcode_intel *)
+			      (mc_saved_in_initrd[i] + initrd_start);
+}
+
+#ifdef CONFIG_X86_32
+static void __cpuinit
+microcode_phys(struct microcode_intel **mc_saved_tmp,
+	       struct mc_saved_data *mc_saved_data)
+{
+	int i;
+	struct microcode_intel ***mc_saved;
+
+	mc_saved = (struct microcode_intel ***)
+		   __pa_symbol(&mc_saved_data->mc_saved);
+	for (i = 0; i < mc_saved_data->mc_saved_count; i++) {
+		struct microcode_intel *p;
+
+		p = *(struct microcode_intel **)
+			__pa(mc_saved_data->mc_saved + i);
+		mc_saved_tmp[i] = (struct microcode_intel *)__pa(p);
+	}
+}
+#endif
+
+static enum ucode_state __cpuinit
+load_microcode(struct mc_saved_data *mc_saved_data,
+	       unsigned long *mc_saved_in_initrd,
+	       unsigned long initrd_start,
+	       struct ucode_cpu_info *uci)
+{
+	struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
+	unsigned int count = mc_saved_data->mc_saved_count;
+
+	if (!mc_saved_data->mc_saved) {
+		microcode_pointer(mc_saved_tmp, mc_saved_in_initrd,
+				  initrd_start, count);
+
+		return generic_load_microcode_early(mc_saved_tmp, count, uci);
+	} else {
+#ifdef CONFIG_X86_32
+		microcode_phys(mc_saved_tmp, mc_saved_data);
+		return generic_load_microcode_early(mc_saved_tmp, count, uci);
+#else
+		return generic_load_microcode_early(mc_saved_data->mc_saved,
+						    count, uci);
+#endif
+	}
+}
+
+static u8 get_x86_family(unsigned long sig)
+{
+	u8 x86;
+
+	x86 = (sig >> 8) & 0xf;
+
+	if (x86 == 0xf)
+		x86 += (sig >> 20) & 0xff;
+
+	return x86;
+}
+
+static u8 get_x86_model(unsigned long sig)
+{
+	u8 x86, x86_model;
+
+	x86 = get_x86_family(sig);
+	x86_model = (sig >> 4) & 0xf;
+
+	if (x86 == 0x6 || x86 == 0xf)
+		x86_model += ((sig >> 16) & 0xf) << 4;
+
+	return x86_model;
+}
+
+/*
+ * Given CPU signature and a microcode patch, this function finds if the
+ * microcode patch has matching family and model with the CPU.
+ */
+static enum ucode_state
+matching_model_microcode(struct microcode_header_intel *mc_header,
+			unsigned long sig)
+{
+	u8 x86, x86_model;
+	u8 x86_ucode, x86_model_ucode;
+	struct extended_sigtable *ext_header;
+	unsigned long total_size = get_totalsize(mc_header);
+	unsigned long data_size = get_datasize(mc_header);
+	int ext_sigcount, i;
+	struct extended_signature *ext_sig;
+
+	x86 = get_x86_family(sig);
+	x86_model = get_x86_model(sig);
+
+	x86_ucode = get_x86_family(mc_header->sig);
+	x86_model_ucode = get_x86_model(mc_header->sig);
+
+	if (x86 == x86_ucode && x86_model == x86_model_ucode)
+		return UCODE_OK;
+
+	/* Look for ext. headers: */
+	if (total_size <= data_size + MC_HEADER_SIZE)
+		return UCODE_NFOUND;
+
+	ext_header = (struct extended_sigtable *)
+		     mc_header + data_size + MC_HEADER_SIZE;
+	ext_sigcount = ext_header->count;
+	ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
+
+	for (i = 0; i < ext_sigcount; i++) {
+		x86_ucode = get_x86_family(ext_sig->sig);
+		x86_model_ucode = get_x86_model(ext_sig->sig);
+
+		if (x86 == x86_ucode && x86_model == x86_model_ucode)
+			return UCODE_OK;
+
+		ext_sig++;
+	}
+
+	return UCODE_NFOUND;
+}
+
+static int
+save_microcode(struct mc_saved_data *mc_saved_data,
+	       struct microcode_intel **mc_saved_src,
+	       unsigned int mc_saved_count)
+{
+	int i, j;
+	struct microcode_intel **mc_saved_p;
+	int ret;
+
+	if (!mc_saved_count)
+		return -EINVAL;
+
+	/*
+	 * Copy new microcode data.
+	 */
+	mc_saved_p = kmalloc(mc_saved_count*sizeof(struct microcode_intel *),
+			     GFP_KERNEL);
+	if (!mc_saved_p)
+		return -ENOMEM;
+
+	for (i = 0; i < mc_saved_count; i++) {
+		struct microcode_intel *mc = mc_saved_src[i];
+		struct microcode_header_intel *mc_header = &mc->hdr;
+		unsigned long mc_size = get_totalsize(mc_header);
+		mc_saved_p[i] = kmalloc(mc_size, GFP_KERNEL);
+		if (!mc_saved_p[i]) {
+			ret = -ENOMEM;
+			goto err;
+		}
+		if (!mc_saved_src[i]) {
+			ret = -EINVAL;
+			goto err;
+		}
+		memcpy(mc_saved_p[i], mc, mc_size);
+	}
+
+	/*
+	 * Point to newly saved microcode.
+	 */
+	mc_saved_data->mc_saved = mc_saved_p;
+	mc_saved_data->mc_saved_count = mc_saved_count;
+
+	return 0;
+
+err:
+	for (j = 0; j <= i; j++)
+		kfree(mc_saved_p[j]);
+	kfree(mc_saved_p);
+
+	return ret;
+}
+
+/*
+ * A microcode patch in ucode_ptr is saved into mc_saved
+ * - if it has matching signature and newer revision compared to an existing
+ *   patch mc_saved.
+ * - or if it is a newly discovered microcode patch.
+ *
+ * The microcode patch should have matching model with CPU.
+ */
+static void _save_mc(struct microcode_intel **mc_saved, u8 *ucode_ptr,
+		     unsigned int *mc_saved_count_p)
+{
+	int i;
+	int found = 0;
+	unsigned int mc_saved_count = *mc_saved_count_p;
+	struct microcode_header_intel *mc_header;
+
+	mc_header = (struct microcode_header_intel *)ucode_ptr;
+	for (i = 0; i < mc_saved_count; i++) {
+		unsigned int sig, pf;
+		unsigned int new_rev;
+		struct microcode_header_intel *mc_saved_header =
+			     (struct microcode_header_intel *)mc_saved[i];
+		sig = mc_saved_header->sig;
+		pf = mc_saved_header->pf;
+		new_rev = mc_header->rev;
+
+		if (get_matching_sig(sig, pf, ucode_ptr, new_rev)) {
+			found = 1;
+			if (update_match_revision(mc_header, new_rev)) {
+				/*
+				 * Found an older ucode saved before.
+				 * Replace the older one with this newer
+				 * one.
+				 */
+				mc_saved[i] =
+					(struct microcode_intel *)ucode_ptr;
+				break;
+			}
+		}
+	}
+	if (i >= mc_saved_count && !found)
+		/*
+		 * This ucode is first time discovered in ucode file.
+		 * Save it to memory.
+		 */
+		mc_saved[mc_saved_count++] =
+				 (struct microcode_intel *)ucode_ptr;
+
+	*mc_saved_count_p = mc_saved_count;
+}
+
+/*
+ * Get microcode matching with BSP's model. Only CPUs with the same model as
+ * BSP can stay in the platform.
+ */
+static enum ucode_state __init
+get_matching_model_microcode(int cpu, unsigned long start,
+			     void *data, size_t size,
+			     struct mc_saved_data *mc_saved_data,
+			     unsigned long *mc_saved_in_initrd,
+			     struct ucode_cpu_info *uci)
+{
+	u8 *ucode_ptr = data;
+	unsigned int leftover = size;
+	enum ucode_state state = UCODE_OK;
+	unsigned int mc_size;
+	struct microcode_header_intel *mc_header;
+	struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
+	unsigned int mc_saved_count = mc_saved_data->mc_saved_count;
+	int i;
+
+	while (leftover) {
+		mc_header = (struct microcode_header_intel *)ucode_ptr;
+
+		mc_size = get_totalsize(mc_header);
+		if (!mc_size || mc_size > leftover ||
+			microcode_sanity_check(ucode_ptr, 0) < 0)
+			break;
+
+		leftover -= mc_size;
+
+		/*
+		 * Since APs with same family and model as the BSP may boot in
+		 * the platform, we need to find and save microcode patches
+		 * with the same family and model as the BSP.
+		 */
+		if (matching_model_microcode(mc_header, uci->cpu_sig.sig) !=
+			 UCODE_OK) {
+			ucode_ptr += mc_size;
+			continue;
+		}
+
+		_save_mc(mc_saved_tmp, ucode_ptr, &mc_saved_count);
+
+		ucode_ptr += mc_size;
+	}
+
+	if (leftover) {
+		state = UCODE_ERROR;
+		goto out;
+	}
+
+	if (mc_saved_count == 0) {
+		state = UCODE_NFOUND;
+		goto out;
+	}
+
+	for (i = 0; i < mc_saved_count; i++)
+		mc_saved_in_initrd[i] = (unsigned long)mc_saved_tmp[i] - start;
+
+	mc_saved_data->mc_saved_count = mc_saved_count;
+out:
+	return state;
+}
+
+#define native_rdmsr(msr, val1, val2)		\
+do {						\
+	u64 __val = native_read_msr((msr));	\
+	(void)((val1) = (u32)__val);		\
+	(void)((val2) = (u32)(__val >> 32));	\
+} while (0)
+
+#define native_wrmsr(msr, low, high)		\
+	native_write_msr(msr, low, high);
+
+static int __cpuinit collect_cpu_info_early(struct ucode_cpu_info *uci)
+{
+	unsigned int val[2];
+	u8 x86, x86_model;
+	struct cpu_signature csig;
+	unsigned int eax, ebx, ecx, edx;
+
+	csig.sig = 0;
+	csig.pf = 0;
+	csig.rev = 0;
+
+	memset(uci, 0, sizeof(*uci));
+
+	eax = 0x00000001;
+	ecx = 0;
+	native_cpuid(&eax, &ebx, &ecx, &edx);
+	csig.sig = eax;
+
+	x86 = get_x86_family(csig.sig);
+	x86_model = get_x86_model(csig.sig);
+
+	if ((x86_model >= 5) || (x86 > 6)) {
+		/* get processor flags from MSR 0x17 */
+		native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+		csig.pf = 1 << ((val[1] >> 18) & 7);
+	}
+	native_wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+
+	/* As documented in the SDM: Do a CPUID 1 here */
+	sync_core();
+
+	/* get the current revision from MSR 0x8B */
+	native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
+
+	csig.rev = val[1];
+
+	uci->cpu_sig = csig;
+	uci->valid = 1;
+
+	return 0;
+}
+
+#ifdef DEBUG
+static void __ref show_saved_mc(void)
+{
+	int i, j;
+	unsigned int sig, pf, rev, total_size, data_size, date;
+	struct ucode_cpu_info uci;
+
+	if (mc_saved_data.mc_saved_count == 0) {
+		pr_debug("no micorcode data saved.\n");
+		return;
+	}
+	pr_debug("Total microcode saved: %d\n", mc_saved_data.mc_saved_count);
+
+	collect_cpu_info_early(&uci);
+
+	sig = uci.cpu_sig.sig;
+	pf = uci.cpu_sig.pf;
+	rev = uci.cpu_sig.rev;
+	pr_debug("CPU%d: sig=0x%x, pf=0x%x, rev=0x%x\n",
+		 smp_processor_id(), sig, pf, rev);
+
+	for (i = 0; i < mc_saved_data.mc_saved_count; i++) {
+		struct microcode_header_intel *mc_saved_header;
+		struct extended_sigtable *ext_header;
+		int ext_sigcount;
+		struct extended_signature *ext_sig;
+
+		mc_saved_header = (struct microcode_header_intel *)
+				  mc_saved_data.mc_saved[i];
+		sig = mc_saved_header->sig;
+		pf = mc_saved_header->pf;
+		rev = mc_saved_header->rev;
+		total_size = get_totalsize(mc_saved_header);
+		data_size = get_datasize(mc_saved_header);
+		date = mc_saved_header->date;
+
+		pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, toal size=0x%x, date = %04x-%02x-%02x\n",
+			 i, sig, pf, rev, total_size,
+			 date & 0xffff,
+			 date >> 24,
+			 (date >> 16) & 0xff);
+
+		/* Look for ext. headers: */
+		if (total_size <= data_size + MC_HEADER_SIZE)
+			continue;
+
+		ext_header = (struct extended_sigtable *)
+			     mc_saved_header + data_size + MC_HEADER_SIZE;
+		ext_sigcount = ext_header->count;
+		ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
+
+		for (j = 0; j < ext_sigcount; j++) {
+			sig = ext_sig->sig;
+			pf = ext_sig->pf;
+
+			pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n",
+				 j, sig, pf);
+
+			ext_sig++;
+		}
+
+	}
+}
+#else
+static inline void show_saved_mc(void)
+{
+}
+#endif
+
+#if defined(CONFIG_MICROCODE_INTEL_EARLY) && defined(CONFIG_HOTPLUG_CPU)
+/*
+ * Save this mc into mc_saved_data. So it will be loaded early when a CPU is
+ * hot added or resumes.
+ *
+ * Please make sure this mc should be a valid microcode patch before calling
+ * this function.
+ */
+int save_mc_for_early(u8 *mc)
+{
+	struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
+	unsigned int mc_saved_count_init;
+	unsigned int mc_saved_count;
+	struct microcode_intel **mc_saved;
+	int ret = 0;
+	int i;
+
+	/*
+	 * Hold hotplug lock so mc_saved_data is not accessed by a CPU in
+	 * hotplug.
+	 */
+	cpu_hotplug_driver_lock();
+
+	mc_saved_count_init = mc_saved_data.mc_saved_count;
+	mc_saved_count = mc_saved_data.mc_saved_count;
+	mc_saved = mc_saved_data.mc_saved;
+
+	if (mc_saved && mc_saved_count)
+		memcpy(mc_saved_tmp, mc_saved,
+		       mc_saved_count * sizeof(struct mirocode_intel *));
+	/*
+	 * Save the microcode patch mc in mc_save_tmp structure if it's a newer
+	 * version.
+	 */
+
+	_save_mc(mc_saved_tmp, mc, &mc_saved_count);
+
+	/*
+	 * Save the mc_save_tmp in global mc_saved_data.
+	 */
+	ret = save_microcode(&mc_saved_data, mc_saved_tmp, mc_saved_count);
+	if (ret) {
+		pr_err("Can not save microcode patch.\n");
+		goto out;
+	}
+
+	show_saved_mc();
+
+	/*
+	 * Free old saved microcod data.
+	 */
+	if (mc_saved) {
+		for (i = 0; i < mc_saved_count_init; i++)
+			kfree(mc_saved[i]);
+		kfree(mc_saved);
+	}
+
+out:
+	cpu_hotplug_driver_unlock();
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(save_mc_for_early);
+#endif
+
+static __initdata char ucode_name[] = "kernel/x86/microcode/GenuineIntel.bin";
+static __init enum ucode_state
+scan_microcode(unsigned long start, unsigned long end,
+		struct mc_saved_data *mc_saved_data,
+		unsigned long *mc_saved_in_initrd,
+		struct ucode_cpu_info *uci)
+{
+	unsigned int size = end - start + 1;
+	struct cpio_data cd;
+	long offset = 0;
+	char *p = (char *)__pa_symbol(&ucode_name);
+
+	cd.data = NULL;
+	cd.size = 0;
+
+	cd = find_cpio_data(p, (void *)start, size, &offset);
+	if (!cd.data)
+		return UCODE_ERROR;
+
+
+	return get_matching_model_microcode(0, start, cd.data, cd.size,
+					    mc_saved_data, mc_saved_in_initrd,
+					    uci);
+}
+
+/*
+ * Print ucode update info.
+ */
+static void __cpuinit
+print_ucode_info(struct ucode_cpu_info *uci, unsigned int date)
+{
+	int cpu = smp_processor_id();
+
+	pr_info("CPU%d microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n",
+		cpu,
+		uci->cpu_sig.rev,
+		date & 0xffff,
+		date >> 24,
+		(date >> 16) & 0xff);
+}
+
+#ifdef CONFIG_X86_32
+
+static int delay_ucode_info;
+static int current_mc_date;
+
+/*
+ * Print early updated ucode info after printk works. This is delayed info dump.
+ */
+void __cpuinit show_ucode_info_early(void)
+{
+	struct ucode_cpu_info uci;
+
+	if (delay_ucode_info) {
+		collect_cpu_info_early(&uci);
+		print_ucode_info(&uci, current_mc_date);
+		delay_ucode_info = 0;
+	}
+}
+
+/*
+ * At this point, we can not call printk() yet. Keep microcode patch number in
+ * mc_saved_data.mc_saved and delay printing microcode info in
+ * show_ucode_info_early() until printk() works.
+ */
+static void __cpuinit print_ucode(struct ucode_cpu_info *uci)
+{
+	struct microcode_intel *mc_intel;
+	int *delay_ucode_info_p;
+	int *current_mc_date_p;
+
+	mc_intel = uci->mc;
+	if (mc_intel == NULL)
+		return;
+
+	delay_ucode_info_p = (int *)__pa_symbol(&delay_ucode_info);
+	current_mc_date_p = (int *)__pa_symbol(&current_mc_date);
+
+	*delay_ucode_info_p = 1;
+	*current_mc_date_p = mc_intel->hdr.date;
+}
+#else
+static inline void __cpuinit print_ucode(struct ucode_cpu_info *uci)
+{
+	struct microcode_intel *mc_intel;
+
+	mc_intel = uci->mc;
+	if (mc_intel == NULL)
+		return;
+
+	print_ucode_info(uci, mc_intel->hdr.date);
+}
+#endif
+
+static int apply_microcode_early(struct mc_saved_data *mc_saved_data,
+				 struct ucode_cpu_info *uci)
+{
+	struct microcode_intel *mc_intel;
+	unsigned int val[2];
+
+	mc_intel = uci->mc;
+	if (mc_intel == NULL)
+		return 0;
+
+	/* write microcode via MSR 0x79 */
+	native_wrmsr(MSR_IA32_UCODE_WRITE,
+	      (unsigned long) mc_intel->bits,
+	      (unsigned long) mc_intel->bits >> 16 >> 16);
+	native_wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+
+	/* As documented in the SDM: Do a CPUID 1 here */
+	sync_core();
+
+	/* get the current revision from MSR 0x8B */
+	native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
+	if (val[1] != mc_intel->hdr.rev)
+		return -1;
+
+	uci->cpu_sig.rev = val[1];
+
+	print_ucode(uci);
+
+	return 0;
+}
+
+/*
+ * This function converts microcode patch offsets previously stored in
+ * mc_saved_in_initrd to pointers and stores the pointers in mc_saved_data.
+ */
+int __init save_microcode_in_initrd(void)
+{
+	unsigned int count = mc_saved_data.mc_saved_count;
+	struct microcode_intel *mc_saved[MAX_UCODE_COUNT];
+	int ret = 0;
+
+	if (count == 0)
+		return ret;
+
+	microcode_pointer(mc_saved, mc_saved_in_initrd, initrd_start, count);
+	ret = save_microcode(&mc_saved_data, mc_saved, count);
+	if (ret)
+		pr_err("Can not save microcod patches from initrd");
+
+	show_saved_mc();
+
+	return ret;
+}
+
+static void __init
+_load_ucode_intel_bsp(struct mc_saved_data *mc_saved_data,
+		      unsigned long *mc_saved_in_initrd,
+		      unsigned long initrd_start_early,
+		      unsigned long initrd_end_early,
+		      struct ucode_cpu_info *uci)
+{
+	collect_cpu_info_early(uci);
+	scan_microcode(initrd_start_early, initrd_end_early, mc_saved_data,
+		       mc_saved_in_initrd, uci);
+	load_microcode(mc_saved_data, mc_saved_in_initrd,
+		       initrd_start_early, uci);
+	apply_microcode_early(mc_saved_data, uci);
+}
+
+void __init
+load_ucode_intel_bsp(char *real_mode_data)
+{
+	u64 ramdisk_image, ramdisk_size, ramdisk_end;
+	unsigned long initrd_start_early, initrd_end_early;
+	struct boot_params *boot_params;
+	struct ucode_cpu_info	uci;
+
+	boot_params = (struct boot_params *)real_mode_data;
+	ramdisk_image = boot_params->hdr.ramdisk_image;
+	ramdisk_size  = boot_params->hdr.ramdisk_size;
+
+#ifdef CONFIG_X86_64
+	ramdisk_end  = PAGE_ALIGN(ramdisk_image + ramdisk_size);
+	initrd_start_early = ramdisk_image + PAGE_OFFSET;
+	initrd_end_early = initrd_start_early + ramdisk_size;
+	_load_ucode_intel_bsp(&mc_saved_data, mc_saved_in_initrd,
+			      initrd_start_early, initrd_end_early, &uci);
+#else
+	ramdisk_end  = ramdisk_image + ramdisk_size;
+	initrd_start_early = ramdisk_image;
+	initrd_end_early = initrd_start_early + ramdisk_size;
+	_load_ucode_intel_bsp(
+		(struct mc_saved_data *)__pa_symbol(&mc_saved_data),
+		(unsigned long *)__pa_symbol(&mc_saved_in_initrd),
+		initrd_start_early, initrd_end_early, &uci);
+#endif
+}
+
+void __cpuinit load_ucode_intel_ap(void)
+{
+	struct mc_saved_data *mc_saved_data_p;
+	struct ucode_cpu_info uci;
+	unsigned long *mc_saved_in_initrd_p;
+	unsigned long initrd_start_addr;
+
+#ifdef CONFIG_X86_64
+	mc_saved_data_p = &mc_saved_data;
+	mc_saved_in_initrd_p = mc_saved_in_initrd;
+	initrd_start_addr = initrd_start;
+#else
+	unsigned long *initrd_start_p;
+
+	mc_saved_in_initrd_p =
+		(unsigned long *)__pa_symbol(mc_saved_in_initrd);
+	mc_saved_data_p = (struct mc_saved_data *)__pa_symbol(&mc_saved_data);
+	initrd_start_p = (unsigned long *)__pa_symbol(&initrd_start);
+	initrd_start_addr = (unsigned long)__pa_symbol(*initrd_start_p);
+#endif
+	/*
+	 * If there is no valid ucode previously saved in memory, no need to
+	 * update ucode on this AP.
+	 */
+	if (mc_saved_data_p->mc_saved_count == 0)
+		return;
+
+	collect_cpu_info_early(&uci);
+	load_microcode(mc_saved_data_p, mc_saved_in_initrd_p,
+		       initrd_start_addr, &uci);
+	apply_microcode_early(mc_saved_data_p, &uci);
+}
-- 
1.8.0.1

[PATCH v3 07/10] x86/head_32.S: Early update ucode in 32-bit

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

This updates ucode in 32-bit kernel. At this point, there is no paging and no
virtual address yet.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/kernel/head_32.S | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index 8e7f655..fdc11f6 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -144,6 +144,12 @@ ENTRY(startup_32)
 	movl %eax, pa(olpc_ofw_pgd)
 #endif
 
+#ifdef CONFIG_MICROCODE_EARLY
+	/* Early load ucode on BSP. */
+	movl $pa(boot_params), %eax
+	call load_ucode_bsp
+#endif
+
 /*
  * Initialize page tables.  This creates a PDE and a set of page
  * tables, which are located immediately beyond __brk_base.  The variable
@@ -299,6 +305,12 @@ ENTRY(startup_32_smp)
 	movl %eax,%ss
 	leal -__PAGE_OFFSET(%ecx),%esp
 
+#ifdef CONFIG_MICROCODE_EARLY
+	/* Early load ucode on AP. */
+	call load_ucode_ap
+#endif
+
+
 default_entry:
 /*
  *	New page tables may be in 4Mbyte page mode and may
-- 
1.8.0.1

[PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

This updates ucode in 64-bit mode. Paging and virtual address are working now.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/kernel/head64.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 037df57..a512f56 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -25,6 +25,7 @@
 #include <asm/kdebug.h>
 #include <asm/e820.h>
 #include <asm/bios_ebda.h>
+#include <asm/microcode.h>
 
 static void __init zap_identity_mappings(void)
 {
@@ -73,6 +74,11 @@ void __init x86_64_start_kernel(char * real_mode_data)
 	/* clear bss before set_intr_gate with early_idt_handler */
 	clear_bss();
 
+	/*
+	 * Load microcode early on BSP.
+	 */
+	load_ucode_bsp(real_mode_data);
+
 	/* Make NULL pointers segfault */
 	zap_identity_mappings();
 
-- 
1.8.0.1

[PATCH v3 09/10] x86/mm/init.c: Copy ucode from initrd image to memory

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

Before initrd image is freed, copy valid ucode patches from initrd image
to kernel virtual memory. The saved ucode will be used to update AP in resume
or hotplug.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/mm/init.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index d7aea41..e5e7973 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -16,6 +16,7 @@
 #include <asm/tlb.h>
 #include <asm/proto.h>
 #include <asm/dma.h>		/* for MAX_DMA_PFN */
+#include <asm/microcode.h>
 
 unsigned long __initdata pgt_buf_start;
 unsigned long __meminitdata pgt_buf_end;
@@ -391,6 +392,15 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
+#ifdef CONFIG_MICROCODE_EARLY
+	/*
+	 * Remember, initrd memory may contain microcode or other useful things.
+	 * Before we lose initrd mem, we need to find a place to hold them
+	 * now that normal virtual memory is enabled.
+	 */
+	save_microcode_in_initrd();
+#endif
+
 	/*
 	 * end could be not aligned, and We can not align that,
 	 * decompresser could be confused by aligned initrd_end
-- 
1.8.0.1

[PATCH v3 10/10] x86/Kconfig: Configurations to enable/disable the feature

[Fenghua Yu]

From: Fenghua Yu <fenghua.yu@intel.com>

MICROCODE_INTEL_LIB, MICROCODE_INTEL_EARLY, and MICROCODE_EARLY are three new
configurations to enable or disable the feature.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 arch/x86/Kconfig | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 65a872b..edf6fd2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1028,6 +1028,24 @@ config MICROCODE_OLD_INTERFACE
 	def_bool y
 	depends on MICROCODE
 
+config MICROCODE_INTEL_LIB
+	def_bool y
+	depends on MICROCODE_INTEL
+
+config MICROCODE_INTEL_EARLY
+	bool "Early load microcode"
+	depends on MICROCODE_INTEL && BLK_DEV_INITRD
+	default y
+	help
+	  This option provides functionality to read additional microcode data
+	  at the beginning of initrd image. The data tells kernel to load
+	  microcode to CPU's as early as possible. No functional change if no
+	  microcode data is glued to the initrd, therefore it's safe to say Y.
+
+config MICROCODE_EARLY
+	def_bool y
+	depends on MICROCODE_INTEL_EARLY
+
 config X86_MSR
 	tristate "/dev/cpu/*/msr - Model-specific register support"
 	---help---
-- 
1.8.0.1

Re: [PATCH v3 04/10] x86/microcode_core_early.c: Define interfaces for early loading ucode

[Borislav Petkov]

On Sun, Dec 16, 2012 at 02:43:23AM -0800, Fenghua Yu wrote:
> +#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
> +#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
> +#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
> +#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
> +#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
> +#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
> +#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
> +
> +#define CPUID_IS(a, b, c) (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))

What, this macro is relying on external variable names and doesn't have
them as its own macro arguments? Why? This is really fragile and very
much prone to errors.

What's wrong with doing:

#define CPUID_IS(a, b, c, ebx, ecx, edx) (!(((ebx) ^ (a))|((edx) ^ (b))|((ecx) ^ (c))))

?

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
--

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yinghai Lu]

On Sun, Dec 16, 2012 at 2:43 AM, Fenghua Yu <fenghua.yu@intel.com> wrote:
> From: Fenghua Yu <fenghua.yu@intel.com>
>
> This updates ucode in 64-bit mode. Paging and virtual address are working now.
>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> ---
>  arch/x86/kernel/head64.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
> index 037df57..a512f56 100644
> --- a/arch/x86/kernel/head64.c
> +++ b/arch/x86/kernel/head64.c
> @@ -25,6 +25,7 @@
>  #include <asm/kdebug.h>
>  #include <asm/e820.h>
>  #include <asm/bios_ebda.h>
> +#include <asm/microcode.h>
>
>  static void __init zap_identity_mappings(void)
>  {
> @@ -73,6 +74,11 @@ void __init x86_64_start_kernel(char * real_mode_data)
>         /* clear bss before set_intr_gate with early_idt_handler */
>         clear_bss();
>
> +       /*
> +        * Load microcode early on BSP.
> +        */
> +       load_ucode_bsp(real_mode_data);
> +
>         /* Make NULL pointers segfault */
>         zap_identity_mappings();
>

So this patchset is after #PF handler set early page table version?

then load_ucode_bsp() should be after

   load_idt((const struct desc_ptr *)&idt_descr);

otherwise it will not work.

Yinghai

RE: [PATCH v3 04/10] x86/microcode_core_early.c: Define interfaces for early loading ucode

[Yu, Fenghua]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1555 bytes --]

> -----Original Message-----
> From: Borislav Petkov [mailto:bp@alien8.de]
> Sent: Sunday, December 16, 2012 9:57 AM
> To: Yu, Fenghua
> Cc: H Peter Anvin; Ingo Molnar; Thomas Gleixner; Mallick, Asit K;
> Tigran Aivazian; Andreas Herrmann; Borislav Petkov; Yinghai Lu; linux-
> kernel; x86
> Subject: Re: [PATCH v3 04/10] x86/microcode_core_early.c: Define
> interfaces for early loading ucode
> 
> On Sun, Dec 16, 2012 at 02:43:23AM -0800, Fenghua Yu wrote:
> > +#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) <<
> 24))
> > +#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
> > +#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
> > +#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
> > +#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
> > +#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
> > +#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
> > +
> > +#define CPUID_IS(a, b, c) (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
> 
> What, this macro is relying on external variable names and doesn't have
> them as its own macro arguments? Why? This is really fragile and very
> much prone to errors.
> 
> What's wrong with doing:
> 
> #define CPUID_IS(a, b, c, ebx, ecx, edx) (!(((ebx) ^ (a))|((edx) ^
> (b))|((ecx) ^ (c))))
> 
> ?

Nothing wrong with taking the parameters. But CPUID_IS is only limited in this file. There is no other places to use it. I think either way is ok.

Thanks.

-Fenghua
ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

Re: [PATCH v3 04/10] x86/microcode_core_early.c: Define interfaces for early loading ucode

[Borislav Petkov]

On Sun, Dec 16, 2012 at 06:09:12PM +0000, Yu, Fenghua wrote:
> Nothing wrong with taking the parameters. But CPUID_IS is only limited
> in this file. There is no other places to use it. I think either way
> is ok.

Please don't do this. Anything can happen, someone can copy it somewhere
else and try to use it, unification, code movement can all of a sudden
break things in the most mysterious ways.

However, if you make the macro definition self-contained. none of those
issues will happen.

Thanks.

-- 
Regards/Gruss,
    Boris.

Sent from a fat crate under my desk. Formatting is fine.
--

RE: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yu, Fenghua]

> -----Original Message-----
> From: yhlu.kernel@gmail.com [mailto:yhlu.kernel@gmail.com] On Behalf Of
> Yinghai Lu
> Sent: Sunday, December 16, 2012 9:59 AM
> To: Yu, Fenghua
> Cc: H Peter Anvin; Ingo Molnar; Thomas Gleixner; Mallick, Asit K;
> Tigran Aivazian; Andreas Herrmann; Borislav Petkov; linux-kernel; x86
> Subject: Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-
> bit
> 
> On Sun, Dec 16, 2012 at 2:43 AM, Fenghua Yu <fenghua.yu@intel.com>
> wrote:
> > From: Fenghua Yu <fenghua.yu@intel.com>
> >
> > This updates ucode in 64-bit mode. Paging and virtual address are
> working now.
> >
> > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> > ---
> >  arch/x86/kernel/head64.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
> > index 037df57..a512f56 100644
> > --- a/arch/x86/kernel/head64.c
> > +++ b/arch/x86/kernel/head64.c
> > @@ -25,6 +25,7 @@
> >  #include <asm/kdebug.h>
> >  #include <asm/e820.h>
> >  #include <asm/bios_ebda.h>
> > +#include <asm/microcode.h>
> >
> >  static void __init zap_identity_mappings(void)
> >  {
> > @@ -73,6 +74,11 @@ void __init x86_64_start_kernel(char *
> real_mode_data)
> >         /* clear bss before set_intr_gate with early_idt_handler */
> >         clear_bss();
> >
> > +       /*
> > +        * Load microcode early on BSP.
> > +        */
> > +       load_ucode_bsp(real_mode_data);
> > +
> >         /* Make NULL pointers segfault */
> >         zap_identity_mappings();
> >
> 
> So this patchset is after #PF handler set early page table version?
> 
> then load_ucode_bsp() should be after
> 
>    load_idt((const struct desc_ptr *)&idt_descr);
> 
> otherwise it will not work.
> 
> Yinghai

load_ucode_bsp() only accesses initrd image, a few global variables. It doesn't call any other kernel functions (e.g. printk or kmalloc()). It is like this mainly because it works on both 32 and 64 bit.

So there is no PF and idt should not impact the function, right?

Thanks.

-Fenghua

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[H. Peter Anvin]

On 12/16/2012 09:59 AM, Yinghai Lu wrote:
>> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
>> index 037df57..a512f56 100644
>> --- a/arch/x86/kernel/head64.c
>> +++ b/arch/x86/kernel/head64.c
>> @@ -25,6 +25,7 @@
>>  #include <asm/kdebug.h>
>>  #include <asm/e820.h>
>>  #include <asm/bios_ebda.h>
>> +#include <asm/microcode.h>
>>
>>  static void __init zap_identity_mappings(void)
>>  {
>> @@ -73,6 +74,11 @@ void __init x86_64_start_kernel(char * real_mode_data)
>>         /* clear bss before set_intr_gate with early_idt_handler */
>>         clear_bss();
>>
>> +       /*
>> +        * Load microcode early on BSP.
>> +        */
>> +       load_ucode_bsp(real_mode_data);
>> +
>>         /* Make NULL pointers segfault */
>>         zap_identity_mappings();
>>
> 
> So this patchset is after #PF handler set early page table version?
> 
> then load_ucode_bsp() should be after
> 
>    load_idt((const struct desc_ptr *)&idt_descr);
> 

This patchset isn't before the #PF handler version (you can tell because
it has zap_identity_mappings()), but it does make sense to load the IDT
first.

	-hpa

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yinghai Lu]

On Sun, Dec 16, 2012 at 1:43 PM, H. Peter Anvin <hpa@zytor.com> wrote:
> On 12/16/2012 09:59 AM, Yinghai Lu wrote:
>>> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
>>> index 037df57..a512f56 100644
>>> --- a/arch/x86/kernel/head64.c
>>> +++ b/arch/x86/kernel/head64.c
>>> @@ -25,6 +25,7 @@
>>>  #include <asm/kdebug.h>
>>>  #include <asm/e820.h>
>>>  #include <asm/bios_ebda.h>
>>> +#include <asm/microcode.h>
>>>
>>>  static void __init zap_identity_mappings(void)
>>>  {
>>> @@ -73,6 +74,11 @@ void __init x86_64_start_kernel(char * real_mode_data)
>>>         /* clear bss before set_intr_gate with early_idt_handler */
>>>         clear_bss();
>>>
>>> +       /*
>>> +        * Load microcode early on BSP.
>>> +        */
>>> +       load_ucode_bsp(real_mode_data);
>>> +
>>>         /* Make NULL pointers segfault */
>>>         zap_identity_mappings();
>>>
>>
>> So this patchset is after #PF handler set early page table version?
>>
>> then load_ucode_bsp() should be after
>>
>>    load_idt((const struct desc_ptr *)&idt_descr);
>>
>
> This patchset isn't before the #PF handler version (you can tell because
> it has zap_identity_mappings()), but it does make sense to load the IDT
> first.

it has to be rebased after #PF handler version. otherwise it can not
handle for framdisk
that is loaded after 1G.

Fenghua,

can you post your boot log with 64bit with your patch?

Yinghai

RE: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yu, Fenghua]

[-- Attachment #1: Type: text/plain, Size: 457 bytes --]


> > This patchset isn't before the #PF handler version (you can tell
> because
> > it has zap_identity_mappings()), but it does make sense to load the
> IDT
> > first.
> 
> it has to be rebased after #PF handler version. otherwise it can not
> handle for framdisk
> that is loaded after 1G.
> 
> Fenghua,
> 
> can you post your boot log with 64bit with your patch?
> 
> Yinghai

Attached is dmesg with the patches.

Thanks.

-Fenghua

[-- Attachment #2: early_ucode_dmesg --]
[-- Type: application/octet-stream, Size: 68615 bytes --]

[    0.000000] CPU0 microcode updated early to revision 0xa4, date = 2010-10-02
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 3.7.0+ (fyu@linux-romley1.sc.intel.com) (gcc version 4.7.0 20120507 (Red Hat 4.7.0-5) (GCC) ) #17 SMP Sun Dec 16 08:39:17 PST 2012
[    0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-3.7.0 root=UUID=94addf6f-dd82-48fd-bb1b-809567e7a9a4 ro rd.md=0 rd.lvm=0 rd.dm=0 SYSFONT=True KEYTABLE=us rd.luks=0 LANG=en_US.UTF-8 rhgb quiet
[    0.000000] e820: BIOS-provided physical RAM map:
[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009d7ff] usable
[    0.000000] BIOS-e820: [mem 0x000000000009d800-0x000000000009ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000000d2000-0x00000000000d3fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000003e6affff] usable
[    0.000000] BIOS-e820: [mem 0x000000003e6b0000-0x000000003e6ccfff] ACPI data
[    0.000000] BIOS-e820: [mem 0x000000003e6cd000-0x000000003e6fffff] ACPI NVS
[    0.000000] BIOS-e820: [mem 0x000000003e700000-0x000000003effffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed14000-0x00000000fed19fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[    0.000000] NX (Execute Disable) protection: active
[    0.000000] DMI present.
[    0.000000] DMI: LENOVO 7658CTO/7658CTO, BIOS 7LET37WW (1.07 ) 04/17/2007
[    0.000000] e820: update [mem 0x00000000-0x0000ffff] usable ==> reserved
[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
[    0.000000] No AGP bridge found
[    0.000000] e820: last_pfn = 0x3e6b0 max_arch_pfn = 0x400000000
[    0.000000] MTRR default type: uncachable
[    0.000000] MTRR fixed ranges enabled:
[    0.000000]   00000-9FFFF write-back
[    0.000000]   A0000-BFFFF uncachable
[    0.000000]   C0000-CFFFF write-protect
[    0.000000]   D0000-DFFFF uncachable
[    0.000000]   E0000-FFFFF write-protect
[    0.000000] MTRR variable ranges enabled:
[    0.000000]   0 base 03F000000 mask FFF000000 uncachable
[    0.000000]   1 base 000000000 mask FC0000000 write-back
[    0.000000]   2 base 03E700000 mask FFFF00000 uncachable
[    0.000000]   3 base 03E800000 mask FFF800000 uncachable
[    0.000000]   4 disabled
[    0.000000]   5 disabled
[    0.000000]   6 disabled
[    0.000000]   7 disabled
[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[    0.000000] original variable MTRRs
[    0.000000] reg 0, base: 1008MB, range: 16MB, type UC
[    0.000000] reg 1, base: 0GB, range: 1GB, type WB
[    0.000000] reg 2, base: 999MB, range: 1MB, type UC
[    0.000000] reg 3, base: 1000MB, range: 8MB, type UC
[    0.000000] total RAM covered: 999M
[    0.000000] Found optimal setting for mtrr clean up
[    0.000000]  gran_size: 64K 	chunk_size: 32M 	num_reg: 4  	lose cover RAM: 0G
[    0.000000] New variable MTRRs
[    0.000000] reg 0, base: 0GB, range: 1GB, type WB
[    0.000000] reg 1, base: 999MB, range: 1MB, type UC
[    0.000000] reg 2, base: 1000MB, range: 8MB, type UC
[    0.000000] reg 3, base: 1008MB, range: 16MB, type UC
[    0.000000] found SMP MP-table at [mem 0x000f6900-0x000f690f] mapped at [ffff8800000f6900]
[    0.000000] initial memory mapped: [mem 0x00000000-0x1fffffff]
[    0.000000] Base memory trampoline at [ffff880000097000] 97000 size 24576
[    0.000000] init_memory_mapping: [mem 0x00000000-0x3e6affff]
[    0.000000]  [mem 0x00000000-0x3e5fffff] page 2M
[    0.000000]  [mem 0x3e600000-0x3e6affff] page 4k
[    0.000000] kernel direct mapping tables up to 0x3e6affff @ [mem 0x1fffd000-0x1fffffff]
[    0.000000] RAMDISK: [mem 0x27608000-0x2fafbfff]
[    0.000000] ACPI: RSDP 00000000000f68d0 00024 (v02 LENOVO)
[    0.000000] ACPI: XSDT 000000003e6bdfb8 00094 (v01 LENOVO TP-7L    00001070  LTP 00000000)
[    0.000000] ACPI: FACP 000000003e6be100 000F4 (v03 LENOVO TP-7L    00001070 LNVO 00000001)
[    0.000000] ACPI BIOS Bug: Warning: 32/64X length mismatch in FADT/Gpe1Block: 0/32 (20121018/tbfadt-567)
[    0.000000] ACPI BIOS Bug: Warning: Optional FADT field Gpe1Block has zero address or length: 0x000000000000102C/0x0 (20121018/tbfadt-598)
[    0.000000] ACPI: DSDT 000000003e6be50c 0E6A9 (v01 LENOVO TP-7L    00001070 MSFT 03000000)
[    0.000000] ACPI: FACS 000000003e6e4000 00040
[    0.000000] ACPI: SSDT 000000003e6be2b4 00258 (v01 LENOVO TP-7L    00001070 MSFT 03000000)
[    0.000000] ACPI: ECDT 000000003e6ccbb5 00052 (v01 LENOVO TP-7L    00001070 LNVO 00000001)
[    0.000000] ACPI: TCPA 000000003e6ccc07 00032 (v02 LENOVO TP-7L    00001070 LNVO 00000001)
[    0.000000] ACPI: APIC 000000003e6ccc39 00068 (v01 LENOVO TP-7L    00001070 LNVO 00000001)
[    0.000000] ACPI: MCFG 000000003e6ccca1 0003C (v01 LENOVO TP-7L    00001070 LNVO 00000001)
[    0.000000] ACPI: HPET 000000003e6cccdd 00038 (v01 LENOVO TP-7L    00001070 LNVO 00000001)
[    0.000000] ACPI: SLIC 000000003e6ccdf0 00176 (v01 LENOVO TP-7L    00001070  LTP 00000000)
[    0.000000] ACPI: BOOT 000000003e6ccf66 00028 (v01 LENOVO TP-7L    00001070  LTP 00000001)
[    0.000000] ACPI: ASF! 000000003e6ccf8e 00072 (v16 LENOVO TP-7L    00001070 PTL  00000001)
[    0.000000] ACPI: SSDT 000000003e6e2697 0025F (v01 LENOVO TP-7L    00001070 INTL 20050513)
[    0.000000] ACPI: SSDT 000000003e6e28f6 000A6 (v01 LENOVO TP-7L    00001070 INTL 20050513)
[    0.000000] ACPI: SSDT 000000003e6e299c 004F7 (v01 LENOVO TP-7L    00001070 INTL 20050513)
[    0.000000] ACPI: SSDT 000000003e6e2e93 001D8 (v01 LENOVO TP-7L    00001070 INTL 20050513)
[    0.000000] ACPI: DMI detected: Lenovo ThinkPad T61
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] No NUMA configuration found
[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000003e6affff]
[    0.000000] Initmem setup node 0 [mem 0x00000000-0x3e6affff]
[    0.000000]   NODE_DATA [mem 0x3e69c000-0x3e6affff]
[    0.000000]  [ffffea0000000000-ffffea0000ffffff] PMD -> [ffff88003ce00000-ffff88003ddfffff] on node 0
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x00010000-0x00ffffff]
[    0.000000]   DMA32    [mem 0x01000000-0xffffffff]
[    0.000000]   Normal   empty
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x00010000-0x0009cfff]
[    0.000000]   node   0: [mem 0x00100000-0x3e6affff]
[    0.000000] On node 0 totalpages: 255549
[    0.000000]   DMA zone: 64 pages used for memmap
[    0.000000]   DMA zone: 6 pages reserved
[    0.000000]   DMA zone: 3911 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 3931 pages used for memmap
[    0.000000]   DMA32 zone: 247637 pages, LIFO batch:31
[    0.000000] ACPI: PM-Timer IO Port: 0x1008
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[    0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ2 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
[    0.000000] smpboot: Allowing 2 CPUs, 0 hotplug CPUs
[    0.000000] nr_irqs_gsi: 40
[    0.000000] PM: Registered nosave memory: 000000000009d000 - 000000000009e000
[    0.000000] PM: Registered nosave memory: 000000000009e000 - 00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000d2000
[    0.000000] PM: Registered nosave memory: 00000000000d2000 - 00000000000d4000
[    0.000000] PM: Registered nosave memory: 00000000000d4000 - 00000000000e0000
[    0.000000] PM: Registered nosave memory: 00000000000e0000 - 0000000000100000
[    0.000000] e820: [mem 0x3f000000-0xefffffff] available for PCI devices
[    0.000000] Booting paravirtualized kernel on bare hardware
[    0.000000] setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:2 nr_node_ids:1
[    0.000000] PERCPU: Embedded 28 pages/cpu @ffff88003e400000 s84416 r8192 d22080 u1048576
[    0.000000] pcpu-alloc: s84416 r8192 d22080 u1048576 alloc=1*2097152
[    0.000000] pcpu-alloc: [0] 0 1 
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 251548
[    0.000000] Policy zone: DMA32
[    0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.7.0 root=UUID=94addf6f-dd82-48fd-bb1b-809567e7a9a4 ro rd.md=0 rd.lvm=0 rd.dm=0 SYSFONT=True KEYTABLE=us rd.luks=0 LANG=en_US.UTF-8 rhgb quiet
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] __ex_table already sorted, skipping sort
[    0.000000] Checking aperture...
[    0.000000] No AGP bridge found
[    0.000000] Memory: 853560k/1022656k available (6328k kernel code, 460k absent, 168636k reserved, 6868k data, 1060k init)
[    0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] 	RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2.
[    0.000000] NR_IRQS:4352 nr_irqs:512 16
[    0.000000] Extended CMOS year: 2000
[    0.000000] Console: colour VGA+ 80x25
[    0.000000] console [tty0] enabled
[    0.000000] hpet clockevent registered
[    0.000000] tsc: Fast TSC calibration using PIT
[    0.000000] tsc: Detected 1795.666 MHz processor
[    0.001004] Calibrating delay loop (skipped), value calculated using timer frequency.. 3591.33 BogoMIPS (lpj=1795666)
[    0.001008] pid_max: default: 32768 minimum: 301
[    0.001047] Security Framework initialized
[    0.001060] SELinux:  Initializing.
[    0.001073] SELinux:  Starting in permissive mode
[    0.001234] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.002239] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes)
[    0.002548] Mount-cache hash table entries: 256
[    0.002821] Initializing cgroup subsys cpuacct
[    0.002824] Initializing cgroup subsys devices
[    0.002826] Initializing cgroup subsys freezer
[    0.002828] Initializing cgroup subsys net_cls
[    0.002830] Initializing cgroup subsys blkio
[    0.002832] Initializing cgroup subsys perf_event
[    0.002863] CPU: Physical Processor ID: 0
[    0.002865] CPU: Processor Core ID: 0
[    0.002867] mce: CPU supports 6 MCE banks
[    0.002875] CPU0: Thermal monitoring enabled (TM2)
[    0.002879] process: using mwait in idle threads
[    0.002885] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4
[    0.002885] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32
[    0.002885] tlb_flushall_shift: -1
[    0.003026] Freeing SMP alternatives: 24k freed
[    0.004696] ACPI: Core revision 20121018
[    0.014017] ftrace: allocating 23864 entries in 94 pages
[    0.023400] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    0.033416] smpboot: CPU0: Intel(R) Core(TM)2 Duo CPU     T7100  @ 1.80GHz (fam: 06, model: 0f, stepping: 0d)
[    0.034000] Performance Events: PEBS fmt0+, 4-deep LBR, Core2 events, Intel PMU driver.
[    0.034000] perf_event_intel: PEBS disabled due to CPU errata
[    0.034000] ... version:                2
[    0.034000] ... bit width:              40
[    0.034000] ... generic registers:      2
[    0.034000] ... value mask:             000000ffffffffff
[    0.034000] ... max period:             000000007fffffff
[    0.034000] ... fixed-purpose events:   3
[    0.034000] ... event mask:             0000000700000003
[    0.034705] smpboot: Booting Node   0, Processors  #1 OK
[    0.002000] CPU1 microcode updated early to revision 0xa4, date = 2010-10-02
[    0.046000] TSC synchronization [CPU#0 -> CPU#1]:
[    0.046000] Measured 327015 cycles TSC warp between CPUs, turning off TSC clock.
[    0.046000] tsc: Marking TSC unstable due to check_tsc_sync_source failed
[    0.046031] Brought up 2 CPUs
[    0.046034] smpboot: Total of 2 processors activated (7182.66 BogoMIPS)
[    0.047009] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
[    0.048122] devtmpfs: initialized
[    0.048230] PM: Registering ACPI NVS region [mem 0x3e6cd000-0x3e6fffff] (208896 bytes)
[    0.050172] atomic64 test passed for x86-64 platform with CX8 and with SSE
[    0.050212] RTC time:  0:07:21, date: 12/17/12
[    0.050263] NET: Registered protocol family 16
[    0.050484] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
[    0.050487] ACPI: bus type pci registered
[    0.050566] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf0000000-0xf3ffffff] (base 0xf0000000)
[    0.050571] PCI: MMCONFIG at [mem 0xf0000000-0xf3ffffff] reserved in E820
[    0.057013] PCI: Using configuration type 1 for base access
[    0.058179] bio: create slab <bio-0> at 0
[    0.058179] ACPI: Added _OSI(Module Device)
[    0.058179] ACPI: Added _OSI(Processor Device)
[    0.058179] ACPI: Added _OSI(3.0 _SCP Extensions)
[    0.058179] ACPI: Added _OSI(Processor Aggregator Device)
[    0.058179] ACPI: Added _OSI(Linux)
[    0.059924] ACPI: EC: EC description table is found, configuring boot EC
[    0.071500] ACPI: SSDT 000000003e6e1d72 00282 (v01  PmRef  Cpu0Ist 00000100 INTL 20050513)
[    0.071516] ACPI: Dynamic OEM Table Load:
[    0.071520] ACPI: SSDT           (null) 00282 (v01  PmRef  Cpu0Ist 00000100 INTL 20050513)
[    0.071660] ACPI: SSDT 000000003e6e2079 0061E (v01  PmRef  Cpu0Cst 00000100 INTL 20050513)
[    0.072279] ACPI: Dynamic OEM Table Load:
[    0.072282] ACPI: SSDT           (null) 0061E (v01  PmRef  Cpu0Cst 00000100 INTL 20050513)
[    0.075228] ACPI: SSDT 000000003e6e1caa 000C8 (v01  PmRef  Cpu1Ist 00000100 INTL 20050513)
[    0.075816] ACPI: Dynamic OEM Table Load:
[    0.075819] ACPI: SSDT           (null) 000C8 (v01  PmRef  Cpu1Ist 00000100 INTL 20050513)
[    0.075913] ACPI: SSDT 000000003e6e1ff4 00085 (v01  PmRef  Cpu1Cst 00000100 INTL 20050513)
[    0.076497] ACPI: Dynamic OEM Table Load:
[    0.076501] ACPI: SSDT           (null) 00085 (v01  PmRef  Cpu1Cst 00000100 INTL 20050513)
[    0.079209] ACPI: Interpreter enabled
[    0.079213] ACPI: (supports S0 S3 S4 S5)
[    0.079233] ACPI: Using IOAPIC for interrupt routing
[    0.083050] ACPI: Power Resource [PUBS] (on)
[    0.087570] ACPI: EC: GPE = 0x12, I/O: command/status = 0x66, data = 0x62
[    0.088886] ACPI: ACPI Dock Station Driver: 3 docks/bays found
[    0.088892] PCI: Ignoring host bridge windows from ACPI; if necessary, use "pci=use_crs" and report a bug
[    0.088919] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[    0.088922] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[    0.089451] pci_root PNP0A08:00: Requesting ACPI _OSC control (0x1d)
[    0.089849] pci_root PNP0A08:00: ACPI _OSC control (0x1d) granted
[    0.089884] pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7] (ignored)
[    0.089888] pci_root PNP0A08:00: host bridge window [io  0x0d00-0xffff] (ignored)
[    0.089891] pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff] (ignored)
[    0.089895] pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff] (ignored)
[    0.089898] pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff] (ignored)
[    0.089901] pci_root PNP0A08:00: host bridge window [mem 0x000dc000-0x000dffff] (ignored)
[    0.089905] pci_root PNP0A08:00: host bridge window [mem 0x3f000000-0xfebfffff] (ignored)
[    0.089908] pci_root PNP0A08:00: host bridge window [mem 0xfed40000-0xfed4bfff] (ignored)
[    0.089911] PCI: root bus 00: using default resources
[    0.089915] pci_root PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge
[    0.089951] PCI host bridge to bus 0000:00
[    0.089956] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.089958] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    0.089961] pci_bus 0000:00: root bus resource [mem 0x00000000-0xfffffffff]
[    0.089974] pci 0000:00:00.0: [8086:2a00] type 00 class 0x060000
[    0.090037] pci 0000:00:02.0: [8086:2a02] type 00 class 0x030000
[    0.090053] pci 0000:00:02.0: reg 10: [mem 0xf8100000-0xf81fffff 64bit]
[    0.090064] pci 0000:00:02.0: reg 18: [mem 0xe0000000-0xefffffff 64bit pref]
[    0.090071] pci 0000:00:02.0: reg 20: [io  0x1800-0x1807]
[    0.090116] pci 0000:00:02.1: [8086:2a03] type 00 class 0x038000
[    0.090129] pci 0000:00:02.1: reg 10: [mem 0xf8200000-0xf82fffff 64bit]
[    0.090205] pci 0000:00:03.0: [8086:2a04] type 00 class 0x078000
[    0.090223] pci 0000:00:03.0: reg 10: [mem 0xfe226800-0xfe22680f 64bit]
[    0.090280] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[    0.090303] pci 0000:00:03.2: [8086:2a06] type 00 class 0x010185
[    0.090319] pci 0000:00:03.2: reg 10: [io  0x1828-0x182f]
[    0.090327] pci 0000:00:03.2: reg 14: [io  0x180c-0x180f]
[    0.090335] pci 0000:00:03.2: reg 18: [io  0x1820-0x1827]
[    0.090343] pci 0000:00:03.2: reg 1c: [io  0x1808-0x180b]
[    0.090352] pci 0000:00:03.2: reg 20: [io  0x1810-0x181f]
[    0.090408] pci 0000:00:03.3: [8086:2a07] type 00 class 0x070002
[    0.090423] pci 0000:00:03.3: reg 10: [io  0x1830-0x1837]
[    0.090431] pci 0000:00:03.3: reg 14: [mem 0xfe024000-0xfe024fff]
[    0.090615] pci 0000:00:19.0: [8086:1049] type 00 class 0x020000
[    0.090675] pci 0000:00:19.0: reg 10: [mem 0xfe000000-0xfe01ffff]
[    0.090697] pci 0000:00:19.0: reg 14: [mem 0xfe025000-0xfe025fff]
[    0.090723] pci 0000:00:19.0: reg 18: [io  0x1840-0x185f]
[    0.090924] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold
[    0.090972] pci 0000:00:1a.0: [8086:2834] type 00 class 0x0c0300
[    0.091104] pci 0000:00:1a.0: reg 20: [io  0x1860-0x187f]
[    0.091209] pci 0000:00:1a.1: [8086:2835] type 00 class 0x0c0300
[    0.091341] pci 0000:00:1a.1: reg 20: [io  0x1880-0x189f]
[    0.091472] pci 0000:00:1a.7: [8086:283a] type 00 class 0x0c0320
[    0.091524] pci 0000:00:1a.7: reg 10: [mem 0xfe226c00-0xfe226fff]
[    0.091786] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold
[    0.091866] pci 0000:00:1b.0: [8086:284b] type 00 class 0x040300
[    0.091918] pci 0000:00:1b.0: reg 10: [mem 0xfe020000-0xfe023fff 64bit]
[    0.092155] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
[    0.092229] pci 0000:00:1c.0: [8086:283f] type 01 class 0x060400
[    0.092492] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[    0.092572] pci 0000:00:1c.1: [8086:2841] type 01 class 0x060400
[    0.092833] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
[    0.092905] pci 0000:00:1c.2: [8086:2843] type 01 class 0x060400
[    0.093174] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold
[    0.093257] pci 0000:00:1c.3: [8086:2845] type 01 class 0x060400
[    0.093520] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
[    0.093602] pci 0000:00:1c.4: [8086:2847] type 01 class 0x060400
[    0.093856] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
[    0.093930] pci 0000:00:1d.0: [8086:2830] type 00 class 0x0c0300
[    0.094064] pci 0000:00:1d.0: reg 20: [io  0x18a0-0x18bf]
[    0.094165] pci 0000:00:1d.1: [8086:2831] type 00 class 0x0c0300
[    0.094304] pci 0000:00:1d.1: reg 20: [io  0x18c0-0x18df]
[    0.094401] pci 0000:00:1d.2: [8086:2832] type 00 class 0x0c0300
[    0.094535] pci 0000:00:1d.2: reg 20: [io  0x18e0-0x18ff]
[    0.094669] pci 0000:00:1d.7: [8086:2836] type 00 class 0x0c0320
[    0.094729] pci 0000:00:1d.7: reg 10: [mem 0xfe227000-0xfe2273ff]
[    0.094985] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
[    0.095046] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401
[    0.095270] pci 0000:00:1f.0: [8086:2811] type 00 class 0x060100
[    0.095466] pci 0000:00:1f.0: quirk: [io  0x1000-0x107f] claimed by ICH6 ACPI/GPIO/TCO
[    0.095477] pci 0000:00:1f.0: quirk: [io  0x1180-0x11bf] claimed by ICH6 GPIO
[    0.095485] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 1 PIO at 1600 (mask 007f)
[    0.095492] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 2 PIO at 15e0 (mask 000f)
[    0.095499] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 3 PIO at 1680 (mask 001f)
[    0.095605] pci 0000:00:1f.1: [8086:2850] type 00 class 0x01018a
[    0.095644] pci 0000:00:1f.1: reg 10: [io  0x0000-0x0007]
[    0.095672] pci 0000:00:1f.1: reg 14: [io  0x0000-0x0003]
[    0.095697] pci 0000:00:1f.1: reg 18: [io  0x0000-0x0007]
[    0.095717] pci 0000:00:1f.1: reg 1c: [io  0x0000-0x0003]
[    0.095736] pci 0000:00:1f.1: reg 20: [io  0x1c00-0x1c0f]
[    0.095858] pci 0000:00:1f.2: [8086:2829] type 00 class 0x010601
[    0.095920] pci 0000:00:1f.2: reg 10: [io  0x1c50-0x1c57]
[    0.095946] pci 0000:00:1f.2: reg 14: [io  0x1c44-0x1c47]
[    0.095975] pci 0000:00:1f.2: reg 18: [io  0x1c48-0x1c4f]
[    0.096002] pci 0000:00:1f.2: reg 1c: [io  0x1c40-0x1c43]
[    0.096031] pci 0000:00:1f.2: reg 20: [io  0x1c20-0x1c3f]
[    0.096060] pci 0000:00:1f.2: reg 24: [mem 0xfe226000-0xfe2267ff]
[    0.096227] pci 0000:00:1f.2: PME# supported from D3hot
[    0.096285] pci 0000:00:1f.3: [8086:283e] type 00 class 0x0c0500
[    0.096325] pci 0000:00:1f.3: reg 10: [mem 0xfe227400-0xfe2274ff]
[    0.096422] pci 0000:00:1f.3: reg 20: [io  0x1c60-0x1c7f]
[    0.096643] pci 0000:00:1c.0: PCI bridge to [bus 02]
[    0.096651] pci 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    0.096659] pci 0000:00:1c.0:   bridge window [mem 0xfc000000-0xfdffffff]
[    0.096675] pci 0000:00:1c.0:   bridge window [mem 0xf8000000-0xf80fffff 64bit pref]
[    0.096881] pci 0000:03:00.0: [8086:4230] type 00 class 0x028000
[    0.096954] pci 0000:03:00.0: reg 10: [mem 0xdf3fe000-0xdf3fffff 64bit]
[    0.097187] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold
[    0.097331] pci 0000:00:1c.1: PCI bridge to [bus 03]
[    0.097341] pci 0000:00:1c.1:   bridge window [io  0x3000-0x3fff]
[    0.097351] pci 0000:00:1c.1:   bridge window [mem 0xdc000000-0xdf3fffff]
[    0.097369] pci 0000:00:1c.1:   bridge window [mem 0xdfe00000-0xdfefffff 64bit pref]
[    0.097515] pci 0000:00:1c.2: PCI bridge to [bus 04]
[    0.097525] pci 0000:00:1c.2:   bridge window [io  0x4000-0x4fff]
[    0.097535] pci 0000:00:1c.2:   bridge window [mem 0xd8000000-0xd9ffffff]
[    0.097553] pci 0000:00:1c.2:   bridge window [mem 0xdfb00000-0xdfbfffff 64bit pref]
[    0.097692] pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
[    0.097702] pci 0000:00:1c.3:   bridge window [io  0x5000-0x5fff]
[    0.097712] pci 0000:00:1c.3:   bridge window [mem 0xd4000000-0xd5ffffff]
[    0.097730] pci 0000:00:1c.3:   bridge window [mem 0xdf800000-0xdf8fffff 64bit pref]
[    0.097877] pci 0000:00:1c.4: PCI bridge to [bus 0d-14]
[    0.097887] pci 0000:00:1c.4:   bridge window [io  0x6000-0x6fff]
[    0.097897] pci 0000:00:1c.4:   bridge window [mem 0xd0000000-0xd1ffffff]
[    0.097912] pci 0000:00:1c.4:   bridge window [mem 0xdf500000-0xdf5fffff 64bit pref]
[    0.098016] pci 0000:15:00.0: [1180:0476] type 02 class 0x060700
[    0.098071] pci 0000:15:00.0: reg 10: [mem 0xf8300000-0xf8300fff]
[    0.098149] pci 0000:15:00.0: supports D1 D2
[    0.098152] pci 0000:15:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.098203] pci 0000:15:00.1: [1180:0832] type 00 class 0x0c0010
[    0.098254] pci 0000:15:00.1: reg 10: [mem 0xf8301000-0xf83017ff]
[    0.098474] pci 0000:15:00.1: supports D1 D2
[    0.098477] pci 0000:15:00.1: PME# supported from D0 D1 D2 D3hot D3cold
[    0.098645] pci 0000:00:1e.0: PCI bridge to [bus 15-18] (subtractive decode)
[    0.098655] pci 0000:00:1e.0:   bridge window [io  0x7000-0xafff]
[    0.098665] pci 0000:00:1e.0:   bridge window [mem 0xf8300000-0xfbffffff]
[    0.098683] pci 0000:00:1e.0:   bridge window [mem 0xf4000000-0xf7ffffff 64bit pref]
[    0.098686] pci 0000:00:1e.0:   bridge window [io  0x0000-0xffff] (subtractive decode)
[    0.098690] pci 0000:00:1e.0:   bridge window [mem 0x00000000-0xfffffffff] (subtractive decode)
[    0.098783] pci_bus 0000:16: busn_res: can not insert [bus 16-ff] under [bus 15-18] (conflicts with (null) [bus 15-18])
[    0.098792] pci_bus 0000:16: busn_res: [bus 16-ff] end is updated to 17
[    0.098899] ACPI: Invalid Power Resource to register!
[    0.098906] ACPI: Invalid Power Resource to register!
[    0.098915] ACPI: Invalid Power Resource to register!
[    0.098920] ACPI: Invalid Power Resource to register!
[    0.098923] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP0._PRT]
[    0.098959] ACPI: Invalid Power Resource to register!
[    0.098962] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP1._PRT]
[    0.098992] ACPI: Invalid Power Resource to register!
[    0.098995] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP2._PRT]
[    0.099030] ACPI: Invalid Power Resource to register!
[    0.099033] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP3._PRT]
[    0.099066] ACPI: Invalid Power Resource to register!
[    0.099069] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP4._PRT]
[    0.099102] ACPI: Invalid Power Resource to register!
[    0.099105] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCI1._PRT]
[    0.099147] ACPI: Invalid Power Resource to register!
[    0.099153] ACPI: Invalid Power Resource to register!
[    0.099158] ACPI: Invalid Power Resource to register!
[    0.099164] ACPI: Invalid Power Resource to register!
[    0.099174] ACPI: Invalid Power Resource to register!
[    0.099183] ACPI: Invalid Power Resource to register!
[    0.099200] ACPI: Invalid Power Resource to register!
[    0.105667] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 *10 11)
[    0.105747] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11)
[    0.105824] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 *11)
[    0.105901] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11)
[    0.105977] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11)
[    0.106058] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 *11)
[    0.106134] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 *11)
[    0.106214] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11)
[    0.107023] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[    0.107030] vgaarb: loaded
[    0.107032] vgaarb: bridge control possible 0000:00:02.0
[    0.107137] SCSI subsystem initialized
[    0.107140] ACPI: bus type scsi registered
[    0.107153] libata version 3.00 loaded.
[    0.107153] ACPI: bus type usb registered
[    0.107153] usbcore: registered new interface driver usbfs
[    0.107153] usbcore: registered new interface driver hub
[    0.107153] usbcore: registered new device driver usb
[    0.107153] PCI: Using ACPI for IRQ routing
[    0.109434] PCI: pci_cache_line_size set to 64 bytes
[    0.109562] e820: reserve RAM buffer [mem 0x0009d800-0x0009ffff]
[    0.109564] e820: reserve RAM buffer [mem 0x3e6b0000-0x3fffffff]
[    0.109684] NetLabel: Initializing
[    0.109686] NetLabel:  domain hash size = 128
[    0.109687] NetLabel:  protocols = UNLABELED CIPSOv4
[    0.109704] NetLabel:  unlabeled traffic allowed by default
[    0.109765] HPET: 3 timers in total, 0 timers will be used for per-cpu timer
[    0.109770] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
[    0.109776] hpet0: 3 comparators, 64-bit 14.318180 MHz counter
[    0.112015] Switching to clocksource hpet
[    0.121171] pnp: PnP ACPI init
[    0.121197] ACPI: bus type pnp registered
[    0.121775] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved
[    0.121780] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved
[    0.121783] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved
[    0.121787] system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved
[    0.121790] system 00:00: [mem 0x000cc000-0x000cffff] has been reserved
[    0.121793] system 00:00: [mem 0x000d0000-0x000d3fff] could not be reserved
[    0.121797] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved
[    0.121800] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved
[    0.121803] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved
[    0.121807] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved
[    0.121810] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved
[    0.121813] system 00:00: [mem 0x00100000-0x3effffff] could not be reserved
[    0.121817] system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved
[    0.121821] system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved
[    0.121827] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
[    0.121993] system 00:01: [io  0x164e-0x164f] has been reserved
[    0.121997] system 00:01: [io  0x1000-0x107f] has been reserved
[    0.122012] system 00:01: [io  0x1180-0x11bf] has been reserved
[    0.122016] system 00:01: [io  0x0800-0x080f] has been reserved
[    0.122019] system 00:01: [io  0x15e0-0x15ef] has been reserved
[    0.122022] system 00:01: [io  0x1600-0x165f] could not be reserved
[    0.122026] system 00:01: [mem 0xf0000000-0xf3ffffff] has been reserved
[    0.122029] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved
[    0.122033] system 00:01: [mem 0xfed14000-0xfed17fff] has been reserved
[    0.122036] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved
[    0.122040] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved
[    0.122044] system 00:01: [mem 0xfed45000-0xfed4bfff] has been reserved
[    0.122048] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.122118] pnp 00:02: Plug and Play ACPI device, IDs PNP0103 (active)
[    0.122131] pnp 00:03: [dma 4]
[    0.122155] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active)
[    0.122191] pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active)
[    0.122239] pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active)
[    0.122279] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.122317] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active)
[    0.122358] pnp 00:08: Plug and Play ACPI device, IDs IBM0057 PNP0f13 (active)
[    0.122810] pnp 00:09: Plug and Play ACPI device, IDs ATM1200 PNP0c31 (active)
[    0.123401] pnp: PnP ACPI: found 10 devices
[    0.123404] ACPI: ACPI bus type pnp unregistered
[    0.130917] pci 0000:00:1c.0: PCI bridge to [bus 02]
[    0.130923] pci 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    0.130931] pci 0000:00:1c.0:   bridge window [mem 0xfc000000-0xfdffffff]
[    0.130938] pci 0000:00:1c.0:   bridge window [mem 0xf8000000-0xf80fffff 64bit pref]
[    0.130948] pci 0000:00:1c.1: PCI bridge to [bus 03]
[    0.130952] pci 0000:00:1c.1:   bridge window [io  0x3000-0x3fff]
[    0.130960] pci 0000:00:1c.1:   bridge window [mem 0xdc000000-0xdf3fffff]
[    0.130966] pci 0000:00:1c.1:   bridge window [mem 0xdfe00000-0xdfefffff 64bit pref]
[    0.130975] pci 0000:00:1c.2: PCI bridge to [bus 04]
[    0.130979] pci 0000:00:1c.2:   bridge window [io  0x4000-0x4fff]
[    0.130987] pci 0000:00:1c.2:   bridge window [mem 0xd8000000-0xd9ffffff]
[    0.130993] pci 0000:00:1c.2:   bridge window [mem 0xdfb00000-0xdfbfffff 64bit pref]
[    0.131012] pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
[    0.131016] pci 0000:00:1c.3:   bridge window [io  0x5000-0x5fff]
[    0.131024] pci 0000:00:1c.3:   bridge window [mem 0xd4000000-0xd5ffffff]
[    0.131030] pci 0000:00:1c.3:   bridge window [mem 0xdf800000-0xdf8fffff 64bit pref]
[    0.131039] pci 0000:00:1c.4: PCI bridge to [bus 0d-14]
[    0.131044] pci 0000:00:1c.4:   bridge window [io  0x6000-0x6fff]
[    0.131051] pci 0000:00:1c.4:   bridge window [mem 0xd0000000-0xd1ffffff]
[    0.131057] pci 0000:00:1c.4:   bridge window [mem 0xdf500000-0xdf5fffff 64bit pref]
[    0.131069] pci 0000:15:00.0: res[15]=[mem 0x04000000-0x03ffffff pref] get_res_add_size add_size 4000000
[    0.131073] pci 0000:15:00.0: res[16]=[mem 0x04000000-0x03ffffff] get_res_add_size add_size 4000000
[    0.131076] pci 0000:15:00.0: res[13]=[io  0x0100-0x00ff] get_res_add_size add_size 100
[    0.131080] pci 0000:15:00.0: res[14]=[io  0x0100-0x00ff] get_res_add_size add_size 100
[    0.131086] pci 0000:15:00.0: BAR 15: assigned [mem 0xf4000000-0xf7ffffff pref]
[    0.131090] pci 0000:15:00.0: BAR 16: assigned [mem 0x40000000-0x43ffffff]
[    0.131094] pci 0000:15:00.0: BAR 13: assigned [io  0x7000-0x70ff]
[    0.131097] pci 0000:15:00.0: BAR 14: assigned [io  0x7400-0x74ff]
[    0.131100] pci 0000:15:00.0: CardBus bridge to [bus 16-17]
[    0.131103] pci 0000:15:00.0:   bridge window [io  0x7000-0x70ff]
[    0.131110] pci 0000:15:00.0:   bridge window [io  0x7400-0x74ff]
[    0.131116] pci 0000:15:00.0:   bridge window [mem 0xf4000000-0xf7ffffff pref]
[    0.131123] pci 0000:15:00.0:   bridge window [mem 0x40000000-0x43ffffff]
[    0.131131] pci 0000:00:1e.0: PCI bridge to [bus 15-18]
[    0.131135] pci 0000:00:1e.0:   bridge window [io  0x7000-0xafff]
[    0.131142] pci 0000:00:1e.0:   bridge window [mem 0xf8300000-0xfbffffff]
[    0.131149] pci 0000:00:1e.0:   bridge window [mem 0xf4000000-0xf7ffffff 64bit pref]
[    0.131210] pci 0000:00:1e.0: enabling device (0005 -> 0007)
[    0.131217] pci 0000:00:1e.0: setting latency timer to 64
[    0.131237] pci 0000:15:00.0: setting latency timer to 64
[    0.131243] pci_bus 0000:00: resource 4 [io  0x0000-0xffff]
[    0.131246] pci_bus 0000:00: resource 5 [mem 0x00000000-0xfffffffff]
[    0.131249] pci_bus 0000:02: resource 0 [io  0x2000-0x2fff]
[    0.131252] pci_bus 0000:02: resource 1 [mem 0xfc000000-0xfdffffff]
[    0.131255] pci_bus 0000:02: resource 2 [mem 0xf8000000-0xf80fffff 64bit pref]
[    0.131258] pci_bus 0000:03: resource 0 [io  0x3000-0x3fff]
[    0.131261] pci_bus 0000:03: resource 1 [mem 0xdc000000-0xdf3fffff]
[    0.131263] pci_bus 0000:03: resource 2 [mem 0xdfe00000-0xdfefffff 64bit pref]
[    0.131266] pci_bus 0000:04: resource 0 [io  0x4000-0x4fff]
[    0.131269] pci_bus 0000:04: resource 1 [mem 0xd8000000-0xd9ffffff]
[    0.131272] pci_bus 0000:04: resource 2 [mem 0xdfb00000-0xdfbfffff 64bit pref]
[    0.131275] pci_bus 0000:05: resource 0 [io  0x5000-0x5fff]
[    0.131278] pci_bus 0000:05: resource 1 [mem 0xd4000000-0xd5ffffff]
[    0.131280] pci_bus 0000:05: resource 2 [mem 0xdf800000-0xdf8fffff 64bit pref]
[    0.131283] pci_bus 0000:0d: resource 0 [io  0x6000-0x6fff]
[    0.131286] pci_bus 0000:0d: resource 1 [mem 0xd0000000-0xd1ffffff]
[    0.131289] pci_bus 0000:0d: resource 2 [mem 0xdf500000-0xdf5fffff 64bit pref]
[    0.131292] pci_bus 0000:15: resource 0 [io  0x7000-0xafff]
[    0.131294] pci_bus 0000:15: resource 1 [mem 0xf8300000-0xfbffffff]
[    0.131297] pci_bus 0000:15: resource 2 [mem 0xf4000000-0xf7ffffff 64bit pref]
[    0.131300] pci_bus 0000:15: resource 4 [io  0x0000-0xffff]
[    0.131303] pci_bus 0000:15: resource 5 [mem 0x00000000-0xfffffffff]
[    0.131306] pci_bus 0000:16: resource 0 [io  0x7000-0x70ff]
[    0.131308] pci_bus 0000:16: resource 1 [io  0x7400-0x74ff]
[    0.131311] pci_bus 0000:16: resource 2 [mem 0xf4000000-0xf7ffffff pref]
[    0.131314] pci_bus 0000:16: resource 3 [mem 0x40000000-0x43ffffff]
[    0.131363] NET: Registered protocol family 2
[    0.131564] TCP established hash table entries: 8192 (order: 5, 131072 bytes)
[    0.131649] TCP bind hash table entries: 8192 (order: 5, 131072 bytes)
[    0.131721] TCP: Hash tables configured (established 8192 bind 8192)
[    0.131800] TCP: reno registered
[    0.131806] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.131817] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.131886] NET: Registered protocol family 1
[    0.131900] pci 0000:00:02.0: Boot video device
[    0.131950] pci 0000:00:1a.1: power state changed by ACPI to D0
[    0.132039] pci 0000:00:1d.0: power state changed by ACPI to D0
[    0.132097] pci 0000:00:1d.2: power state changed by ACPI to D0
[    0.132183] PCI: CLS 64 bytes, default 64
[    0.132232] Unpacking initramfs...
[    3.776116] Freeing initrd memory: 136144k freed
[    3.886694] Simple Boot Flag at 0x35 set to 0x1
[    3.887507] audit: initializing netlink socket (disabled)
[    3.887525] type=2000 audit(1355702844.886:1): initialized
[    3.918036] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[    3.919994] VFS: Disk quotas dquot_6.5.2
[    3.920062] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    3.920620] msgmni has been set to 1933
[    3.920698] SELinux:  Registering netfilter hooks
[    3.921276] alg: No test for stdrng (krng)
[    3.921285] NET: Registered protocol family 38
[    3.921333] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
[    3.921370] io scheduler noop registered
[    3.921373] io scheduler deadline registered
[    3.921385] io scheduler cfq registered (default)
[    3.921590] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X
[    3.921776] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X
[    3.921960] pcieport 0000:00:1c.2: irq 42 for MSI/MSI-X
[    3.922159] pcieport 0000:00:1c.3: irq 43 for MSI/MSI-X
[    3.922339] pcieport 0000:00:1c.4: irq 44 for MSI/MSI-X
[    3.922504] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt
[    3.922511] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded
[    3.922536] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt
[    3.922539] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt
[    3.922546] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded
[    3.922570] pcieport 0000:00:1c.2: Signaling PME through PCIe PME interrupt
[    3.922576] pcie_pme 0000:00:1c.2:pcie01: service driver pcie_pme loaded
[    3.922604] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt
[    3.922611] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded
[    3.922635] pcieport 0000:00:1c.4: Signaling PME through PCIe PME interrupt
[    3.922641] pcie_pme 0000:00:1c.4:pcie01: service driver pcie_pme loaded
[    3.922660] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[    3.922738] pciehp: Using ACPI for slot detection.
[    3.922779] pciehp 0000:00:1c.3:pcie04: HPC vendor_id 8086 device_id 2845 ss_vid 17aa ss_did 20ad
[    3.922803] pciehp 0000:00:1c.3:pcie04: service driver pciehp loaded
[    3.922817] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
[    3.922819] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[    3.923277] intel_idle: does not run on family 6 model 15
[    3.923586] ACPI: AC Adapter [AC] (on-line)
[    3.923689] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0
[    3.923879] ACPI: Lid Switch [LID]
[    3.923982] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1
[    3.923987] ACPI: Sleep Button [SLPB]
[    3.924057] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
[    3.924061] ACPI: Power Button [PWRF]
[    3.924279] ACPI: Requesting acpi_cpufreq
[    3.927738] Monitor-Mwait will be used to enter C-1 state
[    3.927753] Monitor-Mwait will be used to enter C-2 state
[    3.927766] Monitor-Mwait will be used to enter C-3 state
[    3.927788] ACPI: acpi_idle registered with cpuidle
[    3.934775] thermal LNXTHERM:00: registered as thermal_zone0
[    3.934778] ACPI: Thermal Zone [THM0] (53 C)
[    3.936128] thermal LNXTHERM:01: registered as thermal_zone1
[    3.936131] ACPI: Thermal Zone [THM1] (53 C)
[    3.936168] GHES: HEST is not enabled!
[    3.936304] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    3.957253] 0000:00:03.3: ttyS0 at I/O 0x1830 (irq = 17) is a 16550A
[    3.957652] Non-volatile memory driver v1.3
[    3.957655] Linux agpgart interface v0.103
[    3.957801] agpgart-intel 0000:00:00.0: Intel 965GM Chipset
[    3.957915] agpgart-intel 0000:00:00.0: detected gtt size: 524288K total, 262144K mappable
[    3.958543] agpgart-intel 0000:00:00.0: detected 8192K stolen memory
[    3.958865] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xe0000000
[    3.960376] loop: module loaded
[    3.960496] ahci 0000:00:1f.2: version 3.0
[    3.960602] ahci 0000:00:1f.2: irq 45 for MSI/MSI-X
[    3.960684] ahci 0000:00:1f.2: AHCI 0001.0100 32 slots 3 ports 1.5 Gbps 0x1 impl SATA mode
[    3.960689] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ccc 
[    3.960696] ahci 0000:00:1f.2: setting latency timer to 64
[    3.961239] scsi0 : ahci
[    3.961365] scsi1 : ahci
[    3.961509] scsi2 : ahci
[    3.961598] ata1: SATA max UDMA/133 abar m2048@0xfe226000 port 0xfe226100 irq 45
[    3.961600] ata2: DUMMY
[    3.961602] ata3: DUMMY
[    3.961641] ata_piix 0000:00:1f.1: version 2.13
[    3.961728] ata_piix 0000:00:1f.1: setting latency timer to 64
[    3.962173] scsi3 : ata_piix
[    3.962571] scsi4 : ata_piix
[    3.962635] ata4: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x1c00 irq 14
[    3.962638] ata5: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x1c08 irq 15
[    3.962706] libphy: Fixed MDIO Bus: probed
[    3.962777] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.962779] ehci-pci: EHCI PCI platform driver
[    3.962855] ehci-pci 0000:00:1a.7: setting latency timer to 64
[    3.962859] ehci-pci 0000:00:1a.7: EHCI Host Controller
[    3.963088] ehci-pci 0000:00:1a.7: new USB bus registered, assigned bus number 1
[    3.963092] ata5: port disabled--ignoring
[    3.967051] ehci-pci 0000:00:1a.7: debug port 1
[    3.967061] ehci-pci 0000:00:1a.7: cache line size of 64 is not supported
[    3.967082] ehci-pci 0000:00:1a.7: irq 22, io mem 0xfe226c00
[    3.969871] ACPI: Battery Slot [BAT0] (battery present)
[    3.973022] ehci-pci 0000:00:1a.7: USB 2.0 started, EHCI 1.00
[    3.973065] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    3.973068] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.973071] usb usb1: Product: EHCI Host Controller
[    3.973074] usb usb1: Manufacturer: Linux 3.7.0+ ehci_hcd
[    3.973077] usb usb1: SerialNumber: 0000:00:1a.7
[    3.973221] hub 1-0:1.0: USB hub found
[    3.973227] hub 1-0:1.0: 4 ports detected
[    3.973406] ehci-pci 0000:00:1d.7: setting latency timer to 64
[    3.973411] ehci-pci 0000:00:1d.7: EHCI Host Controller
[    3.973464] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 2
[    3.977393] ehci-pci 0000:00:1d.7: debug port 1
[    3.977402] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported
[    3.977419] ehci-pci 0000:00:1d.7: irq 19, io mem 0xfe227000
[    3.983023] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00
[    3.983040] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
[    3.983043] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.983046] usb usb2: Product: EHCI Host Controller
[    3.983049] usb usb2: Manufacturer: Linux 3.7.0+ ehci_hcd
[    3.983052] usb usb2: SerialNumber: 0000:00:1d.7
[    3.983184] hub 2-0:1.0: USB hub found
[    3.983189] hub 2-0:1.0: 6 ports detected
[    3.983389] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    3.983403] uhci_hcd: USB Universal Host Controller Interface driver
[    3.983436] uhci_hcd 0000:00:1a.0: setting latency timer to 64
[    3.983440] uhci_hcd 0000:00:1a.0: UHCI Host Controller
[    3.983496] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3
[    3.983535] uhci_hcd 0000:00:1a.0: irq 20, io base 0x00001860
[    3.983574] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
[    3.983578] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.983581] usb usb3: Product: UHCI Host Controller
[    3.983583] usb usb3: Manufacturer: Linux 3.7.0+ uhci_hcd
[    3.983586] usb usb3: SerialNumber: 0000:00:1a.0
[    3.983697] hub 3-0:1.0: USB hub found
[    3.983702] hub 3-0:1.0: 2 ports detected
[    3.983799] uhci_hcd 0000:00:1a.1: setting latency timer to 64
[    3.983804] uhci_hcd 0000:00:1a.1: UHCI Host Controller
[    3.983851] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4
[    3.983889] uhci_hcd 0000:00:1a.1: irq 21, io base 0x00001880
[    3.983930] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
[    3.983933] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.983936] usb usb4: Product: UHCI Host Controller
[    3.983939] usb usb4: Manufacturer: Linux 3.7.0+ uhci_hcd
[    3.983942] usb usb4: SerialNumber: 0000:00:1a.1
[    3.984073] hub 4-0:1.0: USB hub found
[    3.984078] hub 4-0:1.0: 2 ports detected
[    3.984204] uhci_hcd 0000:00:1d.0: setting latency timer to 64
[    3.984209] uhci_hcd 0000:00:1d.0: UHCI Host Controller
[    3.984258] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 5
[    3.984299] uhci_hcd 0000:00:1d.0: irq 16, io base 0x000018a0
[    3.984340] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
[    3.984343] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.984346] usb usb5: Product: UHCI Host Controller
[    3.984349] usb usb5: Manufacturer: Linux 3.7.0+ uhci_hcd
[    3.984352] usb usb5: SerialNumber: 0000:00:1d.0
[    3.984455] hub 5-0:1.0: USB hub found
[    3.984460] hub 5-0:1.0: 2 ports detected
[    3.984554] uhci_hcd 0000:00:1d.1: setting latency timer to 64
[    3.984559] uhci_hcd 0000:00:1d.1: UHCI Host Controller
[    3.984614] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 6
[    3.984652] uhci_hcd 0000:00:1d.1: irq 17, io base 0x000018c0
[    3.984696] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
[    3.984700] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.984703] usb usb6: Product: UHCI Host Controller
[    3.984706] usb usb6: Manufacturer: Linux 3.7.0+ uhci_hcd
[    3.984708] usb usb6: SerialNumber: 0000:00:1d.1
[    3.984829] hub 6-0:1.0: USB hub found
[    3.984834] hub 6-0:1.0: 2 ports detected
[    3.984955] uhci_hcd 0000:00:1d.2: setting latency timer to 64
[    3.984959] uhci_hcd 0000:00:1d.2: UHCI Host Controller
[    3.985021] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 7
[    3.985063] uhci_hcd 0000:00:1d.2: irq 18, io base 0x000018e0
[    3.985102] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
[    3.985105] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.985108] usb usb7: Product: UHCI Host Controller
[    3.985111] usb usb7: Manufacturer: Linux 3.7.0+ uhci_hcd
[    3.985114] usb usb7: SerialNumber: 0000:00:1d.2
[    3.985226] hub 7-0:1.0: USB hub found
[    3.985231] hub 7-0:1.0: 2 ports detected
[    3.985383] usbcore: registered new interface driver usbserial
[    3.985397] usbcore: registered new interface driver usbserial_generic
[    3.985406] usbserial: USB Serial support registered for generic
[    3.985455] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
[    3.992417] serio: i8042 KBD port at 0x60,0x64 irq 1
[    3.992424] serio: i8042 AUX port at 0x60,0x64 irq 12
[    3.992534] mousedev: PS/2 mouse device common for all mice
[    3.992770] rtc_cmos 00:06: RTC can wake from S4
[    3.992960] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0
[    3.992994] rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
[    3.993128] device-mapper: uevent: version 1.0.3
[    3.993219] device-mapper: ioctl: 4.23.0-ioctl (2012-07-25) initialised: dm-devel@redhat.com
[    3.993356] cpuidle: using governor ladder
[    3.993417] cpuidle: using governor menu
[    3.993793] EFI Variables Facility v0.08 2004-May-17
[    3.993931] usbcore: registered new interface driver usbhid
[    3.993933] usbhid: USB HID core driver
[    3.993961] drop_monitor: Initializing network drop monitor service
[    3.994079] ip_tables: (C) 2000-2006 Netfilter Core Team
[    3.994123] TCP: cubic registered
[    3.994125] Initializing XFRM netlink socket
[    3.994264] NET: Registered protocol family 10
[    3.994469] mip6: Mobile IPv6
[    3.994472] NET: Registered protocol family 17
[    3.994485] Key type dns_resolver registered
[    3.994847] PM: Hibernation image not present or could not be loaded.
[    3.994859] registered taskstats version 1
[    3.995527]   Magic number: 8:375:102
[    3.995681] rtc_cmos 00:06: setting system clock to 2012-12-17 00:07:25 UTC (1355702845)
[    3.997932] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3
[    4.117710] ata4.00: ATAPI: HL-DT-STCD-RW/DVD DRIVE GCC-4247N, 1.02, max UDMA/33
[    4.123561] ata4.00: configured for UDMA/33
[    4.471094] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[    4.472573] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded
[    4.472584] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
[    4.472860] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded
[    4.472869] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
[    4.474029] ata1.00: ATA-7: HTS721010G9SA00, MCZIC14V, max UDMA/100
[    4.474036] ata1.00: 195371568 sectors, multi 16: LBA48 
[    4.476039] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded
[    4.476048] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
[    4.476322] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded
[    4.476330] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
[    4.477487] ata1.00: configured for UDMA/100
[    4.477818] scsi 0:0:0:0: Direct-Access     ATA      HTS721010G9SA00  MCZI PQ: 0 ANSI: 5
[    4.478246] sd 0:0:0:0: [sda] 195371568 512-byte logical blocks: (100 GB/93.1 GiB)
[    4.478250] sd 0:0:0:0: Attached scsi generic sg0 type 0
[    4.478421] sd 0:0:0:0: [sda] Write Protect is off
[    4.478429] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    4.478443] ACPI: Invalid Power Resource to register!
[    4.478696] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    4.482920] scsi 3:0:0:0: CD-ROM            HL-DT-ST RW/DVD GCC-4247N 1.02 PQ: 0 ANSI: 5
[    4.488510] sr0: scsi3-mmc drive: 24x/24x writer cd/rw xa/form2 cdda tray
[    4.488513] cdrom: Uniform CD-ROM driver Revision: 3.20
[    4.488659] sr 3:0:0:0: Attached scsi CD-ROM sr0
[    4.488824] sr 3:0:0:0: Attached scsi generic sg1 type 5
[    4.489058] ACPI: Invalid Power Resource to register!
[    4.499071] usb 3-1: new full-speed USB device number 2 using uhci_hcd
[    4.650142] usb 3-1: New USB device found, idVendor=0a5c, idProduct=2110
[    4.650146] usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[    4.650149] usb 3-1: Product: BCM2045B
[    4.650152] usb 3-1: Manufacturer: Broadcom Corp
[    4.721640] psmouse serio1: synaptics: Touchpad model: 1, fw: 6.2, id: 0x81a0b1, caps: 0xa04793/0x300000/0x0, board id: 71, fw id: 67352
[    4.721647] psmouse serio1: synaptics: serio: Synaptics pass-through port at isa0060/serio1/input0
[    4.763596] input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input4
[    4.828343]  sda: sda1 sda2 sda3
[    4.828954] sd 0:0:0:0: [sda] Attached SCSI disk
[    4.830859] Freeing unused kernel memory: 1060k freed
[    4.831253] Write protecting the kernel read-only data: 12288k
[    4.841463] Freeing unused kernel memory: 1852k freed
[    4.853124] Freeing unused kernel memory: 1392k freed
[    4.953131] dracut: dracut-018-35.git20120510.fc17
[    5.019810] dracut: rd.luks=0: removing cryptoluks activation
[    5.040199] udevd[110]: starting version 182
[    5.081647] [drm] Initialized drm 1.1.0 20060810
[    5.121693] i915 0000:00:02.0: setting latency timer to 64
[    5.161703] i915 0000:00:02.0: irq 46 for MSI/MSI-X
[    5.161716] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[    5.161718] [drm] Driver supports precise vblank timestamp query.
[    5.161772] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    5.289557] [drm] initialized overlay support
[    5.325892] fbcon: inteldrmfb (fb0) is primary device
[    5.873872] Console: switching to colour frame buffer device 180x56
[    5.883115] fb0: inteldrmfb frame buffer device
[    5.883119] drm: registered panic notifier
[    5.891680] acpi device:02: registered as cooling_device2
[    5.891803] ACPI: Video Device [VID] (multi-head: yes  rom: no  post: no)
[    5.891930] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input5
[    5.892175] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
[    5.906278] dracut: Starting plymouth daemon
[    6.091457] dracut: rd.dm=0: removing DM RAID activation
[    6.109877] dracut: rd.md=0: removing MD RAID activation
[    6.200840] pata_acpi 0000:00:03.2: enabling device (0004 -> 0005)
[    6.200885] pata_acpi 0000:00:03.2: setting latency timer to 64
[    6.201554] ata_generic 0000:00:03.2: setting latency timer to 64
[    6.202071] scsi5 : ata_generic
[    6.202168] scsi6 : ata_generic
[    6.202217] ata6: PATA max UDMA/100 cmd 0x1828 ctl 0x180c bmdma 0x1810 irq 18
[    6.202220] ata7: PATA max UDMA/100 cmd 0x1820 ctl 0x1808 bmdma 0x1818 irq 18
[    6.212000] yenta_cardbus 0000:15:00.0: CardBus bridge found [17aa:20c6]
[    6.648933] yenta_cardbus 0000:15:00.0: ISA IRQ mask 0x0cb8, PCI irq 16
[    6.648945] yenta_cardbus 0000:15:00.0: Socket status: 30000006
[    6.648960] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [io  0x7000-0xafff]
[    6.648969] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf8300000-0xfbffffff]
[    6.648977] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf8300000-0xfbffffff:
[    6.648987]  excluding 0xf8300000-0xf86cffff
[    6.649056] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf4000000-0xf7ffffff 64bit pref]
[    6.649065] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf4000000-0xf7ffffff:
[    6.649092]  excluding 0xf4000000-0xf7ffffff
[    6.649869] firewire_ohci 0000:15:00.1: setting latency timer to 64
[    6.703147] firewire_ohci 0000:15:00.1: added OHCI v1.10 device as card 0, 4 IR + 4 IT contexts, quirks 0x11
[    6.757351] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null)
[    6.852603] dracut: Checking ext4: /dev/disk/by-uuid/94addf6f-dd82-48fd-bb1b-809567e7a9a4
[    6.852794] dracut: issuing e2fsck -a  /dev/disk/by-uuid/94addf6f-dd82-48fd-bb1b-809567e7a9a4
[    7.034837] dracut: /dev/disk/by-uuid/94addf6f-dd82-48fd-bb1b-809567e7a9a4: clean, 178875/2564096 files, 1835864/10240000 blocks
[    7.035505] dracut: Remounting /dev/disk/by-uuid/94addf6f-dd82-48fd-bb1b-809567e7a9a4 with -o ro
[    7.044698] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null)
[    7.081228] dracut: Mounted root filesystem /dev/sda3
[    7.204214] firewire_core 0000:15:00.1: created device fw0: GUID 00016c200015db17, S400
[    7.257511] dracut: Switching root
[    7.864883] type=1404 audit(1355702849.367:2): enforcing=1 old_enforcing=0 auid=4294967295 ses=4294967295
[    8.129909] SELinux: 2048 avtab hash slots, 99000 rules.
[    8.151926] SELinux: 2048 avtab hash slots, 99000 rules.
[    8.347196] SELinux:  9 users, 15 roles, 4112 types, 222 bools, 1 sens, 1024 cats
[    8.347202] SELinux:  83 classes, 99000 rules
[    8.352650] SELinux:  Permission wake_alarm in class capability2 not defined in policy.
[    8.352655] SELinux:  Permission block_suspend in class capability2 not defined in policy.
[    8.352661] SELinux: the above unknown classes and permissions will be allowed
[    8.352671] SELinux:  Completing initialization.
[    8.352673] SELinux:  Setting up existing superblocks.
[    8.352684] SELinux: initialized (dev sysfs, type sysfs), uses genfs_contexts
[    8.352691] SELinux: initialized (dev rootfs, type rootfs), uses genfs_contexts
[    8.352713] SELinux: initialized (dev bdev, type bdev), uses genfs_contexts
[    8.352720] SELinux: initialized (dev proc, type proc), uses genfs_contexts
[    8.352733] SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
[    8.352762] SELinux: initialized (dev devtmpfs, type devtmpfs), uses transition SIDs
[    8.353394] SELinux: initialized (dev sockfs, type sockfs), uses task SIDs
[    8.353400] SELinux: initialized (dev debugfs, type debugfs), uses genfs_contexts
[    8.355833] SELinux: initialized (dev pipefs, type pipefs), uses task SIDs
[    8.355845] SELinux: initialized (dev anon_inodefs, type anon_inodefs), uses genfs_contexts
[    8.355850] SELinux: initialized (dev devpts, type devpts), uses transition SIDs
[    8.355873] SELinux: initialized (dev hugetlbfs, type hugetlbfs), uses transition SIDs
[    8.355881] SELinux: initialized (dev mqueue, type mqueue), uses transition SIDs
[    8.355889] SELinux: initialized (dev selinuxfs, type selinuxfs), uses genfs_contexts
[    8.355918] SELinux: initialized (dev sysfs, type sysfs), uses genfs_contexts
[    8.357078] SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
[    8.357088] SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
[    8.357122] SELinux: initialized (dev sda3, type ext4), uses xattr
[    8.377222] type=1403 audit(1355702849.880:3): policy loaded auid=4294967295 ses=4294967295
[    8.527576] SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
[    8.533098] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    8.638104] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    8.643095] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    8.648093] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    8.653109] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    8.658126] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    8.663175] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    8.668171] SELinux: initialized (dev cgroup, type cgroup), uses genfs_contexts
[    9.283536] SELinux: initialized (dev autofs, type autofs), uses genfs_contexts
[   10.471789] psmouse serio2: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3
[   10.532517] udevd[287]: starting version 182
[   10.693648] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/serio2/input/input6
[   10.904555] SELinux: initialized (dev securityfs, type securityfs), uses genfs_contexts
[   10.904614] SELinux: initialized (dev hugetlbfs, type hugetlbfs), uses transition SIDs
[   10.904981] SELinux: initialized (dev configfs, type configfs), uses genfs_contexts
[   10.905369] SELinux: initialized (dev tmpfs, type tmpfs), uses transition SIDs
[   11.849162] EXT4-fs (sda3): re-mounted. Opts: (null)
[   15.284936] microcode: CPU0 sig=0x6fd, pf=0x80, revision=0xa4
[   15.450333] input: PC Speaker as /devices/platform/pcspkr/input/input7
[   15.472549] tpm_tis 00:09: 1.2 TPM (device-id 0x3203, rev-id 9)
[   16.381198] tpm_tis 00:09: TPM is disabled/deactivated (0x6)
[   16.643653] ACPI Warning: 0x0000000000001028-0x000000000000102f SystemIO conflicts with Region \_SB_.PCI0.LPC_.PMIO 1 (20121018/utaddress-251)
[   16.643663] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
[   16.643668] ACPI Warning: 0x00000000000011b0-0x00000000000011bf SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20121018/utaddress-251)
[   16.643673] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
[   16.643675] ACPI Warning: 0x0000000000001180-0x00000000000011af SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20121018/utaddress-251)
[   16.643680] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
[   16.643682] lpc_ich: Resource conflict(s) found affecting gpio_ich
[   16.673822] iTCO_vendor_support: vendor-support=0
[   16.687593] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.10
[   16.687636] iTCO_wdt: Found a ICH8M-E TCO device (Version=2, TCOBASE=0x1060)
[   16.688002] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[   16.712205] i801_smbus 0000:00:1f.3: SMBus using PCI Interrupt
[   17.179774] microcode: CPU1 sig=0x6fd, pf=0x80, revision=0xa4
[   17.179952] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[   17.390317] cfg80211: Calling CRDA to update world regulatory domain
[   17.906450] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff:
[   17.906460]  excluding 0xc0000-0xd3fff 0xe0000-0xfffff
[   17.906527] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff:
[   17.906542]  clean.
[   17.906603] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff:
[   17.906618]  clean.
[   18.013936] cfg80211: World regulatory domain updated:
[   18.013940] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[   18.013943] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   18.013946] cfg80211:   (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[   18.013948] cfg80211:   (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[   18.013950] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   18.013953] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   18.113283] thinkpad_acpi: ThinkPad ACPI Extras v0.24
[   18.113293] thinkpad_acpi: http://ibm-acpi.sf.net/
[   18.113295] thinkpad_acpi: ThinkPad BIOS 7LET37WW (1.07 ), EC 7KHT21WW-1.05
[   18.113297] thinkpad_acpi: Lenovo ThinkPad T61, model 7658CTO
[   18.113732] thinkpad_acpi: detected a 8-level brightness capable ThinkPad
[   18.115191] thinkpad_acpi: ACPI backlight control delay disabled
[   18.115343] thinkpad_acpi: radio switch found; radios are enabled
[   18.115358] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver
[   18.115360] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default...
[   18.118221] thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is unblocked
[   18.121048] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one
[   18.121191] thinkpad_acpi: Console audio control enabled, mode: monitor (read only)
[   18.122364] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input8
[   18.914204] e1000e: Intel(R) PRO/1000 Network Driver - 2.1.4-k
[   18.914208] e1000e: Copyright(c) 1999 - 2012 Intel Corporation.
[   18.914260] e1000e 0000:00:19.0: setting latency timer to 64
[   18.914352] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
[   18.914413] e1000e 0000:00:19.0: irq 47 for MSI/MSI-X
[   19.219682] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:15:58:84:69:ea
[   19.219688] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection
[   19.219720] e1000e 0000:00:19.0 eth0: MAC: 6, PHY: 6, PBA No: FFFFFF-0FF
[   19.788800] hda_intel: probe_mask set to 0x1 for device 17aa:20ac
[   19.788890] snd_hda_intel 0000:00:1b.0: irq 48 for MSI/MSI-X
[   19.955811] Adding 5119996k swap on /dev/sda2.  Priority:0 extents:1 across:5119996k 
[   21.013483] Bluetooth: Core ver 2.16
[   21.013523] NET: Registered protocol family 31
[   21.013525] Bluetooth: HCI device and connection manager initialized
[   21.013632] Bluetooth: HCI socket layer initialized
[   21.013637] Bluetooth: L2CAP socket layer initialized
[   21.013647] Bluetooth: SCO socket layer initialized
[   21.769159] usbcore: registered new interface driver btusb
[   22.283711] iwl4965: Intel(R) Wireless WiFi 4965 driver for Linux, in-tree:d
[   22.283716] iwl4965: Copyright(c) 2003-2011 Intel Corporation
[   22.283857] iwl4965 0000:03:00.0: Detected Intel(R) Wireless WiFi Link 4965AGN, REV=0x4
[   22.322885] iwl4965 0000:03:00.0: device EEPROM VER=0x36, CALIB=0x5
[   22.322934] iwl4965 0000:03:00.0: Tunable channels: 11 802.11bg, 13 802.11a channels
[   22.323047] iwl4965 0000:03:00.0: irq 49 for MSI/MSI-X
[   22.469150] iwl4965 0000:03:00.0: loaded firmware version 228.61.2.24
[   22.500392] ieee80211 phy0: Selected rate control algorithm 'iwl-4965-rs'
[   22.597535] cfg80211: Calling CRDA for country: US
[   22.600837] cfg80211: Regulatory domain changed to country: US
[   22.600841] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[   22.600843] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2700 mBm)
[   22.600846] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 1700 mBm)
[   22.600848] cfg80211:   (5250000 KHz - 5330000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   22.600850] cfg80211:   (5490000 KHz - 5600000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   22.600853] cfg80211:   (5650000 KHz - 5710000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   22.600855] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 3000 mBm)
[   25.519948] ip6_tables: (C) 2000-2006 Netfilter Core Team
[   26.679066] nf_conntrack version 0.5.0 (7765 buckets, 31060 max)
[   28.953233] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[   28.953238] Bluetooth: BNEP filters: protocol multicast
[   28.953257] Bluetooth: BNEP socket layer initialized
[   29.398776] Bluetooth: RFCOMM TTY layer initialized
[   29.398800] Bluetooth: RFCOMM socket layer initialized
[   29.398801] Bluetooth: RFCOMM ver 1.11
[   30.116269] e1000e 0000:00:19.0: irq 47 for MSI/MSI-X
[   30.217148] e1000e 0000:00:19.0: irq 47 for MSI/MSI-X
[   30.217324] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   30.459567] IPv6: ADDRCONF(NETDEV_UP): wlan0: link is not ready
[   33.866700] wlan0: authenticate with 00:19:92:07:18:81
[   33.884351] wlan0: send auth to 00:19:92:07:18:81 (try 1/3)
[   33.886083] wlan0: authenticated
[   33.886280] wlan0: associating with AP with corrupt beacon
[   33.887053] wlan0: associate with 00:19:92:07:18:81 (try 1/3)
[   33.891592] wlan0: RX AssocResp from 00:19:92:07:18:81 (capab=0x421 status=0 aid=22)
[   33.919837] wlan0: associated
[   33.919921] IPv6: ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
[   40.021072] fuse init (API version 7.20)
[   40.046805] SELinux: initialized (dev fusectl, type fusectl), uses genfs_contexts
[   40.056854] SELinux: initialized (dev fuse, type fuse), uses genfs_contexts
[   62.217458] RPC: Registered named UNIX socket transport module.
[   62.217463] RPC: Registered udp transport module.
[   62.217464] RPC: Registered tcp transport module.
[   62.217466] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   79.222888] wlan0: deauthenticating from 00:19:92:07:18:81 by local choice (reason=3)
[   79.245447] cfg80211: Calling CRDA to update world regulatory domain
[   79.257278] cfg80211: World regulatory domain updated:
[   79.257284] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[   79.257287] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   79.257290] cfg80211:   (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[   79.257293] cfg80211:   (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[   79.257295] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   79.257298] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   79.257321] cfg80211: Calling CRDA for country: US
[   79.261770] cfg80211: Regulatory domain changed to country: US
[   79.261775] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[   79.261778] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2700 mBm)
[   79.261780] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 1700 mBm)
[   79.261783] cfg80211:   (5250000 KHz - 5330000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   79.261786] cfg80211:   (5490000 KHz - 5600000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   79.261788] cfg80211:   (5650000 KHz - 5710000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[   79.261791] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 3000 mBm)

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yinghai Lu]

On Sun, Dec 16, 2012 at 3:59 PM, Yu, Fenghua <fenghua.yu@intel.com> wrote:
>
>> it has to be rebased after #PF handler version. otherwise it can not
>> handle for framdisk
>> that is loaded after 1G.
>>
>> Fenghua,
>>
>> can you post your boot log with 64bit with your patch?
>>
>> Yinghai
>
> Attached is dmesg with the patches.
>

yes, your laptop only have 1G ram, and

[    0.000000] e820: BIOS-provided physical RAM map:
[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009d7ff] usable
[    0.000000] BIOS-e820: [mem 0x000000000009d800-0x000000000009ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000000d2000-0x00000000000d3fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000003e6affff] usable
[    0.000000] BIOS-e820: [mem 0x000000003e6b0000-0x000000003e6ccfff] ACPI data
[    0.000000] BIOS-e820: [mem 0x000000003e6cd000-0x000000003e6fffff] ACPI NVS
[    0.000000] BIOS-e820: [mem 0x000000003e700000-0x000000003effffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed14000-0x00000000fed19fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved

ramdisk is at
     RAMDISK: [mem 0x27608000-0x2fafbfff]

and current kernel default set 1G to kernel mapping. so it happens to
work with your patchset.

please find one sytem with 4G or more to test it.

and you may need to rebase your patches on top of my for-x86-boot
branch with working
#PF handler set page table patch.

git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-yinghai.git
for-x86-boot

Thanks

Yinghai

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yinghai Lu]

[-- Attachment #1: Type: text/plain, Size: 2311 bytes --]

On Sun, Dec 16, 2012 at 4:42 PM, Yinghai Lu <yinghai@kernel.org> wrote:
> On Sun, Dec 16, 2012 at 3:59 PM, Yu, Fenghua <fenghua.yu@intel.com> wrote:
>>
>>> it has to be rebased after #PF handler version. otherwise it can not
>>> handle for framdisk
>>> that is loaded after 1G.
>>>
>>> Fenghua,
>>>
>>> can you post your boot log with 64bit with your patch?
>>>
>>> Yinghai
>>
>> Attached is dmesg with the patches.
>>
>
> yes, your laptop only have 1G ram, and
>
> [    0.000000] e820: BIOS-provided physical RAM map:
> [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009d7ff] usable
> [    0.000000] BIOS-e820: [mem 0x000000000009d800-0x000000000009ffff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000000d2000-0x00000000000d3fff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved
> [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000003e6affff] usable
> [    0.000000] BIOS-e820: [mem 0x000000003e6b0000-0x000000003e6ccfff] ACPI data
> [    0.000000] BIOS-e820: [mem 0x000000003e6cd000-0x000000003e6fffff] ACPI NVS
> [    0.000000] BIOS-e820: [mem 0x000000003e700000-0x000000003effffff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fed14000-0x00000000fed19fff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
> [    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
>
> ramdisk is at
>      RAMDISK: [mem 0x27608000-0x2fafbfff]
>
> and current kernel default set 1G to kernel mapping. so it happens to
> work with your patchset.
>
> please find one sytem with 4G or more to test it.
>
> and you may need to rebase your patches on top of my for-x86-boot
> branch with working
> #PF handler set page table patch.
>
> git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-yinghai.git
> for-x86-boot

also you did not consider initrd relocating....

please check attached fix, and see if you can fold in into you next posting.

Thanks

Yinghai

[-- Attachment #2: fix_microcode_v4.patch --]
[-- Type: application/octet-stream, Size: 6633 bytes --]

---
 arch/x86/kernel/microcode_intel_early.c |  101 ++++++++++++++++----------------
 arch/x86/kernel/setup.c                 |   11 +++
 2 files changed, 64 insertions(+), 48 deletions(-)

Index: linux-2.6/arch/x86/kernel/microcode_intel_early.c
===================================================================
--- linux-2.6.orig/arch/x86/kernel/microcode_intel_early.c
+++ linux-2.6/arch/x86/kernel/microcode_intel_early.c
@@ -20,9 +20,11 @@
 #include <linux/vmalloc.h>
 #include <linux/mm.h>
 #include <linux/earlycpio.h>
+
 #include <asm/msr.h>
 #include <asm/microcode_intel.h>
 #include <asm/processor.h>
+#include <asm/setup.h>
 
 struct microcode_intel __initdata *mc_saved_in_initrd[MAX_UCODE_COUNT];
 struct mc_saved_data mc_saved_data;
@@ -290,12 +292,44 @@ static int __cpuinit collect_cpu_info_ea
 	return 0;
 }
 
+#ifdef CONFIG_X86_64
+void __init update_mc_saved_data(unsigned long pa_offset)
+{
+	int i;
+	unsigned long addr;
+
+	if (!pa_offset || !mc_saved_data.mc_saved)
+		return;
+
+	for (i = 0; i< mc_saved_data.mc_saved_count; i++)
+		mc_saved_data.mc_saved[i] += pa_offset;
+}
+#else
+void __init update_mc_saved_data(unsigned long pa_offset)
+{
+	int i;
+
+	if (mc_saved_data.mc_saved) {
+		mc_saved_data.mc_saved = __va(mc_saved_data.mc_saved);
+		for (i = 0; i < mc_saved_data.mc_saved_count; i++)
+			mc_saved_data.mc_saved[i] =
+					 __va(mc_saved_data.mc_saved[i] + pa_offset);
+
+	}
+
+	mc_saved_data.ucode_cpu_info = __va(mc_saved_data.ucode_cpu_info);
+	if (mc_saved_data.ucode_cpu_info->mc)
+		mc_saved_data.ucode_cpu_info->mc =
+				 __va(mc_saved_data.ucode_cpu_info->mc);
+}
+
+#endif
+
 static __init enum ucode_state
-scan_microcode(unsigned long start, unsigned long end,
+scan_microcode(unsigned long start, unsigned long size,
 		struct mc_saved_data *mc_saved_data,
 		struct microcode_intel **mc_saved_in_initrd)
 {
-	unsigned int size = end - start + 1;
 	struct cpio_data cd = { 0, 0 };
 	char ucode_name[] = "kernel/x86/microcode/GenuineIntel.bin";
 	long offset = 0;
@@ -308,7 +342,7 @@ scan_microcode(unsigned long start, unsi
 					 mc_saved_in_initrd, SYSTEM_BOOTING);
 }
 
-static int __init
+static int __cpuinit
 apply_microcode_early(struct mc_saved_data *mc_saved_data, int cpu)
 {
 	struct ucode_cpu_info *uci = mc_saved_data->ucode_cpu_info + cpu;
@@ -339,32 +373,6 @@ apply_microcode_early(struct mc_saved_da
 	return 0;
 }
 
-#ifdef CONFIG_X86_32
-static void __init map_mc_saved(struct mc_saved_data *mc_saved_data,
-				struct microcode_intel **mc_saved_in_initrd)
-{
-	int i;
-
-	if (mc_saved_data->mc_saved) {
-		for (i = 0; i < mc_saved_data->mc_saved_count; i++)
-			mc_saved_data->mc_saved[i] =
-					 __va(mc_saved_data->mc_saved[i]);
-
-		mc_saved_data->mc_saved = __va(mc_saved_data->mc_saved);
-	}
-
-	if (mc_saved_data->ucode_cpu_info->mc)
-		mc_saved_data->ucode_cpu_info->mc =
-				 __va(mc_saved_data->ucode_cpu_info->mc);
-	mc_saved_data->ucode_cpu_info = __va(mc_saved_data->ucode_cpu_info);
-}
-#else
-static inline void __init map_mc_saved(struct mc_saved_data *mc_saved_data,
-				struct microcode_intel **mc_saved_in_initrd)
-{
-}
-#endif
-
 void __init save_microcode_in_initrd(struct mc_saved_data *mc_saved_data,
 		 struct microcode_intel **mc_saved_in_initrd)
 {
@@ -376,7 +384,7 @@ void __init save_microcode_in_initrd(str
 static void __init
 _load_ucode_intel_bsp(struct mc_saved_data *mc_saved_data,
 		      struct microcode_intel **mc_saved_in_initrd,
-		      unsigned long initrd_start, unsigned long initrd_end)
+		      unsigned long initrd_start, unsigned long initrd_size)
 {
 	int cpu = 0;
 
@@ -387,37 +395,34 @@ _load_ucode_intel_bsp(struct mc_saved_da
 			(struct ucode_cpu_info *)__pa(ucode_cpu_info_early);
 #endif
 	collect_cpu_info_early(mc_saved_data->ucode_cpu_info + cpu);
-	scan_microcode(initrd_start, initrd_end, mc_saved_data,
+	scan_microcode(initrd_start, initrd_size, mc_saved_data,
 		       mc_saved_in_initrd);
 	load_microcode(mc_saved_data, cpu);
 	apply_microcode_early(mc_saved_data, cpu);
-	map_mc_saved(mc_saved_data, mc_saved_in_initrd);
 }
 
 void __init
 load_ucode_intel_bsp(char *real_mode_data)
 {
-	u64 ramdisk_image, ramdisk_size, ramdisk_end;
-	unsigned long initrd_start, initrd_end;
-	struct boot_params *boot_params;
-
-	boot_params = (struct boot_params *)real_mode_data;
-	ramdisk_image = boot_params->hdr.ramdisk_image;
-	ramdisk_size  = boot_params->hdr.ramdisk_size;
+	u64 ramdisk_image, ramdisk_size;
 
 #ifdef CONFIG_X86_64
-	ramdisk_end  = PAGE_ALIGN(ramdisk_image + ramdisk_size);
-	initrd_start = ramdisk_image + PAGE_OFFSET;
-	initrd_end = initrd_start + ramdisk_size;
+	ramdisk_image = boot_params.hdr.ramdisk_image;
+	ramdisk_size  = boot_params.hdr.ramdisk_size;
+	if (!ramdisk_image || !ramdisk_size)
+		return;
 	_load_ucode_intel_bsp(&mc_saved_data, mc_saved_in_initrd,
-			      initrd_start, initrd_end);
+			      ramdisk_image, ramdisk_size);
 #else
-	ramdisk_end  = ramdisk_image + ramdisk_size;
-	initrd_start = ramdisk_image;
-	initrd_end = initrd_start + ramdisk_size;
+	struct boot_params *boot_params = (struct boot_params *)real_mode_data;
+
+	ramdisk_image = boot_params->hdr.ramdisk_image;
+	ramdisk_size  = boot_params->hdr.ramdisk_size;
+	if (!ramdisk_image || !ramdisk_size)
+		return;
 	_load_ucode_intel_bsp((struct mc_saved_data *)__pa(&mc_saved_data),
-			(struct microcode_intel **)__pa(mc_saved_in_initrd),
-			initrd_start, initrd_end);
+			      (struct microcode_intel **)__pa(mc_saved_in_initrd),
+			      ramdisk_image, ramdisk_size);
 #endif
 }
 
Index: linux-2.6/arch/x86/kernel/setup.c
===================================================================
--- linux-2.6.orig/arch/x86/kernel/setup.c
+++ linux-2.6/arch/x86/kernel/setup.c
@@ -309,6 +309,14 @@ static u64 __init get_mem_size(unsigned
 
 #ifdef CONFIG_BLK_DEV_INITRD
 
+#ifdef CONFIG_MICROCODE_INTEL_EARLY
+void update_mc_saved_data(unsigned long pa_offset);
+#else
+static inline void update_mc_saved_data(unsigned long pa_offset)
+{
+}
+#endif
+
 static u64 __init get_ramdisk_image(void)
 {
 	u64 ramdisk_image = boot_params.hdr.ramdisk_image;
@@ -376,6 +384,8 @@ static void __init relocate_initrd(void)
 		" [mem %#010llx-%#010llx]\n",
 		ramdisk_image, ramdisk_image + ramdisk_size - 1,
 		ramdisk_here, ramdisk_here + ramdisk_size - 1);
+
+	update_mc_saved_data(ramdisk_here - ramdisk_image);
 }
 
 static void __init early_reserve_initrd(void)
@@ -419,6 +429,7 @@ static void __init reserve_initrd(void)
 		/* All are mapped, easy case */
 		initrd_start = ramdisk_image + PAGE_OFFSET;
 		initrd_end = initrd_start + ramdisk_size;
+		update_mc_saved_data(0);
 		return;
 	}
 

RE: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yu, Fenghua]

> -----Original Message-----
> From: yhlu.kernel@gmail.com [mailto:yhlu.kernel@gmail.com] On Behalf Of
> Yinghai Lu
> Sent: Sunday, December 16, 2012 6:02 PM
> To: Yu, Fenghua
> Cc: H. Peter Anvin; Ingo Molnar; Thomas Gleixner; Mallick, Asit K;
> Tigran Aivazian; Andreas Herrmann; Borislav Petkov; linux-kernel; x86
> Subject: Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-
> bit
> 
> On Sun, Dec 16, 2012 at 4:42 PM, Yinghai Lu <yinghai@kernel.org> wrote:
> > On Sun, Dec 16, 2012 at 3:59 PM, Yu, Fenghua <fenghua.yu@intel.com>
> wrote:
> >>
> >>> it has to be rebased after #PF handler version. otherwise it can
> not
> >>> handle for framdisk that is loaded after 1G.
> >>>
> >>> Fenghua,
> >>>
> >>> can you post your boot log with 64bit with your patch?
> >>>
> >>> Yinghai
> >>
> >> Attached is dmesg with the patches.
> >>
> >
> > yes, your laptop only have 1G ram, and
> >
> > [    0.000000] e820: BIOS-provided physical RAM map:
> > [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009d7ff]
> usable
> > [    0.000000] BIOS-e820: [mem 0x000000000009d800-0x000000000009ffff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000000d2000-0x00000000000d3fff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000003e6affff]
> usable
> > [    0.000000] BIOS-e820: [mem 0x000000003e6b0000-0x000000003e6ccfff]
> ACPI data
> > [    0.000000] BIOS-e820: [mem 0x000000003e6cd000-0x000000003e6fffff]
> ACPI NVS
> > [    0.000000] BIOS-e820: [mem 0x000000003e700000-0x000000003effffff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000fed14000-0x00000000fed19fff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff]
> reserved
> > [    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff]
> reserved
> >
> > ramdisk is at
> >      RAMDISK: [mem 0x27608000-0x2fafbfff]
> >
> > and current kernel default set 1G to kernel mapping. so it happens to
> > work with your patchset.
> >
> > please find one sytem with 4G or more to test it.
> >
> > and you may need to rebase your patches on top of my for-x86-boot
> > branch with working #PF handler set page table patch.
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-
> yinghai.gi
> > t
> > for-x86-boot
> 
> also you did not consider initrd relocating....
> 
> please check attached fix, and see if you can fold in into you next
> posting.
> 
> Thanks
> 
> Yinghai

Your fix is based on old v2 patchset.

Today's v3 patchset fixes this issue already. Basically it uses offset instead of pointer in initrd image and converts offset to pointer when it accesses the microcode in initrd image. It uses pointers after boot time. 

Thanks.

-Fenghua

RE: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yu, Fenghua]

> -----Original Message-----
> From: yhlu.kernel@gmail.com [mailto:yhlu.kernel@gmail.com] On Behalf Of
> Yinghai Lu
> Sent: Sunday, December 16, 2012 4:42 PM
> To: Yu, Fenghua
> Cc: H. Peter Anvin; Ingo Molnar; Thomas Gleixner; Mallick, Asit K;
> Tigran Aivazian; Andreas Herrmann; Borislav Petkov; linux-kernel; x86
> Subject: Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-
> bit
> 
> On Sun, Dec 16, 2012 at 3:59 PM, Yu, Fenghua <fenghua.yu@intel.com>
> wrote:
> >
> >> it has to be rebased after #PF handler version. otherwise it can not
> >> handle for framdisk
> >> that is loaded after 1G.
> >>
> >> Fenghua,
> >>
> >> can you post your boot log with 64bit with your patch?
> >>
> >> Yinghai
> >
> > Attached is dmesg with the patches.
> >
> 
> yes, your laptop only have 1G ram, and
> 
> [    0.000000] e820: BIOS-provided physical RAM map:
> [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009d7ff]
> usable
> [    0.000000] BIOS-e820: [mem 0x000000000009d800-0x000000000009ffff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000000d2000-0x00000000000d3fff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000003e6affff]
> usable
> [    0.000000] BIOS-e820: [mem 0x000000003e6b0000-0x000000003e6ccfff]
> ACPI data
> [    0.000000] BIOS-e820: [mem 0x000000003e6cd000-0x000000003e6fffff]
> ACPI NVS
> [    0.000000] BIOS-e820: [mem 0x000000003e700000-0x000000003effffff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fed14000-0x00000000fed19fff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff]
> reserved
> [    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff]
> reserved
> 
> ramdisk is at
>      RAMDISK: [mem 0x27608000-0x2fafbfff]
> 
> and current kernel default set 1G to kernel mapping. so it happens to
> work with your patchset.
> 
> please find one sytem with 4G or more to test it.
> 
> and you may need to rebase your patches on top of my for-x86-boot
> branch with working
> #PF handler set page table patch.
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-yinghai.git
> for-x86-boot
> 
> Thanks
> 
> Yinghai

OSV may need the patchset based on old kernel. So I'll have the patchset ready. Is this the right place to call load_ucode_bsp() in the upstream kernel?

diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index a512f56..e94b90e 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -93,6 +88,11 @@ void __init x86_64_start_kernel(char * real_mode_data)
        }
        load_idt((const struct desc_ptr *)&idt_descr);

+       /*
+        * Load microcode early on BSP.
+        */
+       load_ucode_bsp(__va(real_mode_data));
+
        if (console_loglevel == 10)
                early_printk("Kernel alive\n");

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yinghai Lu]

On Mon, Dec 17, 2012 at 3:30 PM, Yu, Fenghua <fenghua.yu@intel.com> wrote:
>
> OSV may need the patchset based on old kernel. So I'll have the patchset ready. Is this the right place to call load_ucode_bsp() in the upstream kernel?
>
> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
> index a512f56..e94b90e 100644
> --- a/arch/x86/kernel/head64.c
> +++ b/arch/x86/kernel/head64.c
> @@ -93,6 +88,11 @@ void __init x86_64_start_kernel(char * real_mode_data)
>         }
>         load_idt((const struct desc_ptr *)&idt_descr);
>
> +       /*
> +        * Load microcode early on BSP.
> +        */
> +       load_ucode_bsp(__va(real_mode_data));
> +
>         if (console_loglevel == 10)
>                 early_printk("Kernel alive\n");
>
it has to be after #PF handler set page table patch...

otherwise when ramdisk is above 1G, customer will get early PF exception.

RE: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yu, Fenghua]

> >
> it has to be after #PF handler set page table patch...
> 
> otherwise when ramdisk is above 1G, customer will get early PF
> exception.

In old kernel, where can I put load_ucode_bsp()? Is calling load_ucode_bsp() after relocate_initrd() earliest place?

Thanks.

-Fenghua

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yinghai Lu]

On Mon, Dec 17, 2012 at 4:32 PM, Yu, Fenghua <fenghua.yu@intel.com> wrote:
>> >
>> it has to be after #PF handler set page table patch...
>>
>> otherwise when ramdisk is above 1G, customer will get early PF
>> exception.
>
> In old kernel, where can I put load_ucode_bsp()? Is calling load_ucode_bsp() after relocate_initrd() earliest place?

after init_memory_mapping.

RE: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yu, Fenghua]

> From: yhlu.kernel@gmail.com [mailto:yhlu.kernel@gmail.com] On Behalf Of
> Yinghai Lu
> On Mon, Dec 17, 2012 at 3:30 PM, Yu, Fenghua <fenghua.yu@intel.com>
> wrote:
> >
> > OSV may need the patchset based on old kernel. So I'll have the
> patchset ready. Is this the right place to call load_ucode_bsp() in the
> upstream kernel?
> >
> > diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
> > index a512f56..e94b90e 100644
> > --- a/arch/x86/kernel/head64.c
> > +++ b/arch/x86/kernel/head64.c
> > @@ -93,6 +88,11 @@ void __init x86_64_start_kernel(char *
> real_mode_data)
> >         }
> >         load_idt((const struct desc_ptr *)&idt_descr);
> >
> > +       /*
> > +        * Load microcode early on BSP.
> > +        */
> > +       load_ucode_bsp(__va(real_mode_data));
> > +
> >         if (console_loglevel == 10)
> >                 early_printk("Kernel alive\n");
> >
> it has to be after #PF handler set page table patch...
> 
> otherwise when ramdisk is above 1G, customer will get early PF
> exception.

If based on your for_x86_boot tree, is load_ucode_bsp() called afer load_idt()?

Thanks.

-Fenghua

Re: [PATCH v3 08/10] x86/head64.c: Early update ucode in 64-bit

[Yinghai Lu]

On Tue, Dec 18, 2012 at 2:55 PM, Yu, Fenghua <fenghua.yu@intel.com> wrote:
>> From: yhlu.kernel@gmail.com [mailto:yhlu.kernel@gmail.com] On Behalf Of
>> Yinghai Lu
>> On Mon, Dec 17, 2012 at 3:30 PM, Yu, Fenghua <fenghua.yu@intel.com>
>> wrote:
>> >
>> > OSV may need the patchset based on old kernel. So I'll have the
>> patchset ready. Is this the right place to call load_ucode_bsp() in the
>> upstream kernel?
>> >
>> > diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
>> > index a512f56..e94b90e 100644
>> > --- a/arch/x86/kernel/head64.c
>> > +++ b/arch/x86/kernel/head64.c
>> > @@ -93,6 +88,11 @@ void __init x86_64_start_kernel(char *
>> real_mode_data)
>> >         }
>> >         load_idt((const struct desc_ptr *)&idt_descr);
>> >
>> > +       /*
>> > +        * Load microcode early on BSP.
>> > +        */
>> > +       load_ucode_bsp(__va(real_mode_data));
>> > +
>> >         if (console_loglevel == 10)
>> >                 early_printk("Kernel alive\n");
>> >
>> it has to be after #PF handler set page table patch...
>>
>> otherwise when ramdisk is above 1G, customer will get early PF
>> exception.
>
> If based on your for_x86_boot tree, is load_ucode_bsp() called afer load_idt()?
>

yes.

Please do try your patches on system with more than 4G ram.

Thanks

Yinghai