From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated
Date: Fri, 30 Jul 2021 15:31:56 +0530 [thread overview]
Message-ID: <3f3643fc-95b5-43b2-c512-72a7357f9ca8@arm.com> (raw)
In-Reply-To: <20210728135217.591173-3-suzuki.poulose@arm.com>
On 7/28/21 7:22 PM, Suzuki K Poulose wrote:
> We collect the trace from the TRBE on FILL event from IRQ context
> and when via update_buffer(), when the event is stopped. Let us
> consolidate how we calculate the trace generated into a helper.
>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-trbe.c | 48 ++++++++++++--------
> 1 file changed, 30 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 0368bf405e35..a0168ad204b3 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -528,6 +528,30 @@ static enum trbe_fault_action trbe_get_fault_act(u64 trbsr)
> return TRBE_FAULT_ACT_SPURIOUS;
> }
>
> +static unsigned long trbe_get_trace_size(struct perf_output_handle *handle,
> + struct trbe_buf *buf,
> + bool wrap)
> +{
> + u64 write;
> + u64 start_off, end_off;
> +
> + /*
> + * If the TRBE has wrapped around the write pointer has
> + * wrapped and should be treated as limit.
> + */
> + if (wrap)
> + write = get_trbe_limit_pointer();
> + else
> + write = get_trbe_write_pointer();
> +
> + end_off = write - buf->trbe_base;
> + start_off = PERF_IDX2OFF(handle->head, buf);
> +
> + if (WARN_ON_ONCE(end_off < start_off))
> + return 0;
> + return (end_off - start_off);
> +}
> +
> static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> struct perf_event *event, void **pages,
> int nr_pages, bool snapshot)
> @@ -589,9 +613,9 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> struct trbe_buf *buf = config;
> enum trbe_fault_action act;
> - unsigned long size, offset;
> - unsigned long write, base, status;
> + unsigned long size, status;
> unsigned long flags;
> + bool wrap = false;
>
> WARN_ON(buf->cpudata != cpudata);
> WARN_ON(cpudata->cpu != smp_processor_id());
> @@ -633,8 +657,6 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> * handle gets freed in etm_event_stop().
> */
> trbe_drain_and_disable_local();
> - write = get_trbe_write_pointer();
> - base = get_trbe_base_pointer();
>
> /* Check if there is a pending interrupt and handle it here */
> status = read_sysreg_s(SYS_TRBSR_EL1);
> @@ -658,20 +680,11 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> goto done;
> }
>
> - /*
> - * Otherwise, the buffer is full and the write pointer
> - * has reached base. Adjust this back to the Limit pointer
> - * for correct size. Also, mark the buffer truncated.
> - */
> - write = get_trbe_limit_pointer();
> perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
> + wrap = true;
> }
>
> - offset = write - base;
> - if (WARN_ON_ONCE(offset < PERF_IDX2OFF(handle->head, buf)))
> - size = 0;
> - else
> - size = offset - PERF_IDX2OFF(handle->head, buf);
> + size = trbe_get_trace_size(handle, buf, wrap);
>
> done:
> local_irq_restore(flags);
> @@ -752,11 +765,10 @@ static int trbe_handle_overflow(struct perf_output_handle *handle)
> {
> struct perf_event *event = handle->event;
> struct trbe_buf *buf = etm_perf_sink_config(handle);
> - unsigned long offset, size;
> + unsigned long size;
> struct etm_event_data *event_data;
>
> - offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> - size = offset - PERF_IDX2OFF(handle->head, buf);
> + size = trbe_get_trace_size(handle, buf, true);
> if (buf->snapshot)
> handle->head += size;
>
>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
next prev parent reply other threads:[~2021-07-30 10:02 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-08-02 6:43 ` Anshuman Khandual
2021-09-07 9:04 ` Suzuki K Poulose
2021-09-09 2:55 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-07-30 10:01 ` Anshuman Khandual [this message]
2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-07-30 10:05 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-07-30 10:53 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-07-30 11:02 ` Anshuman Khandual
2021-07-30 14:29 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-07-30 11:26 ` Anshuman Khandual
2021-07-30 14:31 ` Suzuki K Poulose
2021-08-02 11:21 ` Catalin Marinas
2021-08-02 11:21 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-08-02 7:44 ` Anshuman Khandual
2021-08-02 11:22 ` Catalin Marinas
2021-08-06 12:44 ` Linu Cherian
2021-09-07 9:10 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose
2021-08-03 10:25 ` Anshuman Khandual
2021-09-07 9:58 ` Suzuki K Poulose
2021-09-09 4:21 ` Anshuman Khandual
2021-09-09 8:37 ` Suzuki K Poulose
2021-08-06 16:09 ` Linu Cherian
2021-09-07 9:18 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-08-02 9:34 ` Anshuman Khandual
2021-08-02 11:24 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-07-29 9:55 ` Marc Zyngier
2021-07-29 10:41 ` Suzuki K Poulose
2021-08-02 9:12 ` Anshuman Khandual
2021-08-02 9:35 ` Marc Zyngier
2021-08-03 3:51 ` Anshuman Khandual
2021-09-08 13:39 ` Suzuki K Poulose
2021-08-02 11:27 ` Catalin Marinas
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