From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org, mark.rutland@arm.com
Subject: Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures
Date: Tue, 3 Aug 2021 09:21:48 +0530 [thread overview]
Message-ID: <eb02839d-b7af-0284-e4ef-8c628e0548d9@arm.com> (raw)
In-Reply-To: <32f719c8f9f61b244b3fc29137f76a19@kernel.org>
On 8/2/21 3:05 PM, Marc Zyngier wrote:
> On 2021-08-02 10:12, Anshuman Khandual wrote:
>> On 7/29/21 4:11 PM, Suzuki K Poulose wrote:
>>> On 29/07/2021 10:55, Marc Zyngier wrote:
>>>> On Wed, 28 Jul 2021 14:52:17 +0100,
>>>> Suzuki K Poulose <suzuki.poulose@arm.com>
>
> [...]
>
>>>>> + __tsb_csync(); \
>>>>> + __tsb_csync(); \
>>>>> + } else { \
>>>>> + __tsb_csync(); \
>>>>> + } \
>>>>
>>>> nit: You could keep one unconditional __tsb_csync().
>>>
>>> I thought about that, I was worried if the CPU expects them back to back
>>> without any other instructions in between them. Thinking about it a bit
>>> more, it doesn't look like that is the case. I will confirm this and
>>> change it accordingly.
>> But its a very subtle change which might be difficult to debug and blame
>> later on, if indeed both the instructions need to be back to back. Seems
>> like just better to leave this unchanged.
>
> Is that an actual requirement? Sounds like you want to find out
> from the errata document.
Sure, will get back on this.
>
> And if they actually need to be back to back, what ensures that
> this is always called with interrupt disabled?
>
> You would also need to have them in the same asm block to avoid
> the compiler reordering stuff.
Agreed, both the above constructs will be required to make sure that
the instructions will be executed consecutively (if required).
next prev parent reply other threads:[~2021-08-03 3:51 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-08-02 6:43 ` Anshuman Khandual
2021-09-07 9:04 ` Suzuki K Poulose
2021-09-09 2:55 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-07-30 10:01 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-07-30 10:05 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-07-30 10:53 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-07-30 11:02 ` Anshuman Khandual
2021-07-30 14:29 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-07-30 11:26 ` Anshuman Khandual
2021-07-30 14:31 ` Suzuki K Poulose
2021-08-02 11:21 ` Catalin Marinas
2021-08-02 11:21 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-08-02 7:44 ` Anshuman Khandual
2021-08-02 11:22 ` Catalin Marinas
2021-08-06 12:44 ` Linu Cherian
2021-09-07 9:10 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose
2021-08-03 10:25 ` Anshuman Khandual
2021-09-07 9:58 ` Suzuki K Poulose
2021-09-09 4:21 ` Anshuman Khandual
2021-09-09 8:37 ` Suzuki K Poulose
2021-08-06 16:09 ` Linu Cherian
2021-09-07 9:18 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-08-02 9:34 ` Anshuman Khandual
2021-08-02 11:24 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-07-29 9:55 ` Marc Zyngier
2021-07-29 10:41 ` Suzuki K Poulose
2021-08-02 9:12 ` Anshuman Khandual
2021-08-02 9:35 ` Marc Zyngier
2021-08-03 3:51 ` Anshuman Khandual [this message]
2021-09-08 13:39 ` Suzuki K Poulose
2021-08-02 11:27 ` Catalin Marinas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=eb02839d-b7af-0284-e4ef-8c628e0548d9@arm.com \
--to=anshuman.khandual@arm.com \
--cc=catalin.marinas@arm.com \
--cc=coresight@lists.linaro.org \
--cc=james.morse@arm.com \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mathieu.poirier@linaro.org \
--cc=maz@kernel.org \
--cc=mike.leach@linaro.org \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).