From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v1 07/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
Date: Fri, 20 Jan 2023 09:13:15 +0100 [thread overview]
Message-ID: <428dc119-82ab-e565-7bd6-1a99ec3967d9@linaro.org> (raw)
In-Reply-To: <20230120024445.244345-8-xingyu.wu@starfivetech.com>
On 20/01/2023 03:44, Xingyu Wu wrote:
> Add bindings for the Video-Output clock and reset generator (VOUTCRG)
> on the JH7110 RISC-V SoC by StarFive Ltd.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> .../clock/starfive,jh7110-voutcrg.yaml | 96 +++++++++++++++++++
> .../dt-bindings/clock/starfive,jh7110-crg.h | 22 +++++
> .../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++
> 3 files changed, 134 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
> new file mode 100644
> index 000000000000..a6a43d86a392
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Video-Output Clock and Reset Generator
> +
> +maintainers:
> + - Xingyu Wu <xingyu.wu@starfivetech.com>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-voutcrg
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Vout Top core
> + - description: Vout Top Ahb
> + - description: Vout Top Axi
> + - description: Vout Top HDMI MCLK
> + - description: I2STX0 BCLK
> + - description: external HDMI pixel
> +
> + clock-names:
> + items:
> + - const: vout_src
> + - const: vout_top_ahb
> + - const: vout_top_axi
> + - const: vout_top_hdmitx0_mclk
> + - const: i2stx0_bclk
> + - const: hdmitx0_pixelclk
> +
> + resets:
> + items:
> + - description: Vout Top core
> +
> + reset-names:
> + items:
> + - const: vout_top_src
> +
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
> +
> + '#reset-cells':
> + const: 1
> + description:
> + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
> +
> + power-domains:
> + maxItems: 1
> + description:
> + Vout domain power
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - '#clock-cells'
> + - '#reset-cells'
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive,jh7110-crg.h>
> + #include <dt-bindings/power/starfive,jh7110-pmu.h>
> + #include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> + voutcrg: clock-controller@295C0000 {
> + compatible = "starfive,jh7110-voutcrg";
> + reg = <0x295C0000 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
> + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
> + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
> + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
> + <&hdmitx0_pixelclk>;
> + clock-names = "vout_src", "vout_top_ahb",
> + "vout_top_axi", "vout_top_hdmitx0_mclk",
> + "i2stx0_bclk", "hdmitx0_pixelclk";
> + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
> + reset-names = "vout_top_src";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + power-domains = <&pwrc JH7110_PD_VOUT>;
> + };
> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
> index 91ee589809c3..3ebece93cbd3 100644
> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
> @@ -274,4 +274,26 @@
>
> #define JH7110_ISPCLK_END 14
>
> +/* VOUTCRG clocks */
> +#define JH7110_VOUTCLK_APB 0
> +#define JH7110_VOUTCLK_DC8200_PIX 1
> +#define JH7110_VOUTCLK_DSI_SYS 2
> +#define JH7110_VOUTCLK_TX_ESC 3
> +#define JH7110_VOUTCLK_DC8200_AXI 4
> +#define JH7110_VOUTCLK_DC8200_CORE 5
> +#define JH7110_VOUTCLK_DC8200_AHB 6
> +#define JH7110_VOUTCLK_DC8200_PIX0 7
> +#define JH7110_VOUTCLK_DC8200_PIX1 8
> +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
> +#define JH7110_VOUTCLK_DSITX_APB 10
> +#define JH7110_VOUTCLK_DSITX_SYS 11
> +#define JH7110_VOUTCLK_DSITX_DPI 12
> +#define JH7110_VOUTCLK_DSITX_TXESC 13
> +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
> +#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
> +#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
> +#define JH7110_VOUTCLK_HDMI_TX_SYS 17
> +
> +#define JH7110_VOUTCLK_END 18
> +
> #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
> diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
> index 1b40df62cdac..f89589610cf5 100644
> --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
> +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
> @@ -195,4 +195,20 @@
>
> #define JH7110_ISPRST_END 12
>
> +/* VOUTCRG resets */
> +#define JH7110_VOUTRST_DC8200_AXI 0
> +#define JH7110_VOUTRST_DC8200_AHB 1
Ditto
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-01-20 8:13 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 2:44 [PATCH v1 00/11] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 01/11] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
2023-01-20 8:11 ` Krzysztof Kozlowski
2023-01-30 6:17 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 02/11] reset: starfive: jh7110: Add StarFive System-Top-Group reset support Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 03/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
2023-01-26 2:33 ` Stephen Boyd
2023-01-30 8:02 ` Xingyu Wu
2023-01-31 0:35 ` Stephen Boyd
2023-01-31 6:51 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 04/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
2023-01-20 8:12 ` Krzysztof Kozlowski
2023-01-30 8:03 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 05/11] reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 06/11] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
2023-01-26 2:35 ` Stephen Boyd
2023-01-30 8:09 ` Xingyu Wu
2023-01-31 0:38 ` Stephen Boyd
2023-01-31 6:52 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 07/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
2023-01-20 8:13 ` Krzysztof Kozlowski [this message]
2023-01-30 8:10 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 08/11] reset: starfive: jh7110: Add StarFive Video-Output reset support Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 09/11] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
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