From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v1 04/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
Date: Mon, 30 Jan 2023 16:03:28 +0800 [thread overview]
Message-ID: <5a34660f-63b3-e6c8-c25c-6bd74b6dd99d@starfivetech.com> (raw)
In-Reply-To: <f85f5283-98b2-46b1-5a91-64ae708a6353@linaro.org>
On 2023/1/20 16:12, Krzysztof Kozlowski wrote:
> On 20/01/2023 03:44, Xingyu Wu wrote:
>> Add bindings for the Image-Signal-Process clock and reset
>> generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
>> .../clock/starfive,jh7110-ispcrg.yaml | 97 +++++++++++++++++++
>> .../dt-bindings/clock/starfive,jh7110-crg.h | 18 ++++
>> .../dt-bindings/reset/starfive,jh7110-crg.h | 16 +++
>> 3 files changed, 131 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
>> new file mode 100644
>> index 000000000000..32794f809364
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
>> @@ -0,0 +1,97 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
>> +
>> +maintainers:
>> + - Xingyu Wu <xingyu.wu@starfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-ispcrg
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: ISP Top core
>> + - description: ISP Top Axi
>> + - description: NOC ISP Bus
>> + - description: external DVP
>> +
>> + clock-names:
>> + items:
>> + - const: isp_top_core
>> + - const: isp_top_axi
>> + - const: noc_bus_isp_axi
>> + - const: dvp_clk
>> +
>> + resets:
>> + items:
>> + - description: ISP Top core
>> + - description: ISP Top Axi
>> + - description: NOC ISP Bus
>> +
>> + reset-names:
>> + items:
>> + - const: isp_top_core
>> + - const: isp_top_axi
>> + - const: noc_bus_isp_axi
>> +
>> + '#clock-cells':
>> + const: 1
>> + description:
>> + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
>> +
>> + '#reset-cells':
>> + const: 1
>> + description:
>> + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
>> +
>> + power-domains:
>> + maxItems: 1
>> + description:
>> + ISP domain power
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - '#clock-cells'
>> + - '#reset-cells'
>> + - power-domains
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/starfive,jh7110-crg.h>
>> + #include <dt-bindings/power/starfive,jh7110-pmu.h>
>> + #include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> + ispcrg: clock-controller@19810000 {
>> + compatible = "starfive,jh7110-ispcrg";
>> + reg = <0x19810000 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
>> + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
>> + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
>> + <&dvp_clk>;
>> + clock-names = "isp_top_core", "isp_top_axi",
>> + "noc_bus_isp_axi", "dvp_clk";
>> + resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
>> + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
>> + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
>> + reset-names = "isp_top_core",
>> + "isp_top_axi",
>> + "noc_bus_isp_axi";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + power-domains = <&pwrc JH7110_PD_ISP>;
>> + };
>> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> index 5ac8a4d90a7a..91ee589809c3 100644
>> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> @@ -256,4 +256,22 @@
>>
>> #define JH7110_STGCLK_END 29
>>
>> +/* ISPCRG clocks */
>> +#define JH7110_ISPCLK_DOM4_APB_FUNC 0
>> +#define JH7110_ISPCLK_MIPI_RX0_PXL 1
>> +#define JH7110_ISPCLK_DVP_INV 2
>> +#define JH7110_ISPCLK_M31DPHY_CFGCLK_IN 3
>> +#define JH7110_ISPCLK_M31DPHY_REFCLK_IN 4
>> +#define JH7110_ISPCLK_M31DPHY_TXCLKESC_LAN0 5
>> +#define JH7110_ISPCLK_VIN_PCLK 6
>> +#define JH7110_ISPCLK_VIN_SYS_CLK 7
>> +#define JH7110_ISPCLK_VIN_PIXEL_CLK_IF0 8
>> +#define JH7110_ISPCLK_VIN_PIXEL_CLK_IF1 9
>> +#define JH7110_ISPCLK_VIN_PIXEL_CLK_IF2 10
>> +#define JH7110_ISPCLK_VIN_PIXEL_CLK_IF3 11
>> +#define JH7110_ISPCLK_VIN_CLK_P_AXIWR 12
>> +#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_CLK_C 13
>> +
>> +#define JH7110_ISPCLK_END 14
>> +
>> #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
>> diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
>> index cb70a1759482..1b40df62cdac 100644
>> --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
>> @@ -179,4 +179,20 @@
>>
>> #define JH7110_STGRST_END 23
>>
>> +/* ISPCRG resets */
>> +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
>
> Drop weird indentation.
Will fix.
Best regards,
Xingyu Wu
next prev parent reply other threads:[~2023-01-30 8:09 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 2:44 [PATCH v1 00/11] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 01/11] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
2023-01-20 8:11 ` Krzysztof Kozlowski
2023-01-30 6:17 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 02/11] reset: starfive: jh7110: Add StarFive System-Top-Group reset support Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 03/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
2023-01-26 2:33 ` Stephen Boyd
2023-01-30 8:02 ` Xingyu Wu
2023-01-31 0:35 ` Stephen Boyd
2023-01-31 6:51 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 04/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
2023-01-20 8:12 ` Krzysztof Kozlowski
2023-01-30 8:03 ` Xingyu Wu [this message]
2023-01-20 2:44 ` [PATCH v1 05/11] reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 06/11] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
2023-01-26 2:35 ` Stephen Boyd
2023-01-30 8:09 ` Xingyu Wu
2023-01-31 0:38 ` Stephen Boyd
2023-01-31 6:52 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 07/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
2023-01-20 8:13 ` Krzysztof Kozlowski
2023-01-30 8:10 ` Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 08/11] reset: starfive: jh7110: Add StarFive Video-Output reset support Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 09/11] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
2023-01-20 2:44 ` [PATCH v1 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
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