* [PATCHv4 1/7] EDAC, altera: Add panic flag check to A10 IRQ
2016-06-20 14:50 [PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions tthayer
@ 2016-06-20 14:50 ` tthayer
2016-06-20 14:50 ` [PATCHv4 2/7] EDAC, altera: Make all private data structures static const tthayer
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: tthayer @ 2016-06-20 14:50 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.
OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.
ECCs on peripheral FIFO buffers will not cause a kernel panic
on DBERRs because the packet can be retried and therefore
recovered.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2 New patch. Add panic flag to IRQ function.
v3 No change
v4 Add reasons to panic on DBERR in OCRAM.
---
drivers/edac/altera_edac.c | 9 ++++++++-
drivers/edac/altera_edac.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 926bcaf..ced7c55 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -897,7 +897,8 @@ static irqreturn_t altr_edac_a10_ecc_irq(int irq, void *dev_id)
writel(ALTR_A10_ECC_DERRPENA,
base + ALTR_A10_ECC_INTSTAT_OFST);
edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
- panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+ if (dci->data->panic)
+ panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
return IRQ_HANDLED;
}
@@ -936,6 +937,12 @@ const struct edac_device_prv_data a10_ocramecc_data = {
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = &altr_edac_a10_device_inject_fops,
+ /*
+ * OCRAM panic on uncorrectable error because sleep/resume
+ * functions and FPGA contents are stored in OCRAM. Prefer
+ * a kernel panic over executing/loading corrupted data.
+ */
+ .panic = true,
};
#endif /* CONFIG_EDAC_ALTERA_OCRAM */
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 62b0fa0..cf4e8cb 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -298,6 +298,7 @@ struct edac_device_prv_data {
irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
int trig_alloc_sz;
const struct file_operations *inject_fops;
+ bool panic;
};
struct altr_edac_device_dev {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCHv4 2/7] EDAC, altera: Make all private data structures static const.
2016-06-20 14:50 [PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions tthayer
2016-06-20 14:50 ` [PATCHv4 1/7] EDAC, altera: Add panic flag check to A10 IRQ tthayer
@ 2016-06-20 14:50 ` tthayer
2016-06-20 14:50 ` [PATCHv4 3/7] EDAC, altera: Share Arria10 check_deps & IRQ functions tthayer
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: tthayer @ 2016-06-20 14:50 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
The device private data structures should be converted from const
struct edac_device_prv_data to static const struct edac_device_prv_data.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v4 New patch added for conversion.
---
drivers/edac/altera_edac.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index ced7c55..14c9248 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -550,10 +550,10 @@ module_platform_driver(altr_edac_driver);
* trigger testing are different for each memory.
*/
-const struct edac_device_prv_data ocramecc_data;
-const struct edac_device_prv_data l2ecc_data;
-const struct edac_device_prv_data a10_ocramecc_data;
-const struct edac_device_prv_data a10_l2ecc_data;
+static const struct edac_device_prv_data ocramecc_data;
+static const struct edac_device_prv_data l2ecc_data;
+static const struct edac_device_prv_data a10_ocramecc_data;
+static const struct edac_device_prv_data a10_l2ecc_data;
static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
{
@@ -908,7 +908,7 @@ static irqreturn_t altr_edac_a10_ecc_irq(int irq, void *dev_id)
return IRQ_NONE;
}
-const struct edac_device_prv_data ocramecc_data = {
+static const struct edac_device_prv_data ocramecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
.ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
@@ -924,7 +924,7 @@ const struct edac_device_prv_data ocramecc_data = {
.inject_fops = &altr_edac_device_inject_fops,
};
-const struct edac_device_prv_data a10_ocramecc_data = {
+static const struct edac_device_prv_data a10_ocramecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
@@ -1028,7 +1028,7 @@ static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
return IRQ_NONE;
}
-const struct edac_device_prv_data l2ecc_data = {
+static const struct edac_device_prv_data l2ecc_data = {
.setup = altr_l2_check_deps,
.ce_clear_mask = 0,
.ue_clear_mask = 0,
@@ -1043,7 +1043,7 @@ const struct edac_device_prv_data l2ecc_data = {
.inject_fops = &altr_edac_device_inject_fops,
};
-const struct edac_device_prv_data a10_l2ecc_data = {
+static const struct edac_device_prv_data a10_l2ecc_data = {
.setup = altr_l2_check_deps,
.ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
.ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCHv4 3/7] EDAC, altera: Share Arria10 check_deps & IRQ functions
2016-06-20 14:50 [PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions tthayer
2016-06-20 14:50 ` [PATCHv4 1/7] EDAC, altera: Add panic flag check to A10 IRQ tthayer
2016-06-20 14:50 ` [PATCHv4 2/7] EDAC, altera: Make all private data structures static const tthayer
@ 2016-06-20 14:50 ` tthayer
2016-06-20 14:50 ` [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding tthayer
` (3 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: tthayer @ 2016-06-20 14:50 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2 New patch. Move shared functions outside OCRAM only area.
v3 Change title line - check_deps & IRQ.
v4 Replace #ifdeffery with __maybe_unused macro.
---
drivers/edac/altera_edac.c | 62 +++++++++++++++++++++++---------------------
1 file changed, 33 insertions(+), 29 deletions(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 14c9248..5f01974 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -825,16 +825,16 @@ static struct platform_driver altr_edac_device_driver = {
};
module_platform_driver(altr_edac_device_driver);
-/*********************** OCRAM EDAC Device Functions *********************/
+/******************* Arria10 Device ECC Shared Functions *****************/
-#ifdef CONFIG_EDAC_ALTERA_OCRAM
/*
* Test for memory's ECC dependencies upon entry because platform specific
* startup should have initialized the memory and enabled the ECC.
* Can't turn on ECC here because accessing un-initialized memory will
* cause CE/UE errors possibly causing an ABORT.
*/
-static int altr_check_ecc_deps(struct altr_edac_device_dev *device)
+static int __maybe_unused
+altr_check_ecc_deps(struct altr_edac_device_dev *device)
{
void __iomem *base = device->base;
const struct edac_device_prv_data *prv = device->data;
@@ -848,6 +848,36 @@ static int altr_check_ecc_deps(struct altr_edac_device_dev *device)
return -ENODEV;
}
+static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
+{
+ struct altr_edac_device_dev *dci = dev_id;
+ void __iomem *base = dci->base;
+
+ if (irq == dci->sb_irq) {
+ writel(ALTR_A10_ECC_SERRPENA,
+ base + ALTR_A10_ECC_INTSTAT_OFST);
+ edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
+
+ return IRQ_HANDLED;
+ } else if (irq == dci->db_irq) {
+ writel(ALTR_A10_ECC_DERRPENA,
+ base + ALTR_A10_ECC_INTSTAT_OFST);
+ edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
+ if (dci->data->panic)
+ panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+
+ return IRQ_HANDLED;
+ }
+
+ WARN_ON(1);
+
+ return IRQ_NONE;
+}
+
+/*********************** OCRAM EDAC Device Functions *********************/
+
+#ifdef CONFIG_EDAC_ALTERA_OCRAM
+
static void *ocram_alloc_mem(size_t size, void **other)
{
struct device_node *np;
@@ -882,32 +912,6 @@ static void ocram_free_mem(void *p, size_t size, void *other)
gen_pool_free((struct gen_pool *)other, (u32)p, size);
}
-static irqreturn_t altr_edac_a10_ecc_irq(int irq, void *dev_id)
-{
- struct altr_edac_device_dev *dci = dev_id;
- void __iomem *base = dci->base;
-
- if (irq == dci->sb_irq) {
- writel(ALTR_A10_ECC_SERRPENA,
- base + ALTR_A10_ECC_INTSTAT_OFST);
- edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
-
- return IRQ_HANDLED;
- } else if (irq == dci->db_irq) {
- writel(ALTR_A10_ECC_DERRPENA,
- base + ALTR_A10_ECC_INTSTAT_OFST);
- edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
- if (dci->data->panic)
- panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
-
- return IRQ_HANDLED;
- }
-
- WARN_ON(1);
-
- return IRQ_NONE;
-}
-
static const struct edac_device_prv_data ocramecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding
2016-06-20 14:50 [PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions tthayer
` (2 preceding siblings ...)
2016-06-20 14:50 ` [PATCHv4 3/7] EDAC, altera: Share Arria10 check_deps & IRQ functions tthayer
@ 2016-06-20 14:50 ` tthayer
2016-06-21 13:33 ` Rob Herring
2016-06-20 14:50 ` [PATCHv4 5/7] EDAC, altera: Add Arria10 ECC memory init functions tthayer
` (2 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: tthayer @ 2016-06-20 14:50 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
v4 Add compatible string for parent node.
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 15eb0df..7c714ba 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -82,6 +82,14 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
+Ethernet FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-eth-mac-ecc"
+- reg : Address and size for ECC block registers.
+- parent : phandle to parent (altr,socfpga-stmmac) Ethernet node.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -108,4 +116,20 @@ Example:
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
<33 IRQ_TYPE_LEVEL_HIGH> ;
};
+
+ emac0-rx-ecc@ff8c0800 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0800 0x400>;
+ parent = <&gmac0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+ <36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-tx-ecc@ff8c0c00 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0c00 0x400>;
+ parent = <&gmac0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+ <37 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding
2016-06-20 14:50 ` [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding tthayer
@ 2016-06-21 13:33 ` Rob Herring
2016-06-21 14:46 ` Thor Thayer
0 siblings, 1 reply; 12+ messages in thread
From: Rob Herring @ 2016-06-21 13:33 UTC (permalink / raw)
To: tthayer
Cc: bp, dougthompson, m.chehab, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
tthayer.linux
On Mon, Jun 20, 2016 at 09:50:49AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree bindings needed to support the Altera Ethernet
> FIFO buffers on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2 No Change
> v3 Change to common compatible string based on maintainer comments
> Add local IRQ values.
> v4 Add compatible string for parent node.
> ---
> .../bindings/arm/altera/socfpga-eccmgr.txt | 24 ++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
> index 15eb0df..7c714ba 100644
> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
> @@ -82,6 +82,14 @@ Required Properties:
> - interrupts : Should be single bit error interrupt, then double bit error
> interrupt, in this order.
>
> +Ethernet FIFO ECC
> +Required Properties:
> +- compatible : Should be "altr,socfpga-eth-mac-ecc"
> +- reg : Address and size for ECC block registers.
> +- parent : phandle to parent (altr,socfpga-stmmac) Ethernet node.
Sorry if I wasn't clear before, but I was suggesting changing 'parent'
to 'altr,ethernet-mac':
altr,ethernet-mac = <&gmac0>;
Rob
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding
2016-06-21 13:33 ` Rob Herring
@ 2016-06-21 14:46 ` Thor Thayer
2016-06-21 15:48 ` Rob Herring
0 siblings, 1 reply; 12+ messages in thread
From: Thor Thayer @ 2016-06-21 14:46 UTC (permalink / raw)
To: Rob Herring
Cc: bp, dougthompson, m.chehab, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
tthayer.linux
Hi Rob,
On 06/21/2016 08:33 AM, Rob Herring wrote:
> On Mon, Jun 20, 2016 at 09:50:49AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add the device tree bindings needed to support the Altera Ethernet
>> FIFO buffers on the Arria10 chip.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>> v2 No Change
>> v3 Change to common compatible string based on maintainer comments
>> Add local IRQ values.
>> v4 Add compatible string for parent node.
>> ---
>> .../bindings/arm/altera/socfpga-eccmgr.txt | 24 ++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>> index 15eb0df..7c714ba 100644
>> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>> @@ -82,6 +82,14 @@ Required Properties:
>> - interrupts : Should be single bit error interrupt, then double bit error
>> interrupt, in this order.
>>
>> +Ethernet FIFO ECC
>> +Required Properties:
>> +- compatible : Should be "altr,socfpga-eth-mac-ecc"
>> +- reg : Address and size for ECC block registers.
>> +- parent : phandle to parent (altr,socfpga-stmmac) Ethernet node.
>
> Sorry if I wasn't clear before, but I was suggesting changing 'parent'
> to 'altr,ethernet-mac':
>
> altr,ethernet-mac = <&gmac0>;
>
> Rob
>
Ahh, I see what you're saying.
I used parent as the tag because I have a generic function for
validating that the parent status is "okay" using the "parent" string in
my validate_parent_available() function (see below).
I will be submitting other peripheral FIFOs with EDAC protection in
future patches (USB, DMA, etc).
static int validate_parent_available(struct device_node *np)
{
struct device_node *parent;
int ret = 0;
/* Ensure parent device is enabled if parent node exists */
parent = of_parse_phandle(np, "parent", 0);
if (parent && !of_device_is_available(parent))
ret = -ENODEV;
of_node_put(parent);
return ret;
}
I can change this to using a passed in data string but the code won't be
as straightforward.
Thanks for reviewing,
Thor
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding
2016-06-21 14:46 ` Thor Thayer
@ 2016-06-21 15:48 ` Rob Herring
2016-06-21 15:57 ` Thor Thayer
0 siblings, 1 reply; 12+ messages in thread
From: Rob Herring @ 2016-06-21 15:48 UTC (permalink / raw)
To: Thor Thayer
Cc: Borislav Petkov, Doug Thompson, Mauro Carvalho Chehab,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King - ARM Linux, Dinh Nguyen, Grant Likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
Thor Thayer
On Tue, Jun 21, 2016 at 9:46 AM, Thor Thayer
<tthayer@opensource.altera.com> wrote:
> Hi Rob,
>
>
> On 06/21/2016 08:33 AM, Rob Herring wrote:
>>
>> On Mon, Jun 20, 2016 at 09:50:49AM -0500, tthayer@opensource.altera.com
>> wrote:
>>>
>>> From: Thor Thayer <tthayer@opensource.altera.com>
>>>
>>> Add the device tree bindings needed to support the Altera Ethernet
>>> FIFO buffers on the Arria10 chip.
>>>
>>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>>> ---
>>> v2 No Change
>>> v3 Change to common compatible string based on maintainer comments
>>> Add local IRQ values.
>>> v4 Add compatible string for parent node.
>>> ---
>>> .../bindings/arm/altera/socfpga-eccmgr.txt | 24
>>> ++++++++++++++++++++
>>> 1 file changed, 24 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>> b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>> index 15eb0df..7c714ba 100644
>>> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>> @@ -82,6 +82,14 @@ Required Properties:
>>> - interrupts : Should be single bit error interrupt, then double bit
>>> error
>>> interrupt, in this order.
>>>
>>> +Ethernet FIFO ECC
>>> +Required Properties:
>>> +- compatible : Should be "altr,socfpga-eth-mac-ecc"
>>> +- reg : Address and size for ECC block registers.
>>> +- parent : phandle to parent (altr,socfpga-stmmac) Ethernet node.
>>
>>
>> Sorry if I wasn't clear before, but I was suggesting changing 'parent'
>> to 'altr,ethernet-mac':
>>
>> altr,ethernet-mac = <&gmac0>;
>>
>> Rob
>>
> Ahh, I see what you're saying.
>
> I used parent as the tag because I have a generic function for validating
> that the parent status is "okay" using the "parent" string in my
> validate_parent_available() function (see below).
Ah, so common ecc-mgr code is parsing it. Then how about 'altr,ecc-parent'?
Rob
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding
2016-06-21 15:48 ` Rob Herring
@ 2016-06-21 15:57 ` Thor Thayer
0 siblings, 0 replies; 12+ messages in thread
From: Thor Thayer @ 2016-06-21 15:57 UTC (permalink / raw)
To: Rob Herring
Cc: Borislav Petkov, Doug Thompson, Mauro Carvalho Chehab,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King - ARM Linux, Dinh Nguyen, Grant Likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
Thor Thayer
On 06/21/2016 10:48 AM, Rob Herring wrote:
> On Tue, Jun 21, 2016 at 9:46 AM, Thor Thayer
> <tthayer@opensource.altera.com> wrote:
>> Hi Rob,
>>
>>
>> On 06/21/2016 08:33 AM, Rob Herring wrote:
>>>
>>> On Mon, Jun 20, 2016 at 09:50:49AM -0500, tthayer@opensource.altera.com
>>> wrote:
>>>>
>>>> From: Thor Thayer <tthayer@opensource.altera.com>
>>>>
>>>> Add the device tree bindings needed to support the Altera Ethernet
>>>> FIFO buffers on the Arria10 chip.
>>>>
>>>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>>>> ---
>>>> v2 No Change
>>>> v3 Change to common compatible string based on maintainer comments
>>>> Add local IRQ values.
>>>> v4 Add compatible string for parent node.
>>>> ---
>>>> .../bindings/arm/altera/socfpga-eccmgr.txt | 24
>>>> ++++++++++++++++++++
>>>> 1 file changed, 24 insertions(+)
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>> b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>> index 15eb0df..7c714ba 100644
>>>> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>>>> @@ -82,6 +82,14 @@ Required Properties:
>>>> - interrupts : Should be single bit error interrupt, then double bit
>>>> error
>>>> interrupt, in this order.
>>>>
>>>> +Ethernet FIFO ECC
>>>> +Required Properties:
>>>> +- compatible : Should be "altr,socfpga-eth-mac-ecc"
>>>> +- reg : Address and size for ECC block registers.
>>>> +- parent : phandle to parent (altr,socfpga-stmmac) Ethernet node.
>>>
>>>
>>> Sorry if I wasn't clear before, but I was suggesting changing 'parent'
>>> to 'altr,ethernet-mac':
>>>
>>> altr,ethernet-mac = <&gmac0>;
>>>
>>> Rob
>>>
>> Ahh, I see what you're saying.
>>
>> I used parent as the tag because I have a generic function for validating
>> that the parent status is "okay" using the "parent" string in my
>> validate_parent_available() function (see below).
>
> Ah, so common ecc-mgr code is parsing it. Then how about 'altr,ecc-parent'?
>
> Rob
>
That's clean - I'll change to that string. Thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCHv4 5/7] EDAC, altera: Add Arria10 ECC memory init functions
2016-06-20 14:50 [PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions tthayer
` (3 preceding siblings ...)
2016-06-20 14:50 ` [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding tthayer
@ 2016-06-20 14:50 ` tthayer
2016-06-20 14:50 ` [PATCHv4 6/7] EDAC, altera: Add Arria10 Ethernet EDAC support tthayer
2016-06-20 14:50 ` [PATCHv4 7/7] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry tthayer
6 siblings, 0 replies; 12+ messages in thread
From: tthayer @ 2016-06-20 14:50 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific functions so that function
declarations are not required.
Use ERRINTENS & ERRINTENR registers instead of read/modify/write.
v3: Changes for common compatibility string:
- Pass node instead of compatibility string.
- New altr_init_a10_ecc_device_type() for peripherals.
- Add __init to altr_init_a10_ecc_block().
- Add a10_get_irq_mask().
v4 Replace ifdefs with __maybe_unused macro
Improve if,else statement in altr_init_memory_port()
Remove confusing comment about shared function.
---
drivers/edac/altera_edac.c | 192 ++++++++++++++++++++++++++++++++++++++++++++
drivers/edac/altera_edac.h | 8 ++
2 files changed, 200 insertions(+)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 5f01974..d97f22e 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -19,6 +19,7 @@
#include <asm/cacheflush.h>
#include <linux/ctype.h>
+#include <linux/delay.h>
#include <linux/edac.h>
#include <linux/genalloc.h>
#include <linux/interrupt.h>
@@ -874,6 +875,197 @@ static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
return IRQ_NONE;
}
+/******************* Arria10 Memory Buffer Functions *********************/
+
+static inline int a10_get_irq_mask(struct device_node *np)
+{
+ int irq;
+ const u32 *handle = of_get_property(np, "interrupts", NULL);
+
+ if (!handle)
+ return -ENODEV;
+ irq = be32_to_cpup(handle);
+ return irq;
+}
+
+static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
+{
+ u32 value = readl(ioaddr);
+
+ value |= bit_mask;
+ writel(value, ioaddr);
+}
+
+static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
+{
+ u32 value = readl(ioaddr);
+
+ value &= ~bit_mask;
+ writel(value, ioaddr);
+}
+
+static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
+{
+ u32 value = readl(ioaddr);
+
+ return (value & bit_mask) ? 1 : 0;
+}
+
+/*
+ * This function uses the memory initialization block in the Arria10 ECC
+ * controller to initialize/clear the entire memory data and ECC data.
+ */
+static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
+{
+ int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
+ u32 init_mask, stat_mask, clear_mask;
+ int ret = 0;
+
+ if (port) {
+ init_mask = ALTR_A10_ECC_INITB;
+ stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
+ clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
+ } else {
+ init_mask = ALTR_A10_ECC_INITA;
+ stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
+ clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
+ }
+
+ ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
+ while (limit--) {
+ if (ecc_test_bits(stat_mask,
+ (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
+ break;
+ udelay(1);
+ }
+ if (limit < 0)
+ ret = -EBUSY;
+
+ /* Clear any pending ECC interrupts */
+ writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
+
+ return ret;
+}
+
+static __init int __maybe_unused
+altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
+ u32 ecc_ctrl_en_mask, bool dual_port)
+{
+ int ret = 0;
+ void __iomem *ecc_block_base;
+ struct regmap *ecc_mgr_map;
+ char *ecc_name;
+ struct device_node *np_eccmgr;
+
+ ecc_name = (char *)np->name;
+
+ /* Get the ECC Manager - parent of the device EDACs */
+ np_eccmgr = of_get_parent(np);
+ ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
+ "altr,sysmgr-syscon");
+ of_node_put(np_eccmgr);
+ if (IS_ERR(ecc_mgr_map)) {
+ edac_printk(KERN_ERR, EDAC_DEVICE,
+ "Unable to get syscon altr,sysmgr-syscon\n");
+ return -ENODEV;
+ }
+
+ /* Map the ECC Block */
+ ecc_block_base = of_iomap(np, 0);
+ if (!ecc_block_base) {
+ edac_printk(KERN_ERR, EDAC_DEVICE,
+ "Unable to map %s ECC block\n", ecc_name);
+ return -ENODEV;
+ }
+
+ /* Disable ECC */
+ regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
+ writel(ALTR_A10_ECC_SERRINTEN,
+ (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
+ ecc_clear_bits(ecc_ctrl_en_mask,
+ (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
+ /* Ensure all writes complete */
+ wmb();
+ /* Use HW initialization block to initialize memory for ECC */
+ ret = altr_init_memory_port(ecc_block_base, 0);
+ if (ret) {
+ edac_printk(KERN_ERR, EDAC_DEVICE,
+ "ECC: cannot init %s PORTA memory\n", ecc_name);
+ goto out;
+ }
+
+ if (dual_port) {
+ ret = altr_init_memory_port(ecc_block_base, 1);
+ if (ret) {
+ edac_printk(KERN_ERR, EDAC_DEVICE,
+ "ECC: cannot init %s PORTB memory\n",
+ ecc_name);
+ goto out;
+ }
+ }
+
+ /* Interrupt mode set to every SBERR */
+ regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
+ ALTR_A10_ECC_INTMODE);
+ /* Enable ECC */
+ ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
+ ALTR_A10_ECC_CTRL_OFST));
+ writel(ALTR_A10_ECC_SERRINTEN,
+ (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
+ regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
+ /* Ensure all writes complete */
+ wmb();
+out:
+ iounmap(ecc_block_base);
+ return ret;
+}
+
+static int validate_parent_available(struct device_node *np);
+static const struct of_device_id altr_edac_a10_device_of_match[];
+static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
+{
+ int irq;
+ struct device_node *child, *np = of_find_compatible_node(NULL, NULL,
+ "altr,socfpga-a10-ecc-manager");
+ if (!np) {
+ edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
+ return -ENODEV;
+ }
+
+ for_each_child_of_node(np, child) {
+ const struct of_device_id *pdev_id;
+ const struct edac_device_prv_data *prv;
+
+ if (!of_device_is_available(child))
+ continue;
+ if (!of_device_is_compatible(child, compat))
+ continue;
+
+ if (validate_parent_available(child))
+ continue;
+
+ irq = a10_get_irq_mask(child);
+ if (irq < 0)
+ continue;
+
+ /* Get matching node and check for valid result */
+ pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
+ if (IS_ERR_OR_NULL(pdev_id))
+ continue;
+
+ /* Validate private data pointer before dereferencing */
+ prv = pdev_id->data;
+ if (!prv)
+ continue;
+
+ altr_init_a10_ecc_block(child, BIT(irq),
+ prv->ecc_enable_mask, 0);
+ }
+
+ of_node_put(np);
+ return 0;
+}
+
/*********************** OCRAM EDAC Device Functions *********************/
#ifdef CONFIG_EDAC_ALTERA_OCRAM
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index cf4e8cb..aa7c690 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -230,8 +230,13 @@ struct altr_sdram_mc_data {
#define ALTR_A10_ECC_INITCOMPLETEB BIT(8)
#define ALTR_A10_ECC_ERRINTEN_OFST 0x10
+#define ALTR_A10_ECC_ERRINTENS_OFST 0x14
+#define ALTR_A10_ECC_ERRINTENR_OFST 0x18
#define ALTR_A10_ECC_SERRINTEN BIT(0)
+#define ALTR_A10_ECC_INTMODE_OFST 0x1C
+#define ALTR_A10_ECC_INTMODE BIT(0)
+
#define ALTR_A10_ECC_INTSTAT_OFST 0x20
#define ALTR_A10_ECC_SERRPENA BIT(0)
#define ALTR_A10_ECC_DERRPENA BIT(8)
@@ -280,6 +285,9 @@ struct altr_sdram_mc_data {
/* Arria 10 OCRAM ECC Management Group Defines */
#define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
+/* A10 ECC Controller memory initialization timeout */
+#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
+
struct altr_edac_device_dev;
struct edac_device_prv_data {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCHv4 6/7] EDAC, altera: Add Arria10 Ethernet EDAC support
2016-06-20 14:50 [PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions tthayer
` (4 preceding siblings ...)
2016-06-20 14:50 ` [PATCHv4 5/7] EDAC, altera: Add Arria10 ECC memory init functions tthayer
@ 2016-06-20 14:50 ` tthayer
2016-06-20 14:50 ` [PATCHv4 7/7] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry tthayer
6 siblings, 0 replies; 12+ messages in thread
From: tthayer @ 2016-06-20 14:50 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
v3 Use common compatiblity string.
Simplify socfpga_init_ethernet_ecc().
v4 Make private data static.
Rename Ethernet private data to more generic name.
Remove panic field initialization.
Rename EN mask field to ALTR_A10_COMMON_ECC_EN_CTL
---
drivers/edac/Kconfig | 7 +++++++
drivers/edac/altera_edac.c | 37 +++++++++++++++++++++++++++++++++++--
drivers/edac/altera_edac.h | 3 +++
3 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 6ca7474..d0c1dab 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -391,6 +391,13 @@ config EDAC_ALTERA_OCRAM
Support for error detection and correction on the
Altera On-Chip RAM Memory for Altera SoCs.
+config EDAC_ALTERA_ETHERNET
+ bool "Altera Ethernet FIFO ECC"
+ depends on EDAC_ALTERA=y
+ help
+ Support for error detection and correction on the
+ Altera Ethernet FIFO Memory for Altera SoCs.
+
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index d97f22e..c4e3d0f 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1258,6 +1258,33 @@ static const struct edac_device_prv_data a10_l2ecc_data = {
#endif /* CONFIG_EDAC_ALTERA_L2C */
+/********************* Ethernet Device Functions ********************/
+
+#ifdef CONFIG_EDAC_ALTERA_ETHERNET
+
+static const struct edac_device_prv_data a10_enetecc_data = {
+ .setup = altr_check_ecc_deps,
+ .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
+ .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
+ .dbgfs_name = "altr_trigger",
+ .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
+ .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
+ .ce_set_mask = ALTR_A10_ECC_TSERRA,
+ .ue_set_mask = ALTR_A10_ECC_TDERRA,
+ .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+ .ecc_irq_handler = altr_edac_a10_ecc_irq,
+ .inject_fops = &altr_edac_a10_device_inject_fops,
+};
+
+static int __init socfpga_init_ethernet_ecc(void)
+{
+ return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
+}
+
+early_initcall(socfpga_init_ethernet_ecc);
+
+#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
+
/********************* Arria10 EDAC Device Functions *************************/
static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_L2C
@@ -1267,6 +1294,10 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
{ .compatible = "altr,socfpga-a10-ocram-ecc",
.data = &a10_ocramecc_data },
#endif
+#ifdef CONFIG_EDAC_ALTERA_ETHERNET
+ { .compatible = "altr,socfpga-eth-mac-ecc",
+ .data = &a10_enetecc_data },
+#endif
{},
};
MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
@@ -1555,8 +1586,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
continue;
if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
altr_edac_a10_device_add(edac, child);
- else if (of_device_is_compatible(child,
- "altr,socfpga-a10-ocram-ecc"))
+ else if ((of_device_is_compatible(child,
+ "altr,socfpga-a10-ocram-ecc")) ||
+ (of_device_is_compatible(child,
+ "altr,socfpga-eth-mac-ecc")))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
"altr,sdram-edac-a10"))
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index aa7c690..687d8e7 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -285,6 +285,9 @@ struct altr_sdram_mc_data {
/* Arria 10 OCRAM ECC Management Group Defines */
#define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
+/* Arria 10 Ethernet ECC Management Group Defines */
+#define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
+
/* A10 ECC Controller memory initialization timeout */
#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCHv4 7/7] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry
2016-06-20 14:50 [PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions tthayer
` (5 preceding siblings ...)
2016-06-20 14:50 ` [PATCHv4 6/7] EDAC, altera: Add Arria10 Ethernet EDAC support tthayer
@ 2016-06-20 14:50 ` tthayer
6 siblings, 0 replies; 12+ messages in thread
From: tthayer @ 2016-06-20 14:50 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2 No change
v3 Add interrupts for SBERR and DBERR.
v4 No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 21f6c3c..5cf4dc5 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -628,6 +628,22 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
<33 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ emac0-rx-ecc@ff8c0800 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0800 0x400>;
+ parent = <&gmac0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+ <36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-tx-ecc@ff8c0c00 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0c00 0x400>;
+ parent = <&gmac0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+ <37 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
rst: rstmgr@ffd05000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 12+ messages in thread