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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register
Date: Wed, 6 May 2020 12:05:50 +0530	[thread overview]
Message-ID: <7116fd7d-eb16-c5c4-c8e4-ffdc71b0983c@arm.com> (raw)
In-Reply-To: <f5e8b407-c731-7ff9-df47-fc54182f2d25@arm.com>



On 05/05/2020 10:29 AM, Suzuki K Poulose wrote:
> On 05/02/2020 02:33 PM, Anshuman Khandual wrote:
>> Enable MPAM and SEL2 features bits in ID_AA64PFR0 register as per ARM DDI
>> 0487F.a specification.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>>
>> Suggested-by: Will Deacon <will@kernel.org>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   arch/arm64/include/asm/sysreg.h | 2 ++
>>   arch/arm64/kernel/cpufeature.c  | 2 ++
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 40eaf89f1032..c93ea6613f51 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -641,6 +641,8 @@
>>   #define ID_AA64PFR0_CSV2_SHIFT        56
>>   #define ID_AA64PFR0_DIT_SHIFT        48
>>   #define ID_AA64PFR0_AMU_SHIFT        44
>> +#define ID_AA64PFR0_MPAM_SHIFT        40
>> +#define ID_AA64PFR0_SEL2_SHIFT        36
>>   #define ID_AA64PFR0_SVE_SHIFT        32
>>   #define ID_AA64PFR0_RAS_SHIFT        28
>>   #define ID_AA64PFR0_GIC_SHIFT        24
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index dbedcae28061..f5a39e040804 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -217,6 +217,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
>>       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
>> +    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
> 
> Both of them must be hidden. And also need to check the impact of exposing this to the guests, especially MPAM.

Just trying to understand. We should make both MPAM and SEL2, FTR_HIDDEN for
now, in which case they should not be visible to the userspace or guests. But
we would need to check impact of their exposure to guests before they can be
made visible later on. Is that correct ?

  reply	other threads:[~2020-05-06  6:36 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-02 13:33 [PATCH V3 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-04 20:24   ` Will Deacon
2020-05-05  6:50     ` Anshuman Khandual
2020-05-05 10:42       ` Will Deacon
2020-05-08  4:25         ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-05 11:10   ` Will Deacon
2020-05-08  4:59     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-05 11:12   ` Will Deacon
2020-05-05 11:16     ` Mark Rutland
2020-05-05 11:18       ` Mark Rutland
2020-05-05 11:27       ` Will Deacon
2020-05-05 11:50         ` Mark Rutland
2020-05-05 12:12           ` Will Deacon
2020-05-05 12:49             ` Mark Rutland
2020-05-08  8:32     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-03 21:35   ` Suzuki K Poulose
2020-05-02 13:33 ` [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-04 20:33   ` Will Deacon
2020-05-05  7:01     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-05 11:14   ` Will Deacon
2020-05-06  6:43     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-05  4:54   ` Suzuki K Poulose
2020-05-05  7:06     ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-05  4:59   ` Suzuki K Poulose
2020-05-06  6:35     ` Anshuman Khandual [this message]
2020-05-02 13:34 ` [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-05  9:24   ` Suzuki K Poulose
2020-05-06  6:33     ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual

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