From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
mark.rutland@arm.com, james.morse@arm.com,
kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 CPU register
Date: Sun, 3 May 2020 22:35:42 +0100 [thread overview]
Message-ID: <baaccab1-4f54-bc86-4244-2dc981b2dc90@arm.com> (raw)
In-Reply-To: <1588426445-24344-6-git-send-email-anshuman.khandual@arm.com>
On 05/02/2020 02:33 PM, Anshuman Khandual wrote:
> This adds basic building blocks required for ID_DFR1 CPU register which
> provides top level information about the debug system in AArch32 state.
> This is added per ARM DDI 0487F.a specification.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: kvmarm@lists.cs.columbia.edu
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Suggested-by: Will Deacon <will@kernel.org>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/include/asm/cpu.h | 1 +
> arch/arm64/include/asm/sysreg.h | 3 +++
> arch/arm64/kernel/cpufeature.c | 10 ++++++++++
> arch/arm64/kernel/cpuinfo.c | 1 +
> arch/arm64/kvm/sys_regs.c | 2 +-
> 5 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index 464e828a994d..d9a78bdec409 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -33,6 +33,7 @@ struct cpuinfo_arm64 {
> u64 reg_id_aa64zfr0;
>
> u32 reg_id_dfr0;
> + u32 reg_id_dfr1;
> u32 reg_id_isar0;
> u32 reg_id_isar1;
> u32 reg_id_isar2;
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c977449e02db..2e1e922e1409 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -154,6 +154,7 @@
> #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
> #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
> #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
> +#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
>
> #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
> #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
> @@ -763,6 +764,8 @@
> #define ID_ISAR4_WITHSHIFTS_SHIFT 4
> #define ID_ISAR4_UNPRIV_SHIFT 0
>
> +#define ID_DFR1_MTPMU_SHIFT 0
> +
> #define ID_ISAR0_DIVIDE_SHIFT 24
> #define ID_ISAR0_DEBUG_SHIFT 20
> #define ID_ISAR0_COPROC_SHIFT 16
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index a8247bf92959..2ce952d9668d 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -451,6 +451,11 @@ static const struct arm64_ftr_bits ftr_id_dfr0[] = {
> ARM64_FTR_END,
> };
>
> +static const struct arm64_ftr_bits ftr_id_dfr1[] = {
> + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
> - ID_UNALLOCATED(3,5),
> + ID_SANITISED(ID_DFR1_EL1),
> ID_UNALLOCATED(3,6),
> ID_UNALLOCATED(3,7),
>
IIUC, we should not expose the MTPMU to the KVM guests. Either we could
drop this entire patch, or we should emulate the MTPMU to 0 in KVM.
Suzuki
next prev parent reply other threads:[~2020-05-03 21:30 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-02 13:33 [PATCH V3 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-04 20:24 ` Will Deacon
2020-05-05 6:50 ` Anshuman Khandual
2020-05-05 10:42 ` Will Deacon
2020-05-08 4:25 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-05 11:10 ` Will Deacon
2020-05-08 4:59 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-05 11:12 ` Will Deacon
2020-05-05 11:16 ` Mark Rutland
2020-05-05 11:18 ` Mark Rutland
2020-05-05 11:27 ` Will Deacon
2020-05-05 11:50 ` Mark Rutland
2020-05-05 12:12 ` Will Deacon
2020-05-05 12:49 ` Mark Rutland
2020-05-08 8:32 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-03 21:35 ` Suzuki K Poulose [this message]
2020-05-02 13:33 ` [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-04 20:33 ` Will Deacon
2020-05-05 7:01 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-05 11:14 ` Will Deacon
2020-05-06 6:43 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-05 4:54 ` Suzuki K Poulose
2020-05-05 7:06 ` Anshuman Khandual
2020-05-02 13:33 ` [PATCH V3 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-05 4:59 ` Suzuki K Poulose
2020-05-06 6:35 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-05 9:24 ` Suzuki K Poulose
2020-05-06 6:33 ` Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-02 13:34 ` [PATCH V3 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
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