From: Thomas Gleixner <tglx@linutronix.de>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: peterlin@andestech.com, acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
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conor+dt@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org, Evan Green <evan@rivosinc.com>,
geert+renesas@glider.be, guoren@kernel.org,
Heiko Stuebner <heiko@sntech.de>,
irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org,
jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
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Paul Walmsley <paul.walmsley@sifive.com>,
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robh+dt@kernel.org, samuel@sholland.org,
Sunil V L <sunilvl@ventanamicro.com>,
tim609@andestech.com, uwu@icenowy.me, wens@csie.org,
Will Deacon <will@kernel.org>,
inochiama@outlook.com, unicorn_wang@outlook.com, wefu@redhat.com,
randolph@andestech.com
Subject: Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
Date: Tue, 12 Mar 2024 15:28:04 +0100 [thread overview]
Message-ID: <871q8fplsb.ffs@tglx> (raw)
In-Reply-To: <mhng-d47edbdb-0a36-4adb-9575-8af094d80e5e@palmer-ri-x1c9>
On Tue, Mar 12 2024 at 07:23, Palmer Dabbelt wrote:
> On Fri, 23 Feb 2024 01:06:44 PST (-0800), tglx@linutronix.de wrote:
>> Contains:
>>
>> f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
>> 96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
>>
>> on top of v6.8-rc1
>
> Sorry I missed this. I just merged this into my testing tree, it might
> take a bit to show up because I've managed to break my VPN so I can't
> poke the tester box right now...
Alternatively you can just rebase on Linus tree. The interrupt changes
are already merged.
next prev parent reply other threads:[~2024-03-12 14:28 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-02-22 21:33 ` Thomas Gleixner
2024-02-23 9:44 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-02-22 21:36 ` Thomas Gleixner
2024-02-23 8:49 ` Thomas Gleixner
2024-02-23 8:54 ` Thomas Gleixner
2024-02-23 9:06 ` Thomas Gleixner
2024-03-12 14:23 ` Palmer Dabbelt
2024-03-12 14:28 ` Thomas Gleixner [this message]
2024-02-23 9:43 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-02-26 12:27 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-02-26 12:28 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv
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