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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: acme@kernel.org, adrian.hunter@intel.com,
	ajones@ventanamicro.com,  alexander.shishkin@linux.intel.com,
	andre.przywara@arm.com,  anup@brainfault.org,
	aou@eecs.berkeley.edu, atishp@atishpatra.org,
	 conor+dt@kernel.org, conor.dooley@microchip.com,
	conor@kernel.org,  devicetree@vger.kernel.org, evan@rivosinc.com,
	geert+renesas@glider.be,  guoren@kernel.org, heiko@sntech.de,
	irogers@google.com,  jernej.skrabec@gmail.com, jolsa@kernel.org,
	jszhang@kernel.org,  krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org,
	 linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	 linux-renesas-soc@vger.kernel.org,
	linux-riscv@lists.infradead.org,  linux-sunxi@lists.linux.dev,
	locus84@andestech.com, magnus.damm@gmail.com,
	 mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
	 namhyung@kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com,  peterz@infradead.org,
	prabhakar.mahadev-lad.rj@bp.renesas.com,  rdunlap@infradead.org,
	robh+dt@kernel.org, samuel@sholland.org,
	 sunilvl@ventanamicro.com, tglx@linutronix.de,
	tim609@andestech.com,  uwu@icenowy.me, wens@csie.org,
	will@kernel.org, inochiama@outlook.com,
	 unicorn_wang@outlook.com, wefu@redhat.com
Subject: Re: [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
Date: Mon, 26 Feb 2024 13:28:16 +0100	[thread overview]
Message-ID: <CAMuHMdV7f_R-_OiP-18rQATVdnS-1yo_kT++O=e1KuUSfeiygw@mail.gmail.com> (raw)
In-Reply-To: <20240222083946.3977135-10-peterlin@andestech.com>

On Thu, Feb 22, 2024 at 9:41 AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
> xandespmu stands for Andes Performance Monitor Unit extension.
> Based on the added Andes PMU ISA string, the SBI PMU driver
> will make use of the non-standard irq source.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Changes v1 -> v2:
>   - New patch
> Changes v2 -> v3:
>   - No change
> Changes v3 -> v4:
>   - No change
> Changes v4 -> v5:
>   - Include Geert's Reviewed-by
>   - Include Prabhakar's Reviewed/Tested-by
> Changes v5 -> v6:
>   - Include Conor's Acked-by
> Changes v6 -> v7:
>   - No change
> Changes v7 -> v8:
>   - No change
> Changes v8 -> v9:
>   - No change

Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
so Palmer can pick it up with the rest of the series
(the Renesas tree merge window for v6.9 has closed)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2024-02-26 12:28 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-22  8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-02-22 21:33   ` Thomas Gleixner
2024-02-23  9:44   ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-02-22 21:36   ` Thomas Gleixner
2024-02-23  8:49     ` Thomas Gleixner
2024-02-23  8:54       ` Thomas Gleixner
2024-02-23  9:06         ` Thomas Gleixner
2024-03-12 14:23           ` Palmer Dabbelt
2024-03-12 14:28             ` Thomas Gleixner
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-02-26 12:27   ` Geert Uytterhoeven
2024-02-22  8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-02-26 12:28   ` Geert Uytterhoeven [this message]
2024-02-22  8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv

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