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From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
	acme@kernel.org, adrian.hunter@intel.com,
	ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
	andre.przywara@arm.com, anup@brainfault.org,
	aou@eecs.berkeley.edu, atishp@atishpatra.org,
	conor+dt@kernel.org, conor.dooley@microchip.com,
	conor@kernel.org, devicetree@vger.kernel.org, evan@rivosinc.com,
	geert+renesas@glider.be, guoren@kernel.org, heiko@sntech.de,
	irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org,
	jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
	locus84@andestech.com, magnus.damm@gmail.com,
	mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
	namhyung@kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, peterlin@andestech.com,
	peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com,
	rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org,
	sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me,
	wens@csie.org, will@kernel.org, inochiama@outlook.com,
	unicorn_wang@outlook.com, wefu@redhat.com
Cc: Randolph <randolph@andestech.com>
Subject: Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
Date: Fri, 23 Feb 2024 09:54:48 +0100	[thread overview]
Message-ID: <874jdzef1j.ffs@tglx> (raw)
In-Reply-To: <877civefa5.ffs@tglx>

On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>> Palmer, feel free to take this through the riscv tree. I have no other
>> changes pending against that driver.
>
> Aargh. Spoken too early. This conflicts with Anups AIA series.
>
>   https://lore.kernel.org/all/20240222094006.1030709-1-apatel@ventanamicro.com
>
> So I rather take the pile through my tree and deal with the conflicts
> localy than inflicting it on next.

> Palmer?

Nah. I just apply the two intc patches localy and give you a tag to pull
from so we carry both the same commits. Then I can deal with the
conflicts on my side trivially.

Thanks,

        tglx

  reply	other threads:[~2024-02-23  8:54 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-22  8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-02-22 21:33   ` Thomas Gleixner
2024-02-23  9:44   ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-02-22 21:36   ` Thomas Gleixner
2024-02-23  8:49     ` Thomas Gleixner
2024-02-23  8:54       ` Thomas Gleixner [this message]
2024-02-23  9:06         ` Thomas Gleixner
2024-03-12 14:23           ` Palmer Dabbelt
2024-03-12 14:28             ` Thomas Gleixner
2024-02-23  9:43   ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-02-26 12:27   ` Geert Uytterhoeven
2024-02-22  8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin
2024-02-22  8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-02-26 12:28   ` Geert Uytterhoeven
2024-02-22  8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv

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