From: Thomas Gleixner <tglx@linutronix.de>
To: Yu Chien Peter Lin <peterlin@andestech.com>,
acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
aou@eecs.berkeley.edu, atishp@atishpatra.org,
conor+dt@kernel.org, conor.dooley@microchip.com,
conor@kernel.org, devicetree@vger.kernel.org, evan@rivosinc.com,
geert+renesas@glider.be, guoren@kernel.org, heiko@sntech.de,
irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org,
jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
locus84@andestech.com, magnus.damm@gmail.com,
mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com,
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paul.walmsley@sifive.com, peterlin@andestech.com,
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rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org,
sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me,
wens@csie.org, will@kernel.org, inochiama@outlook.com,
unicorn_wang@outlook.com, wefu@redhat.com
Cc: Randolph <randolph@andestech.com>
Subject: Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
Date: Thu, 22 Feb 2024 22:36:47 +0100 [thread overview]
Message-ID: <87o7c8dvv4.ffs@tglx> (raw)
In-Reply-To: <20240222083946.3977135-4-peterlin@andestech.com>
On Thu, Feb 22 2024 at 16:39, Yu Chien Peter Lin wrote:
> Add support for the Andes hart-level interrupt controller. This
> controller provides interrupt mask/unmask functions to access the
> custom register (SLIE) where the non-standard S-mode local interrupt
> enable bits are located. The base of custom interrupt number is set
> to 256.
>
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> passed to the irq_domain_set_info() as a private data.
>
> Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> compatible string to be present in interrupt-controller of cpu node to
> enable the use of custom local interrupt source.
> e.g.,
>
> cpu0: cpu@0 {
> compatible = "andestech,ax45mp", "riscv";
> ...
> cpu0-intc: interrupt-controller {
> #interrupt-cells = <0x01>;
> compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> interrupt-controller;
> };
> };
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Randolph <randolph@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Palmer, feel free to take this through the riscv tree. I have no other
changes pending against that driver.
Thanks,
tglx
next prev parent reply other threads:[~2024-02-22 21:36 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-22 8:39 [PATCH v9 00/10] Support Andes PMU extension Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 01/10] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-02-22 21:33 ` Thomas Gleixner
2024-02-23 9:44 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-02-22 21:36 ` Thomas Gleixner [this message]
2024-02-23 8:49 ` Thomas Gleixner
2024-02-23 8:54 ` Thomas Gleixner
2024-02-23 9:06 ` Thomas Gleixner
2024-03-12 14:23 ` Palmer Dabbelt
2024-03-12 14:28 ` Thomas Gleixner
2024-02-23 9:43 ` [tip: irq/msi] " tip-bot2 for Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-02-26 12:27 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 08/10] dt-bindings: riscv: Add Andes PMU extension description Yu Chien Peter Lin
2024-02-22 8:39 ` [PATCH v9 09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-02-26 12:28 ` Geert Uytterhoeven
2024-02-22 8:39 ` [PATCH v9 10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-03-14 12:30 ` [PATCH v9 00/10] Support Andes PMU extension patchwork-bot+linux-riscv
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