From: Robert Jarzmik <robert.jarzmik@free.fr>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Nicolas Pitre <nico@fluxnic.net>,
Russell King - ARM Linux <linux@armlinux.org.uk>,
Arnd Bergmann <arnd@arndb.de>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] net: smsc911x: add u16 workaround for pxa platforms
Date: Thu, 06 Oct 2016 08:47:13 +0200 [thread overview]
Message-ID: <87lgy27z4e.fsf@belgarion.home> (raw)
In-Reply-To: <871szx9rhc.fsf@belgarion.home> (Robert Jarzmik's message of "Mon, 03 Oct 2016 21:12:31 +0200")
Robert Jarzmik <robert.jarzmik@free.fr> writes:
> Mark Rutland <mark.rutland@arm.com> writes:
>
>> On Mon, Oct 03, 2016 at 06:11:23PM +0200, Robert Jarzmik wrote:
>>> Mark Rutland <mark.rutland@arm.com> writes:
>>>
>>> reg-u16-align4 tells that a specific hardware doesn't support 16 bit writes not
>>> being 32 bits aligned, or said differently that a "store" 16 bits wide on an
>>> address of the format 4*n + 2 deserves a special handling in the driver, while a
>>> store 16 bits wide on an address of the format 4*n can follow the simple casual
>>> case.
>>
>> If I've understood correctly, effectively the low 2 address lines to the
>> device are hard-wired to zero, e.g. a 16-bit access to 4*n + 2 would go
>> to 4*n + 0 on the device? Or is the failure case distinct from that?
> It is distinct.
>
> The "awful truth" is that an FPGA lies between the system bus and the
> smc91c111. And this FPGA cannot handle correctly the 4*n + 2 u16 writes.
>
>> Do we have other platforms where similar is true? e.g. u8 accesses
>> requiring 16-bit alignment?
>
> Not really, ie. not with a alignement requirement.
>
> But there are of course these ones are handled by reg-io-width and the
> SMC_USE_xxx_BITS flags as far as I understand it. These cases are when a
> platform declares SMC91X_USE_16BIT or SMC91X_USE_32BIT, but not SMC91X_USE_8BIT,
> which would make me think of :
> - CONFIG_SH_SH4202_MICRODEV,
> - CONFIG_M32R
> - several omap1 boards
> - 1 sa1100 board
> - several MMP and realview boards
>
> With all these platforms, each u8 access is replaced with a u16 access and a
> mask / shift + mask.
Or so what should I call this entry if reg-u16-align4 is not a good candidate ?
Cheers.
--
Robert
next prev parent reply other threads:[~2016-10-06 6:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-03 9:05 [PATCH 1/3] net: smc91x: isolate u16 writes alignment workaround Robert Jarzmik
2016-10-03 9:05 ` [PATCH 2/3] net: smc91x: take into account half-word workaround Robert Jarzmik
2016-10-03 9:05 ` [PATCH 3/3] net: smsc911x: add u16 workaround for pxa platforms Robert Jarzmik
2016-10-03 15:21 ` Jeremy Linton
2016-10-03 16:14 ` Robert Jarzmik
2016-10-03 15:46 ` Mark Rutland
2016-10-03 16:09 ` Russell King - ARM Linux
2016-10-03 16:42 ` Mark Rutland
2016-10-09 1:28 ` Rob Herring
2016-10-03 16:11 ` Robert Jarzmik
2016-10-03 16:50 ` Mark Rutland
2016-10-03 19:12 ` Robert Jarzmik
2016-10-06 6:47 ` Robert Jarzmik [this message]
2016-10-09 1:28 ` Rob Herring
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