From: Michael Walle <michael@walle.cc>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
netdev@vger.kernel.org, Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>
Subject: Re: [RFC PATCH 3/3] net: phy: at803x: add device tree binding
Date: Sat, 02 Nov 2019 02:18:27 +0100 [thread overview]
Message-ID: <9de3e32f081c9b2d1227514b4e9f166e@walle.cc> (raw)
In-Reply-To: <64c0dda8-d428-643e-5edf-ac5108c7ec5c@gmail.com>
Am 2019-10-31 18:35, schrieb Florian Fainelli:
> On 10/31/19 10:22 AM, Michael Walle wrote:
>> Am 2019-10-31 00:59, schrieb Michael Walle:
>>>>> +
>>>>> + if (of_property_read_bool(node, "atheros,keep-pll-enabled"))
>>>>> + priv->flags |= AT803X_KEEP_PLL_ENABLED;
>>>>
>>>> This should probably be a PHY tunable rather than a Device Tree
>>>> property
>>>> as this delves more into the policy than the pure hardware
>>>> description.
>>>
>>> To be frank. I'll first need to look into PHY tunables before
>>> answering ;)
>>> But keep in mind that this clock output might be used anywhere on the
>>> board. It must not have something to do with networking. The PHY has
>>> a
>>> crystal and it can generate these couple of frequencies regardless of
>>> its network operation.
>>
>> Although it could be used to provide any clock on the board, I don't
>> know
>> if that is possible at the moment, because the PHY is configured in
>> config_init() which is only called when someone brings the interface
>> up,
>> correct?
>>
>> Anyway, I don't know if that is worth the hassle because in almost all
>> cases the use case is to provide a fixed clock to the MAC for an RGMII
>> interface. I don't know if that really fits a PHY tunable, because in
>> the worst case the link won't work at all if the SoC expects an
>> always-on clock.
>
> Well, that was my question really, is the clock output being controlled
> the actual RXC that will feed back to the MAC or is this is another
> clock output pin (sorry if you indicated that before and I missed it)?
No it is not the RX clock. The PHY has three clock pins, RX clock, TX
clock and a general purpose CLK_25M pin.
> If this is the PHY's RXC, then does the configuration (DSP, PLL, XTAL)
> matter at all on the generated output frequency, or is this just a
> choice for the board designer, and whether the PHY is configured for
> MII/RGMII, it outputs the appropriate clock at 25/125Mhz?
The RXC changes the frequency according to the speed.
--
-michael
prev parent reply other threads:[~2019-11-02 1:18 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-30 22:42 [RFC PATCH 0/3] net: phy: at803x device tree binding Michael Walle
2019-10-30 22:42 ` [RFC PATCH 1/3] net: phy: at803x: fix Kconfig description Michael Walle
2019-10-30 23:13 ` Andrew Lunn
2019-10-30 23:16 ` Florian Fainelli
2019-10-30 23:18 ` Andrew Lunn
2019-10-30 23:32 ` Florian Fainelli
2019-10-31 0:05 ` Michael Walle
2019-10-30 22:42 ` [RFC PATCH 2/3] dt-bindings: net: phy: Add support for AT803X Michael Walle
2019-10-30 23:17 ` Andrew Lunn
2019-10-31 0:14 ` Michael Walle
2019-10-31 16:45 ` Florian Fainelli
2019-10-31 17:14 ` Michael Walle
2019-10-30 23:28 ` Florian Fainelli
2019-10-30 23:36 ` Michael Walle
2019-11-01 15:03 ` Simon Horman
2019-11-02 1:19 ` Michael Walle
2019-10-30 22:42 ` [RFC PATCH 3/3] net: phy: at803x: add device tree binding Michael Walle
2019-10-30 23:21 ` Andrew Lunn
2019-10-30 23:28 ` Florian Fainelli
2019-10-30 23:59 ` Michael Walle
2019-10-31 17:22 ` Michael Walle
2019-10-31 17:35 ` Florian Fainelli
2019-11-02 1:18 ` Michael Walle [this message]
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