From: Anup Patel <anup@brainfault.org>
To: Christoph Hellwig <hch@lst.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
palmer@sifive.com, jason@lakedaemon.net,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
linux-riscv@lists.infradead.org,
Stafford Horne <shorne@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 3/6] irqchip: RISC-V Local Interrupt Controller Driver
Date: Thu, 26 Jul 2018 19:09:57 +0530 [thread overview]
Message-ID: <CAAhSdy0JAmd=ma82yWTwQYMi2T-G8SLriV5tPyScWxOm8rCpjw@mail.gmail.com> (raw)
In-Reply-To: <20180726082706.GA22868@lst.de>
On Thu, Jul 26, 2018 at 1:57 PM, Christoph Hellwig <hch@lst.de> wrote:
> On Thu, Jul 26, 2018 at 09:08:00AM +0530, Anup Patel wrote:
>> Actually, RISCV HLIC and PLIC are very similar to RPi2 and RPi3 SOCs.
>>
>> On RPi2 and RPi3, we have per-CPU BCM2836 local intc and the global
>> interrupts are managed using BCM2835 intc. You should certainly have
>> a look a this drivers because these very simple compared to GICv2 and
>> GICv3 drivers.
>
> Yes, using that model makes writing the per-cpu irq controller driver
> trivial. But retrofitting it into the device tree, where the existing
> bootloader (bbl) assumes the old DT layout is a giant pain in the neck.
This can also be taken care in HLIC driver probe function with something
like below:
if (parent)
return 0;
if (of_is_compatible(parent, "riscv,cpu")) {
/*
* Legacy DT binding so we have HLIC DT node
* under each CPU DT node. To provide backwared
* compatiblity we go forward for only one HLIC
* DT node
*/
if (atomic_inc_return(&hlic_lottery) > 1)
return 0;
}
In PLIC driver probe, register nested IRQ handler for only first two
entries of interrupts-extended because it is HLIC IRQs are per-CPU. We
can happily ignore other entries in interrupts-extended of Legacy DTS.
>
> At the same time I'm still not conveninced RISC-V really needs a full
> irqchip driver for the per-cpu interrupt 'controller' really is nothing
> but 1 and a half architectural control registers:
>
> - the scause register that contains the reason for an exception
> (any exception including syscalls and page faults) for the entry
> into supervisor mode. This includes a bit to indicate interrupts,
> and then logical interrupt reason, out of which only three are
> interesting for supervisor mode (timer, software, external)
> - the sie register that allows to to enable/disable each of the above
> causes individually
Biggest plus is the ability show stats for per-CPU interrupts via
"cat /proc/interrupts" (just like other architectures).
Currently, we have only three per-CPU interrupts (timer, software,
and external) but in-future people might come-up with interesting
devices which might have per-CPU interrupts.
>
> So after burning out on DT hacking (never mind retrofitting that into
> actual shipping SOCs vs just qemu) I'm going to try a version that
> doesn't add an irqchip for this but just handles it hardcoded in
> RISC-V do_IRQ. I'll still keep the irqchip for the PLIC, which while
> specificed in the RISC-V spec isn't architectural but an actual
> periphal.
I believe it possible to have RICV HLIC driver which maintains
backward compatibility with legacy DTS. I haven't tried above
approach myself on QEMU so I will let you decide.
Regards,
Anup
next prev parent reply other threads:[~2018-07-26 13:40 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-25 9:36 RISC-V irqchip drivers Christoph Hellwig
2018-07-25 9:36 ` [PATCH 1/6] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-07-25 21:44 ` Palmer Dabbelt
2018-07-26 8:10 ` Christoph Hellwig
2018-07-25 9:36 ` [PATCH 2/6] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-07-25 21:44 ` Palmer Dabbelt
2018-07-25 9:36 ` [PATCH 3/6] irqchip: RISC-V Local Interrupt Controller Driver Christoph Hellwig
2018-07-25 11:18 ` Marc Zyngier
2018-07-25 11:24 ` Christoph Hellwig
2018-07-25 11:37 ` Marc Zyngier
2018-07-25 17:54 ` Atish Patra
2018-07-26 3:38 ` Anup Patel
2018-07-26 8:27 ` Christoph Hellwig
2018-07-26 13:39 ` Anup Patel [this message]
2018-08-01 18:55 ` Thomas Gleixner
2018-08-02 7:34 ` Christoph Hellwig
2018-08-02 9:35 ` Thomas Gleixner
2018-08-02 9:43 ` Christoph Hellwig
2018-08-02 9:44 ` Thomas Gleixner
2018-08-04 4:03 ` Palmer Dabbelt
2018-08-04 16:40 ` Thomas Gleixner
2018-07-25 9:36 ` [PATCH 4/6] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs Christoph Hellwig
2018-07-31 22:37 ` Rob Herring
2018-08-01 7:13 ` Christoph Hellwig
2018-08-01 18:14 ` Rob Herring
2018-07-25 9:36 ` [PATCH 5/6] irqchip: New RISC-V PLIC Driver Christoph Hellwig
2018-07-25 9:36 ` [PATCH 6/6] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-07-31 22:46 ` Rob Herring
2018-08-01 7:16 ` Christoph Hellwig
2018-08-01 18:26 ` Rob Herring
2018-08-02 9:55 ` Christoph Hellwig
2018-08-02 14:43 ` Rob Herring
2018-08-04 1:48 ` Palmer Dabbelt
2018-07-25 21:26 ` RISC-V irqchip drivers Palmer Dabbelt
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