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From: Thomas Gleixner <tglx@linutronix.de>
To: Christoph Hellwig <hch@lst.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	palmer@sifive.com, jason@lakedaemon.net, robh+dt@kernel.org,
	mark.rutland@arm.com, devicetree@vger.kernel.org,
	aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, shorne@gmail.com,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 3/6] irqchip: RISC-V Local Interrupt Controller Driver
Date: Wed, 1 Aug 2018 20:55:06 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.21.1808012049170.1835@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20180725112457.GA24502@lst.de>


On Wed, 25 Jul 2018, Christoph Hellwig wrote:

> On Wed, Jul 25, 2018 at 12:18:39PM +0100, Marc Zyngier wrote:
> > This feels odd. It means that you cannot have the following sequence:
> > 
> > 	local_irq_disable();
> > 	enable_irq(x); // where x is owned by a remote hart
> > 
> > as smp_call_function_single() requires interrupts to be enabled.
> > 
> > More fundamentally, why are you trying to make these interrupts look
> > global while they aren't? arm/arm64 have similar restrictions with GICv2
> > and earlier, and treats these interrupts as per-cpu.
> > 
> > Given that the drivers that deal with drivers connected to the per-hart
> > irqchip are themselves likely to be aware of the per-cpu aspect, it
> > would make sense to align things (we've been through that same
> > discussion about the clocksource driver a few weeks back).
> 
> Right now the only direct consumers are said clocksource, the PLIC
> driver later in this series and the RISC-V arch IPI code.  None of them
> is going to do a manual enable_irq, so I guess the remote case of the
> code is simply dead code.  I'll take a look at converting them to
> per-cpu.  I guess the GICv2 driver is the best template?

Confused. The timer and the IPI are separate causes and have nothing to do
with the per cpu irq domain. That's what the low level interrupt handling
code tells me.

If I understand correctly then the per cpu irq domain is for device
interrupts, right? If so, then this simply cannot work and there is no way
to make it work with per cpu interrupts either.

Is there some high level documentation about the design (or the lack of) or
can someone give a concise explanation how this stuff is supposed to work?

Thanks,

	tglx

  parent reply	other threads:[~2018-08-01 18:55 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-25  9:36 RISC-V irqchip drivers Christoph Hellwig
2018-07-25  9:36 ` [PATCH 1/6] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-07-25 21:44   ` Palmer Dabbelt
2018-07-26  8:10     ` Christoph Hellwig
2018-07-25  9:36 ` [PATCH 2/6] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-07-25 21:44   ` Palmer Dabbelt
2018-07-25  9:36 ` [PATCH 3/6] irqchip: RISC-V Local Interrupt Controller Driver Christoph Hellwig
2018-07-25 11:18   ` Marc Zyngier
2018-07-25 11:24     ` Christoph Hellwig
2018-07-25 11:37       ` Marc Zyngier
2018-07-25 17:54         ` Atish Patra
2018-07-26  3:38       ` Anup Patel
2018-07-26  8:27         ` Christoph Hellwig
2018-07-26 13:39           ` Anup Patel
2018-08-01 18:55       ` Thomas Gleixner [this message]
2018-08-02  7:34         ` Christoph Hellwig
2018-08-02  9:35           ` Thomas Gleixner
2018-08-02  9:43             ` Christoph Hellwig
2018-08-02  9:44               ` Thomas Gleixner
2018-08-04  4:03         ` Palmer Dabbelt
2018-08-04 16:40           ` Thomas Gleixner
2018-07-25  9:36 ` [PATCH 4/6] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs Christoph Hellwig
2018-07-31 22:37   ` Rob Herring
2018-08-01  7:13     ` Christoph Hellwig
2018-08-01 18:14       ` Rob Herring
2018-07-25  9:36 ` [PATCH 5/6] irqchip: New RISC-V PLIC Driver Christoph Hellwig
2018-07-25  9:36 ` [PATCH 6/6] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-07-31 22:46   ` Rob Herring
2018-08-01  7:16     ` Christoph Hellwig
2018-08-01 18:26       ` Rob Herring
2018-08-02  9:55         ` Christoph Hellwig
2018-08-02 14:43           ` Rob Herring
2018-08-04  1:48         ` Palmer Dabbelt
2018-07-25 21:26 ` RISC-V irqchip drivers Palmer Dabbelt

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