From: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: hdegoede@redhat.com, mgross@linux.intel.com,
gayatri.kammela@intel.com, platform-driver-x86@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/9] platform/x86: intel_pmc_core: Don't use global pmcdev in quirks
Date: Wed, 7 Apr 2021 10:58:37 -0400 [thread overview]
Message-ID: <CAE2upjT143Co-e6G6Hjxr4VcnmFXbHm=nz7fF3Yg54ZK1Xx-oQ@mail.gmail.com> (raw)
In-Reply-To: <20210401030558.2301621-2-david.e.box@linux.intel.com>
Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
<david.e.box@linux.intel.com> wrote:
>
> The DMI callbacks, used for quirks, currently access the PMC by getting
> the address a global pmc_dev struct. Instead, have the callbacks set a
> global quirk specific variable. In probe, after calling dmi_check_system(),
> pass pmc_dev to a function that will handle each quirk if its variable
> condition is met. This allows removing the global pmc_dev later.
>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
> drivers/platform/x86/intel_pmc_core.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
> index b5888aeb4bcf..260d49dca1ad 100644
> --- a/drivers/platform/x86/intel_pmc_core.c
> +++ b/drivers/platform/x86/intel_pmc_core.c
> @@ -1186,9 +1186,15 @@ static const struct pci_device_id pmc_pci_ids[] = {
> * the platform BIOS enforces 24Mhz crystal to shutdown
> * before PMC can assert SLP_S0#.
> */
> +static bool xtal_ignore;
> static int quirk_xtal_ignore(const struct dmi_system_id *id)
> {
> - struct pmc_dev *pmcdev = &pmc;
> + xtal_ignore = true;
> + return 0;
> +}
> +
> +static void pmc_core_xtal_ignore(struct pmc_dev *pmcdev)
> +{
> u32 value;
>
> value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
> @@ -1197,7 +1203,6 @@ static int quirk_xtal_ignore(const struct dmi_system_id *id)
> /* Low Voltage Mode Enable */
> value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
> pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
> - return 0;
> }
>
> static const struct dmi_system_id pmc_core_dmi_table[] = {
> @@ -1212,6 +1217,14 @@ static const struct dmi_system_id pmc_core_dmi_table[] = {
> {}
> };
>
> +static void pmc_core_do_dmi_quirks(struct pmc_dev *pmcdev)
> +{
> + dmi_check_system(pmc_core_dmi_table);
> +
> + if (xtal_ignore)
> + pmc_core_xtal_ignore(pmcdev);
> +}
> +
> static int pmc_core_probe(struct platform_device *pdev)
> {
> static bool device_initialized;
> @@ -1253,7 +1266,7 @@ static int pmc_core_probe(struct platform_device *pdev)
> mutex_init(&pmcdev->lock);
> platform_set_drvdata(pdev, pmcdev);
> pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
> - dmi_check_system(pmc_core_dmi_table);
> + pmc_core_do_dmi_quirks(pmcdev);
>
> /*
> * On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when
> --
> 2.25.1
>
--
Thanks,
Rajneesh
next prev parent reply other threads:[~2021-04-07 14:59 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 3:05 [PATCH 0/9] intel_pmc_core: Add sub-state requirements and mode latching support David E. Box
2021-04-01 3:05 ` [PATCH 1/9] platform/x86: intel_pmc_core: Don't use global pmcdev in quirks David E. Box
2021-04-07 14:23 ` Hans de Goede
2021-04-07 14:58 ` Rajneesh Bhardwaj [this message]
2021-04-01 3:05 ` [PATCH 2/9] platform/x86: intel_pmc_core: Remove global struct pmc_dev David E. Box
2021-04-07 14:23 ` Hans de Goede
2021-04-07 15:02 ` Rajneesh Bhardwaj
2021-04-01 3:05 ` [PATCH 3/9] platform/x86: intel_pmc_core: Handle sub-states generically David E. Box
2021-04-07 14:23 ` Hans de Goede
2021-04-07 15:22 ` Rajneesh Bhardwaj
2021-04-01 3:05 ` [PATCH 4/9] platform/x86: intel_pmc_core: Show LPM residency in microseconds David E. Box
2021-04-07 14:23 ` Hans de Goede
2021-04-07 15:24 ` Rajneesh Bhardwaj
2021-04-01 3:05 ` [PATCH 5/9] platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake David E. Box
2021-04-07 14:27 ` Hans de Goede
2021-04-07 15:38 ` Rajneesh Bhardwaj
2021-04-01 3:05 ` [PATCH 6/9] platform/x86: intel_pmc_core: Add requirements file to debugfs David E. Box
2021-04-07 14:28 ` Hans de Goede
2021-04-07 15:45 ` Rajneesh Bhardwaj
2021-04-07 17:47 ` David E. Box
2021-04-01 3:05 ` [PATCH 7/9] platform/x86: intel_pmc_core: Add option to set/clear LPM mode David E. Box
2021-04-07 14:37 ` Hans de Goede
2021-04-07 17:19 ` David E. Box
2021-04-01 3:05 ` [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake David E. Box
2021-04-07 14:48 ` Hans de Goede
2021-04-07 15:48 ` Rajneesh Bhardwaj
2021-04-07 15:50 ` Rajneesh Bhardwaj
2021-04-01 3:05 ` [PATCH 9/9] platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P David E. Box
2021-04-07 14:48 ` Hans de Goede
2021-04-07 15:49 ` Rajneesh Bhardwaj
2021-04-07 14:49 ` [PATCH 0/9] intel_pmc_core: Add sub-state requirements and mode latching support Hans de Goede
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