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From: Hans de Goede <hdegoede@redhat.com>
To: "David E. Box" <david.e.box@linux.intel.com>,
	irenic.rajneesh@gmail.com, mgross@linux.intel.com,
	gayatri.kammela@intel.com
Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
Date: Wed, 7 Apr 2021 16:48:16 +0200	[thread overview]
Message-ID: <ba4f7edf-298a-2859-5421-b9356fc1985d@redhat.com> (raw)
In-Reply-To: <20210401030558.2301621-9-david.e.box@linux.intel.com>

Hi,

On 4/1/21 5:05 AM, David E. Box wrote:
> From: Gayatri Kammela <gayatri.kammela@intel.com>
> 
> Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information
> and supports a few additional registers. Hence add the LTR registers
> specific to Tiger Lake to the cnp_ltr_show_map[].
> 
> Also adjust the number of LTR IPs for Tiger Lake to the correct amount.
> 
> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>

Thanks, patch looks good to me:

Reviewed-by: Hans de Goede <hdegoede@redhat.com>

Regards,

Hans


> ---
>  drivers/platform/x86/intel_pmc_core.c | 2 ++
>  drivers/platform/x86/intel_pmc_core.h | 4 +++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
> index 458c0056e7a1..9168062c927e 100644
> --- a/drivers/platform/x86/intel_pmc_core.c
> +++ b/drivers/platform/x86/intel_pmc_core.c
> @@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
>  	 * a list of core SoCs using this.
>  	 */
>  	{"WIGIG",		ICL_PMC_LTR_WIGIG},
> +	{"THC0",                TGL_PMC_LTR_THC0},
> +	{"THC1",                TGL_PMC_LTR_THC1},
>  	/* Below two cannot be used for LTR_IGNORE */
>  	{"CURRENT_PLATFORM",	CNP_PMC_LTR_CUR_PLT},
>  	{"AGGREGATED_SYSTEM",	CNP_PMC_LTR_CUR_ASLT},
> diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
> index f41f61aa7008..634130b589a2 100644
> --- a/drivers/platform/x86/intel_pmc_core.h
> +++ b/drivers/platform/x86/intel_pmc_core.h
> @@ -192,8 +192,10 @@ enum ppfear_regs {
>  #define ETR3_CLEAR_LPM_EVENTS_BIT		28
>  #define LPM_STS_LATCH_MODE_BIT			31
>  
> -#define TGL_NUM_IP_IGN_ALLOWED			22
>  #define TGL_PMC_SLP_S0_RES_COUNTER_STEP		0x7A
> +#define TGL_PMC_LTR_THC0			0x1C04
> +#define TGL_PMC_LTR_THC1			0x1C08
> +#define TGL_NUM_IP_IGN_ALLOWED			23
>  #define TGL_PMC_LPM_RES_COUNTER_STEP_X2		61	/* 30.5us * 2 */
>  
>  /*
> 


  reply	other threads:[~2021-04-07 14:48 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-01  3:05 [PATCH 0/9] intel_pmc_core: Add sub-state requirements and mode latching support David E. Box
2021-04-01  3:05 ` [PATCH 1/9] platform/x86: intel_pmc_core: Don't use global pmcdev in quirks David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 14:58   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 2/9] platform/x86: intel_pmc_core: Remove global struct pmc_dev David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 15:02   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 3/9] platform/x86: intel_pmc_core: Handle sub-states generically David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 15:22   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 4/9] platform/x86: intel_pmc_core: Show LPM residency in microseconds David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 15:24   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 5/9] platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake David E. Box
2021-04-07 14:27   ` Hans de Goede
2021-04-07 15:38   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 6/9] platform/x86: intel_pmc_core: Add requirements file to debugfs David E. Box
2021-04-07 14:28   ` Hans de Goede
2021-04-07 15:45   ` Rajneesh Bhardwaj
2021-04-07 17:47     ` David E. Box
2021-04-01  3:05 ` [PATCH 7/9] platform/x86: intel_pmc_core: Add option to set/clear LPM mode David E. Box
2021-04-07 14:37   ` Hans de Goede
2021-04-07 17:19     ` David E. Box
2021-04-01  3:05 ` [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake David E. Box
2021-04-07 14:48   ` Hans de Goede [this message]
2021-04-07 15:48   ` Rajneesh Bhardwaj
2021-04-07 15:50     ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 9/9] platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P David E. Box
2021-04-07 14:48   ` Hans de Goede
2021-04-07 15:49   ` Rajneesh Bhardwaj
2021-04-07 14:49 ` [PATCH 0/9] intel_pmc_core: Add sub-state requirements and mode latching support Hans de Goede

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