From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Jian Hu <jian.hu@amlogic.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Rob Herring <robh@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
Victor Wan <victor.wan@amlogic.com>,
Chandle Zou <chandle.zou@amlogic.com>,
linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v6 2/5] clk: meson: add support for A1 PLL clock ops
Date: Sat, 18 Jan 2020 22:57:01 +0100 [thread overview]
Message-ID: <CAFBinCCkmUzNBeUz0k7na2FgR1SPKda81j+RnhEp9Jj84HEzmg@mail.gmail.com> (raw)
In-Reply-To: <20200116080440.118679-3-jian.hu@amlogic.com>
Hi Jian,
thank you for the update!
On Thu, Jan 16, 2020 at 9:04 AM Jian Hu <jian.hu@amlogic.com> wrote:
>
> Compared with the previous SoCs, self-adaption current module
> is newly added for A1, and there is no reset parm except the
> fixed pll. In A1 PLL, the PLL enable sequence is different, using
> the new power-on sequence to enable the PLL.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[...]
> @@ -323,13 +330,34 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
> return 0;
>
> /* Make sure the pll is in reset */
> - meson_parm_write(clk->map, &pll->rst, 1);
> + if (MESON_PARM_APPLICABLE(&pll->rst))
> + meson_parm_write(clk->map, &pll->rst, 1);
>
> /* Enable the pll */
> meson_parm_write(clk->map, &pll->en, 1);
>
> /* Take the pll out reset */
> - meson_parm_write(clk->map, &pll->rst, 0);
> + if (MESON_PARM_APPLICABLE(&pll->rst))
> + meson_parm_write(clk->map, &pll->rst, 0);
> +
> + /*
> + * Compared with the previous SoCs, self-adaption current module
> + * is newly added for A1, keep the new power-on sequence to enable the
> + * PLL. The sequence is:
> + * 1. enable the pll, delay for 10us
> + * 2. enable the pll self-adaption current module, delay for 40us
> + * 3. enable the lock detect module
> + */
> + if (MESON_PARM_APPLICABLE(&pll->current_en)) {
> + udelay(10);
> + meson_parm_write(clk->map, &pll->current_en, 1);
> + udelay(40);
note to myself: first I thought that these have to be converted to ulseep_range
BUT: clk_enable can be called from atomic context, so the atomic
versions (udelay instead of usleep/usleep_range) are perfectly fine in
Jian's patch
Martin
next prev parent reply other threads:[~2020-01-18 21:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-16 8:04 [PATCH v6 0/5] add Amlogic A1 clock controller driver Jian Hu
2020-01-16 8:04 ` [PATCH v6 1/5] dt-bindings: clock: meson: add A1 PLL clock controller bindings Jian Hu
2020-01-16 20:48 ` Rob Herring
2020-01-17 12:16 ` Jian Hu
2020-01-16 8:04 ` [PATCH v6 2/5] clk: meson: add support for A1 PLL clock ops Jian Hu
2020-01-18 21:57 ` Martin Blumenstingl [this message]
2020-01-16 8:04 ` [PATCH v6 3/5] clk: meson: a1: add support for Amlogic A1 PLL clock driver Jian Hu
2020-01-16 8:04 ` [PATCH v6 4/5] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Jian Hu
2020-01-16 8:04 ` [PATCH v6 5/5] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Jian Hu
2020-01-29 5:42 ` Stephen Boyd
2020-02-03 9:04 ` Jian Hu
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