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From: Linus Torvalds <torvalds@linux-foundation.org>
To: Al Viro <viro@zeniv.linux.org.uk>
Cc: Michael Ellerman <mpe@ellerman.id.au>,
	Christophe Leroy <christophe.leroy@c-s.fr>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	Peter Zijlstra <peterz@infradead.org>,
	"the arch/x86 maintainers" <x86@kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: objtool clac/stac handling change..
Date: Fri, 3 Jul 2020 18:54:15 -0700	[thread overview]
Message-ID: <CAHk-=whxLURD=qsF3ijmQYxGRPSyjS8_zoxZz-AsD-7tmRBM0w@mail.gmail.com> (raw)
In-Reply-To: <20200704004959.GY2786714@ZenIV.linux.org.uk>

On Fri, Jul 3, 2020 at 5:50 PM Al Viro <viro@zeniv.linux.org.uk> wrote:
>
>     How could prefetcht0 possibly
> raise an exception?  Intel manual says that the only exception is #UD if
> LOCK PREFETCHT0 is encountered; not here, obviously.  AMD manual simply
> says "no exceptions".  Confused...

Several CPU bugs in this area. I think they may all have been AMD.

But we've definitely had "prefetch causes page faults" errata.

Google for it. One pdf (AMD errata) I found had this:

 "Software Prefetches May Report A Page Fault

  Description Software prefetch instructions are defined to ignore
page faults. Under highly specific and detailed internal
circumstances, a prefetch instruction may report a page fault if both
of the following conditions are true:

   • The target address of the prefetch would cause a page fault if
the address was accessed by an actual memory load or store instruction
under the current privilege mode;

   • The prefetch instruction is followed in execution-order by an
actual or speculative byte-sized memory access of the same
modify-intent to the same address. PREFETCH and PREFETCHNTA/0/1/2 have
the same modify-intent as a memory load access.

  PREFETCHW has the same modify-intent as a memory store access. The
page fault exception error code bits for the faulting prefetch will be
identical to that for a bytesized memory access of the same-modify
intent to the same address. Note that some misaligned accesses can be
broken up by the processor into multiple accesses where at least one
of the accesses is a byte-sized access. If the target address of the
subsequent memory access of the same modify-intent is aligned and not
byte-sized, this errata does not occur and no workaround is needed.

  Potential Effect on System An unexpected page fault may occur
infrequently on a prefetch instruction."

So sadly the architecture manuals do not reflect reality.

That said, software prefetch instructions very seldom actually work.
They are only useful if you have one _very_ specific load and run one
one _very_ specific micrcoarchiecture.

Ir's almost always a mistake to have them in the first place.

            Linus

  reply	other threads:[~2020-07-04  1:54 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-01 18:22 objtool clac/stac handling change Linus Torvalds
2020-07-01 18:29 ` Andy Lutomirski
2020-07-01 19:35   ` Linus Torvalds
2020-07-01 20:36     ` Andy Lutomirski
2020-07-01 20:51       ` Josh Poimboeuf
2020-07-01 21:02         ` Linus Torvalds
2020-07-02  0:00           ` Josh Poimboeuf
2020-07-02  8:05             ` Peter Zijlstra
2020-07-01 20:51       ` Linus Torvalds
2020-07-02  0:47         ` Andy Lutomirski
2020-07-02  2:30           ` Linus Torvalds
2020-07-02  2:35             ` Linus Torvalds
2020-07-02  3:08             ` Andy Lutomirski
2020-07-01 18:41 ` Al Viro
2020-07-01 19:04   ` Linus Torvalds
2020-07-01 19:59     ` Al Viro
2020-07-01 20:25       ` Linus Torvalds
2020-07-02 13:34         ` Michael Ellerman
2020-07-02 14:01           ` Al Viro
2020-07-02 14:04             ` Al Viro
2020-07-02 15:13           ` Christophe Leroy
2020-07-02 20:13             ` Linus Torvalds
2020-07-03  3:59               ` Michael Ellerman
2020-07-03  3:17             ` Michael Ellerman
2020-07-03  5:27               ` Christophe Leroy
2020-07-02 19:52           ` Linus Torvalds
2020-07-02 20:17             ` Al Viro
2020-07-02 20:32               ` Linus Torvalds
2020-07-02 20:59                 ` Al Viro
2020-07-02 21:55                   ` Linus Torvalds
2020-07-03  1:33                     ` Al Viro
2020-07-03  3:32                       ` Linus Torvalds
2020-07-03 21:02                       ` Al Viro
2020-07-03 21:10                         ` Linus Torvalds
2020-07-03 21:41                           ` Andy Lutomirski
2020-07-03 22:25                             ` Al Viro
2020-07-03 21:59                           ` Al Viro
2020-07-03 22:04                             ` Al Viro
2020-07-03 22:12                           ` Al Viro
2020-07-04  0:49                         ` Al Viro
2020-07-04  1:54                           ` Linus Torvalds [this message]
2020-07-04  2:30                             ` Al Viro
2020-07-04  3:06                               ` Linus Torvalds
2020-07-04  2:11                           ` Al Viro
2020-07-07 12:35                             ` David Laight
2020-07-10 22:37                               ` Linus Torvalds
2020-07-13  9:32                                 ` David Laight

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