From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: "Michel Dänzer" <michel@daenzer.net>
Cc: Christoph Hellwig <hch@infradead.org>,
Will Deacon <will.deacon@arm.com>,
David Zhou <David1.Zhou@amd.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
David Airlie <airlied@linux.ie>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Michel Daenzer <michel.daenzer@amd.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
amd-gfx@lists.freedesktop.org, Junwei Zhang <Jerry.Zhang@amd.com>,
Huang Rui <ray.huang@amd.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
Daniel Vetter <daniel@ffwll.ch>,
Michael Ellerman <mpe@ellerman.id.au>,
Alex Deucher <alexander.deucher@amd.com>,
Sean Paul <sean@poorly.run>,
Christian Koenig <christian.koenig@amd.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86
Date: Mon, 21 Jan 2019 18:59:10 +0100 [thread overview]
Message-ID: <CAKv+Gu8OkbHwY5UBxahpQpM_gKh2331pQ6o-4YyJdLurbFNHvw@mail.gmail.com> (raw)
In-Reply-To: <59ccf85d-b99d-b5c8-ea87-66c2a892e197@daenzer.net>
On Mon, 21 Jan 2019 at 18:55, Michel Dänzer <michel@daenzer.net> wrote:
>
> On 2019-01-21 5:30 p.m., Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 17:22, Christoph Hellwig <hch@infradead.org> wrote:
> >
> >> Until that happens we should just change the driver ifdefs to default
> >> the hacks to off and only enable them on setups where we 100%
> >> positively know that they actually work. And document that fact
> >> in big fat comments.
> >
> > Well, as I mentioned in my commit log as well, if we default to off
> > unless CONFIG_X86, we may break working setups on MIPS and Power where
> > the device is in fact non-cache coherent, and relies on this
> > 'optimization' to get things working.
>
> FWIW, the amdgpu driver doesn't rely on non-snooped transfers for
> correct basic operation (the scenario Christian brought up is a very
> specialized use-case), so that shouldn't be an issue.
>
The point is that this is only true for x86.
On other architectures, the use of non-cached mappings on the CPU side
means that you /do/ rely on non-snooped transfers, since if those
transfers turn out not to snoop inadvertently, the accesses are
incoherent with the CPU's view of memory.
next prev parent reply other threads:[~2019-01-21 17:59 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-21 10:06 [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86 Ard Biesheuvel
2019-01-21 10:11 ` Koenig, Christian
2019-01-21 15:07 ` Christoph Hellwig
2019-01-21 15:33 ` Ard Biesheuvel
2019-01-21 15:59 ` Christoph Hellwig
2019-01-21 16:14 ` Ard Biesheuvel
2019-01-21 16:22 ` Christoph Hellwig
2019-01-21 16:30 ` Ard Biesheuvel
2019-01-21 16:35 ` Christoph Hellwig
2019-01-21 16:50 ` Ard Biesheuvel
2019-01-21 17:55 ` Michel Dänzer
2019-01-21 17:59 ` Ard Biesheuvel [this message]
2019-01-21 18:04 ` Michel Dänzer
2019-01-21 18:20 ` Ard Biesheuvel
2019-01-21 18:23 ` Michel Dänzer
2019-01-21 18:28 ` Ard Biesheuvel
2019-01-21 19:04 ` Michel Dänzer
2019-01-21 19:18 ` Ard Biesheuvel
2019-01-22 8:38 ` Ard Biesheuvel
2019-01-22 20:56 ` Alex Deucher
2019-01-22 21:07 ` Ard Biesheuvel
2019-01-23 7:15 ` Christoph Hellwig
2019-01-23 9:08 ` Ard Biesheuvel
2019-01-23 16:44 ` Christoph Hellwig
2019-01-23 16:52 ` Ard Biesheuvel
2019-01-24 9:13 ` Christoph Hellwig
2019-01-24 9:25 ` Koenig, Christian
2019-01-24 9:28 ` Ard Biesheuvel
2019-01-24 9:45 ` Koenig, Christian
2019-01-24 9:59 ` Ard Biesheuvel
2019-01-24 11:23 ` Koenig, Christian
2019-01-24 11:26 ` Ard Biesheuvel
2019-01-24 11:37 ` Koenig, Christian
2019-01-24 11:45 ` Ard Biesheuvel
2019-01-24 13:54 ` Alex Deucher
2019-01-24 13:57 ` Ard Biesheuvel
2019-01-24 14:00 ` Alex Deucher
2019-01-24 16:04 ` Michel Dänzer
2019-01-24 9:31 ` Michel Dänzer
2019-01-24 9:37 ` Ard Biesheuvel
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