From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: "Koenig, Christian" <Christian.Koenig@amd.com>
Cc: "Christoph Hellwig" <hch@infradead.org>,
"Alex Deucher" <alexdeucher@gmail.com>,
"Michel Dänzer" <michel@daenzer.net>,
"Maxime Ripard" <maxime.ripard@bootlin.com>,
"Will Deacon" <will.deacon@arm.com>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
"amd-gfx list" <amd-gfx@lists.freedesktop.org>,
"David Airlie" <airlied@linux.ie>,
"Huang, Ray" <Ray.Huang@amd.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
"Michael Ellerman" <mpe@ellerman.id.au>,
"Zhang, Jerry" <Jerry.Zhang@amd.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
"Sean Paul" <sean@poorly.run>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86
Date: Thu, 24 Jan 2019 12:45:25 +0100 [thread overview]
Message-ID: <CAKv+Gu_D4FC05Rz3Oxm_dTWLaGt+a3EDecbsrge1eHY7gFXEYg@mail.gmail.com> (raw)
In-Reply-To: <40ad3ae7-9970-0cb9-d35c-05e128f83820@amd.com>
On Thu, 24 Jan 2019 at 12:37, Koenig, Christian
<Christian.Koenig@amd.com> wrote:
>
> Am 24.01.19 um 12:26 schrieb Ard Biesheuvel:
> > On Thu, 24 Jan 2019 at 12:23, Koenig, Christian
> > <Christian.Koenig@amd.com> wrote:
> >> Am 24.01.19 um 10:59 schrieb Ard Biesheuvel:
> >>> [SNIP]
> >>> This is *exactly* my point the whole time.
> >>>
> >>> The current code has
> >>>
> >>> static inline bool drm_arch_can_wc_memory(void)
> >>> {
> >>> #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
> >>> return false;
> >>>
> >>> which means the optimization is disabled *unless the system is
> >>> non-cache coherent*
> >>>
> >>> So if you have reports that the optimization works on some PowerPC, it
> >>> must be non-cache coherent PowerPC, because that is the only place
> >>> where it is enabled in the first place.
> >>>
> >>>> The only problematic here actually seems to be ARM, so you should
> >>>> probably just add an "#ifdef .._ARM return false;".
> >>>>
> >>> ARM/arm64 does not have a Kconfig symbol like
> >>> CONFIG_NOT_COHERENT_CACHE, so we can only disable it everywhere. If
> >>> there are non-coherent ARM systems that are currently working in the
> >>> same way as those non-coherent PowerPC systems, we will break them by
> >>> doing this.
> >> Summing the things I've read so far for ARM up I actually think it
> >> depends on a runtime configuration and not on compile time one.
> >>
> >> So the whole idea of providing the device to the drm_*_can_wc_memory()
> >> function isn't so far fetched.
> >>
> > Thank you.
> >
> >> But for now I do prefer working and slightly slower system over broken
> >> one, so I think we should just disable this on ARM for now.
> >>
> > Again, this is not about non-cache coherent being slower without the
> > optimization, it is about non-cache coherent likely not working *at
> > all* unless the optimization is enabled.
>
> As Michel tried to explain this CAN'T happen. The optimization is a
> purely optional request from userspace.
>
Right.
So in that case, we can assume that the following test
static inline bool drm_arch_can_wc_memory(void)
{
#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
return false;
is bogus, and it was just unnecessary caution on the part of the
author to disregard non-cache coherent devices.
Unfortunately, those commits have no log messages whatsoever, so it is
difficult to infer the intent retroactively.
> > Otherwise, the driver will vmap() DMA pages with cacheable attributes,
> > while the non-cache coherent device uses uncached attributes, breaking
> > coherency.
>
> Again this is mandated by the userspace APIs anyway. E.g. we can't
> vmap() pages in any other way or our userspace APIs would break.
>
OK,
So let's just disable this for all ARM and arm64 then, given that
non-cache coherent is not supported in any case
next prev parent reply other threads:[~2019-01-24 11:45 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-21 10:06 [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86 Ard Biesheuvel
2019-01-21 10:11 ` Koenig, Christian
2019-01-21 15:07 ` Christoph Hellwig
2019-01-21 15:33 ` Ard Biesheuvel
2019-01-21 15:59 ` Christoph Hellwig
2019-01-21 16:14 ` Ard Biesheuvel
2019-01-21 16:22 ` Christoph Hellwig
2019-01-21 16:30 ` Ard Biesheuvel
2019-01-21 16:35 ` Christoph Hellwig
2019-01-21 16:50 ` Ard Biesheuvel
2019-01-21 17:55 ` Michel Dänzer
2019-01-21 17:59 ` Ard Biesheuvel
2019-01-21 18:04 ` Michel Dänzer
2019-01-21 18:20 ` Ard Biesheuvel
2019-01-21 18:23 ` Michel Dänzer
2019-01-21 18:28 ` Ard Biesheuvel
2019-01-21 19:04 ` Michel Dänzer
2019-01-21 19:18 ` Ard Biesheuvel
2019-01-22 8:38 ` Ard Biesheuvel
2019-01-22 20:56 ` Alex Deucher
2019-01-22 21:07 ` Ard Biesheuvel
2019-01-23 7:15 ` Christoph Hellwig
2019-01-23 9:08 ` Ard Biesheuvel
2019-01-23 16:44 ` Christoph Hellwig
2019-01-23 16:52 ` Ard Biesheuvel
2019-01-24 9:13 ` Christoph Hellwig
2019-01-24 9:25 ` Koenig, Christian
2019-01-24 9:28 ` Ard Biesheuvel
2019-01-24 9:45 ` Koenig, Christian
2019-01-24 9:59 ` Ard Biesheuvel
2019-01-24 11:23 ` Koenig, Christian
2019-01-24 11:26 ` Ard Biesheuvel
2019-01-24 11:37 ` Koenig, Christian
2019-01-24 11:45 ` Ard Biesheuvel [this message]
2019-01-24 13:54 ` Alex Deucher
2019-01-24 13:57 ` Ard Biesheuvel
2019-01-24 14:00 ` Alex Deucher
2019-01-24 16:04 ` Michel Dänzer
2019-01-24 9:31 ` Michel Dänzer
2019-01-24 9:37 ` Ard Biesheuvel
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