* [PATCH 01/13] arm: dts: calxeda: Basic DT file fixes
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:08 ` [PATCH 02/13] arm: dts: calxeda: Provide UART clock Andre Przywara
` (11 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
The .dts files for the Calxeda machines are quite old, so carry some
sloppy mistakes that the DT schema checker will complain about.
Fix those issues, they should not have any effect on functionality.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/boot/dts/ecx-2000.dts | 3 ---
arch/arm/boot/dts/highbank.dts | 7 ++-----
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 5651ae6dc969..81eb382b4c23 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -13,7 +13,6 @@
compatible = "calxeda,ecx-2000";
#address-cells = <2>;
#size-cells = <2>;
- clock-ranges;
cpus {
#address-cells = <1>;
@@ -83,8 +82,6 @@
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
- #size-cells = <0>;
- #address-cells = <1>;
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xfff11000 0x1000>,
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index f4e4dca6f7e7..9e34d1bd7994 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -13,7 +13,6 @@
compatible = "calxeda,highbank";
#address-cells = <1>;
#size-cells = <1>;
- clock-ranges;
cpus {
#address-cells = <1>;
@@ -96,7 +95,7 @@
};
};
- memory {
+ memory@0 {
name = "memory";
device_type = "memory";
reg = <0x00000000 0xff900000>;
@@ -128,14 +127,12 @@
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
- #size-cells = <0>;
- #address-cells = <1>;
interrupt-controller;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xfff12000 0x1000>;
interrupts = <0 70 4>;
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 02/13] arm: dts: calxeda: Provide UART clock
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
2020-02-26 18:08 ` [PATCH 01/13] arm: dts: calxeda: Basic DT file fixes Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:08 ` [PATCH 03/13] arm: dts: calxeda: Fix interrupt grouping Andre Przywara
` (10 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
The PL011 UART binding requires two clocks to be named in a node.
Add the second clock, which is the bus gate, that just gets enabled.
Since this is a fixed clock anyway, it doesn't make any difference.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/boot/dts/ecx-common.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index 66ee1d34f72b..f819e3328a9e 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -114,8 +114,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xfff36000 0x1000>;
interrupts = <0 20 4>;
- clocks = <&pclk>;
- clock-names = "apb_pclk";
+ clocks = <&pclk>, <&pclk>;
+ clock-names = "uartclk", "apb_pclk";
};
smic@fff3a000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 03/13] arm: dts: calxeda: Fix interrupt grouping
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
2020-02-26 18:08 ` [PATCH 01/13] arm: dts: calxeda: Basic DT file fixes Andre Przywara
2020-02-26 18:08 ` [PATCH 02/13] arm: dts: calxeda: Provide UART clock Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:08 ` [PATCH 04/13] arm: dts: calxeda: Group port-phys and sgpio-gpio items Andre Przywara
` (9 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
Currently multiple interrupts for some devices are written as one array
instead of using the DT grouping notation (<0 42 4>, <0 23 4>).
This ends up in the same binary representation in the .dtb, but is
semantically not equivalent. The yaml schema checks will stumble over
this, so lets fix that first.
I refrained from using the symbolic names for GIC_SPI/GIC_PPI and
IRQ_TYPE_LEVEL_HIGH, mostly because it increases the delta between the
original DTS files and the mainline versions, so it's just additional
churn.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/ecx-common.dtsi | 4 ++--
arch/arm/boot/dts/highbank.dts | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 81eb382b4c23..93cdd020637b 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -92,7 +92,7 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
+ interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
};
};
};
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index f819e3328a9e..b7e74a357471 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -202,14 +202,14 @@
ethernet@fff50000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff50000 0x1000>;
- interrupts = <0 77 4 0 78 4 0 79 4>;
+ interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
dma-coherent;
};
ethernet@fff51000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff51000 0x1000>;
- interrupts = <0 80 4 0 81 4 0 82 4>;
+ interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
dma-coherent;
};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 9e34d1bd7994..b6b0225a769e 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -142,14 +142,14 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
+ interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
};
sregs@fff3c200 {
compatible = "calxeda,hb-sregs-l2-ecc";
reg = <0xfff3c200 0x100>;
- interrupts = <0 71 4 0 72 4>;
+ interrupts = <0 71 4>, <0 72 4>;
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 04/13] arm: dts: calxeda: Group port-phys and sgpio-gpio items
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (2 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 03/13] arm: dts: calxeda: Fix interrupt grouping Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:08 ` [PATCH 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema Andre Przywara
` (8 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
For proper bindings checks we need to properly group the port-phys and
sgpio-gpio items, so that they match the expected number of items.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/boot/dts/ecx-common.dtsi | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index b7e74a357471..57a028a69373 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -27,10 +27,11 @@
reg = <0xffe08000 0x10000>;
interrupts = <0 83 4>;
dma-coherent;
- calxeda,port-phys = <&combophy5 0 &combophy0 0
- &combophy0 1 &combophy0 2
- &combophy0 3>;
- calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+ calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
+ <&combophy0 1>, <&combophy0 2>,
+ <&combophy0 3>;
+ calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
+ <&gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (3 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 04/13] arm: dts: calxeda: Group port-phys and sgpio-gpio items Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:24 ` Maxime Ripard
2020-02-26 18:08 ` [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller " Andre Przywara
` (7 subsequent siblings)
12 siblings, 1 reply; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas, Michael Turquette, Stephen Boyd,
linux-clk
Convert the Calxeda clock bindings to DT schema format using json-schema.
This just covers the actual PLL and divider clock nodes. In the actual
DTs they are somewhat unconnected (no ranges or bus compatible) children
of the sregs node, but for the actual clock bindings this is not
relevant.
One oddity is that the addresses are relative to the parent node,
without that being pronounced using a ranges property.
But this is too late to fix now.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
---
.../devicetree/bindings/clock/calxeda.txt | 17 ----
.../devicetree/bindings/clock/calxeda.yaml | 83 +++++++++++++++++++
2 files changed, 83 insertions(+), 17 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/calxeda.txt
create mode 100644 Documentation/devicetree/bindings/clock/calxeda.yaml
diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
deleted file mode 100644
index 0a6ac1bdcda1..000000000000
--- a/Documentation/devicetree/bindings/clock/calxeda.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Device Tree Clock bindings for Calxeda highbank platform
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be one of the following:
- "calxeda,hb-pll-clock" - for a PLL clock
- "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
- A9 clock.
- "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
- "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
-- reg : shall be the control register offset from SYSREGs base for the clock.
-- clocks : shall be the input parent clock phandle for the clock. This is
- either an oscillator or a pll output.
-- #clock-cells : from common clock binding; shall be set to 0.
diff --git a/Documentation/devicetree/bindings/clock/calxeda.yaml b/Documentation/devicetree/bindings/clock/calxeda.yaml
new file mode 100644
index 000000000000..0ad66af0eb0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/calxeda.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/calxeda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Device Tree Clock bindings for Calxeda highbank platform
+
+description: |
+ This binding covers the Calxeda SoC internal peripheral and bus clocks
+ as used by peripherals. The clocks live inside the "system register"
+ region of the SoC, so are typically presented as children of an
+ "hb-sregs" node.
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+ "#clock-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - calxeda,hb-pll-clock
+ - calxeda,hb-a9periph-clock
+ - calxeda,hb-a9bus-clock
+ - calxeda,hb-emmc-clock
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - "#clock-cells"
+ - compatible
+ - clocks
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ sregs@3fffc000 {
+ compatible = "calxeda,hb-sregs";
+ reg = <0x3fffc000 0x1000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333000>;
+ };
+
+ ddrpll: ddrpll {
+ #clock-cells = <0>;
+ compatible = "calxeda,hb-pll-clock";
+ clocks = <&osc>;
+ reg = <0x108>;
+ };
+
+ a9pll: a9pll {
+ #clock-cells = <0>;
+ compatible = "calxeda,hb-pll-clock";
+ clocks = <&osc>;
+ reg = <0x100>;
+ };
+
+ a9periphclk: a9periphclk {
+ #clock-cells = <0>;
+ compatible = "calxeda,hb-a9periph-clock";
+ clocks = <&a9pll>;
+ reg = <0x104>;
+ };
+ };
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema
2020-02-26 18:08 ` [PATCH 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema Andre Przywara
@ 2020-02-26 18:24 ` Maxime Ripard
0 siblings, 0 replies; 22+ messages in thread
From: Maxime Ripard @ 2020-02-26 18:24 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, linux-arm-kernel, linux-kernel, devicetree,
Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas, Michael Turquette, Stephen Boyd,
linux-clk
[-- Attachment #1: Type: text/plain, Size: 3494 bytes --]
On Wed, Feb 26, 2020 at 06:08:53PM +0000, Andre Przywara wrote:
> Convert the Calxeda clock bindings to DT schema format using json-schema.
>
> This just covers the actual PLL and divider clock nodes. In the actual
> DTs they are somewhat unconnected (no ranges or bus compatible) children
> of the sregs node, but for the actual clock bindings this is not
> relevant.
>
> One oddity is that the addresses are relative to the parent node,
> without that being pronounced using a ranges property.
> But this is too late to fix now.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: linux-clk@vger.kernel.org
>
> ---
> .../devicetree/bindings/clock/calxeda.txt | 17 ----
> .../devicetree/bindings/clock/calxeda.yaml | 83 +++++++++++++++++++
> 2 files changed, 83 insertions(+), 17 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/calxeda.txt
> create mode 100644 Documentation/devicetree/bindings/clock/calxeda.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
> deleted file mode 100644
> index 0a6ac1bdcda1..000000000000
> --- a/Documentation/devicetree/bindings/clock/calxeda.txt
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -Device Tree Clock bindings for Calxeda highbank platform
> -
> -This binding uses the common clock binding[1].
> -
> -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> -
> -Required properties:
> -- compatible : shall be one of the following:
> - "calxeda,hb-pll-clock" - for a PLL clock
> - "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
> - A9 clock.
> - "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
> - "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
> -- reg : shall be the control register offset from SYSREGs base for the clock.
> -- clocks : shall be the input parent clock phandle for the clock. This is
> - either an oscillator or a pll output.
> -- #clock-cells : from common clock binding; shall be set to 0.
> diff --git a/Documentation/devicetree/bindings/clock/calxeda.yaml b/Documentation/devicetree/bindings/clock/calxeda.yaml
> new file mode 100644
> index 000000000000..0ad66af0eb0c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/calxeda.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/calxeda.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Device Tree Clock bindings for Calxeda highbank platform
> +
> +description: |
> + This binding covers the Calxeda SoC internal peripheral and bus clocks
> + as used by peripherals. The clocks live inside the "system register"
> + region of the SoC, so are typically presented as children of an
> + "hb-sregs" node.
> +
> +maintainers:
> + - Andre Przywara <andre.przywara@arm.com>
> +
> +properties:
> + "#clock-cells":
> + const: 0
> +
> + compatible:
> + enum:
> + - calxeda,hb-pll-clock
> + - calxeda,hb-a9periph-clock
> + - calxeda,hb-a9bus-clock
> + - calxeda,hb-emmc-clock
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
There's no need to specify the type, it's already checked by a schemas
there:
https://github.com/devicetree-org/dt-schema/blob/master/schemas/clock/clock.yaml
Maxime
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller to json-schema
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (4 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:25 ` Maxime Ripard
2020-02-26 18:08 ` [PATCH 07/13] dt-bindings: net: Convert Calxeda Ethernet binding " Andre Przywara
` (6 subsequent siblings)
12 siblings, 1 reply; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas, Jens Axboe
Convert the Calxeda Highbank SATA controller binding to DT schema format
using json-schema.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Cc: Jens Axboe <axboe@kernel.dk>
---
.../devicetree/bindings/ata/sata_highbank.txt | 44 ---------
.../bindings/ata/sata_highbank.yaml | 96 +++++++++++++++++++
2 files changed, 96 insertions(+), 44 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt
create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.yaml
diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
deleted file mode 100644
index aa83407cb7a4..000000000000
--- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-* Calxeda AHCI SATA Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-The Calxeda SATA controller mostly conforms to the AHCI interface
-with some special extensions to add functionality.
-Each SATA controller should have its own node.
-
-Required properties:
-- compatible : compatible list, contains "calxeda,hb-ahci"
-- interrupts : <interrupt mapping for SATA IRQ>
-- reg : <registers mapping>
-
-Optional properties:
-- dma-coherent : Present if dma operations are coherent
-- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
- SATA port to a combophy and a lane within that
- combophy
-- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
- which indicates that the driver supports SGPIO
- indicator lights using the indicated GPIOs
-- calxeda,led-order : a u32 array that map port numbers to offsets within the
- SGPIO bitstream.
-- calxeda,tx-atten : a u32 array that contains TX attenuation override
- codes, one per port. The upper 3 bytes are always
- 0 and thus ignored.
-- calxeda,pre-clocks : a u32 that indicates the number of additional clock
- cycles to transmit before sending an SGPIO pattern
-- calxeda,post-clocks: a u32 that indicates the number of additional clock
- cycles to transmit after sending an SGPIO pattern
-
-Example:
- sata@ffe08000 {
- compatible = "calxeda,hb-ahci";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
- dma-coherent;
- calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
- &combophy0 2 &combophy0 3>;
- calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
- calxeda,led-order = <4 0 1 2 3>;
- calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
- calxeda,pre-clocks = <10>;
- calxeda,post-clocks = <0>;
- };
diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.yaml b/Documentation/devicetree/bindings/ata/sata_highbank.yaml
new file mode 100644
index 000000000000..392a3efc9833
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda AHCI SATA Controller
+
+description: |
+ The Calxeda SATA controller mostly conforms to the AHCI interface
+ with some special extensions to add functionality, to map GPIOs for
+ activity LEDs and for mapping the ComboPHYs.
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+ compatible:
+ const: calxeda,hb-ahci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dma-coherent: true
+
+ calxeda,pre-clocks:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Indicates the number of additional clock cycles to transmit before
+ sending an SGPIO pattern.
+
+ calxeda,post-clocks:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Indicates the number of additional clock cycles to transmit after
+ sending an SGPIO pattern.
+
+ calxeda,led-order:
+ description: Maps port numbers to offsets within the SGPIO bitstream.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 1
+ maxItems: 8
+
+ calxeda,port-phys:
+ description: |
+ phandle-combophy and lane assignment, which maps each SATA port to a
+ combophy and a lane within that combophy
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle-array
+ - minItems: 1
+ maxItems: 8
+
+ calxeda,tx-atten:
+ description: |
+ Contains TX attenuation override codes, one per port.
+ The upper 24 bits of each entry are always 0 and thus ignored.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 1
+ maxItems: 8
+
+ calxeda,sgpio-gpio:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ phandle-gpio bank, bit offset, and default on or off, which indicates
+ that the driver supports SGPIO indicator lights using the indicated
+ GPIOs.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ sata@ffe08000 {
+ compatible = "calxeda,hb-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;
+ dma-coherent;
+ calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
+ &combophy0 2 &combophy0 3>;
+ calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+ calxeda,led-order = <4 0 1 2 3>;
+ calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
+ calxeda,pre-clocks = <10>;
+ calxeda,post-clocks = <0>;
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller to json-schema
2020-02-26 18:08 ` [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller " Andre Przywara
@ 2020-02-26 18:25 ` Maxime Ripard
0 siblings, 0 replies; 22+ messages in thread
From: Maxime Ripard @ 2020-02-26 18:25 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, linux-arm-kernel, linux-kernel, devicetree,
Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas, Jens Axboe
[-- Attachment #1: Type: text/plain, Size: 5446 bytes --]
On Wed, Feb 26, 2020 at 06:08:54PM +0000, Andre Przywara wrote:
> Convert the Calxeda Highbank SATA controller binding to DT schema format
> using json-schema.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Cc: Jens Axboe <axboe@kernel.dk>
> ---
> .../devicetree/bindings/ata/sata_highbank.txt | 44 ---------
> .../bindings/ata/sata_highbank.yaml | 96 +++++++++++++++++++
> 2 files changed, 96 insertions(+), 44 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt
> create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.yaml
>
> diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> deleted file mode 100644
> index aa83407cb7a4..000000000000
> --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -* Calxeda AHCI SATA Controller
> -
> -SATA nodes are defined to describe on-chip Serial ATA controllers.
> -The Calxeda SATA controller mostly conforms to the AHCI interface
> -with some special extensions to add functionality.
> -Each SATA controller should have its own node.
> -
> -Required properties:
> -- compatible : compatible list, contains "calxeda,hb-ahci"
> -- interrupts : <interrupt mapping for SATA IRQ>
> -- reg : <registers mapping>
> -
> -Optional properties:
> -- dma-coherent : Present if dma operations are coherent
> -- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
> - SATA port to a combophy and a lane within that
> - combophy
> -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
> - which indicates that the driver supports SGPIO
> - indicator lights using the indicated GPIOs
> -- calxeda,led-order : a u32 array that map port numbers to offsets within the
> - SGPIO bitstream.
> -- calxeda,tx-atten : a u32 array that contains TX attenuation override
> - codes, one per port. The upper 3 bytes are always
> - 0 and thus ignored.
> -- calxeda,pre-clocks : a u32 that indicates the number of additional clock
> - cycles to transmit before sending an SGPIO pattern
> -- calxeda,post-clocks: a u32 that indicates the number of additional clock
> - cycles to transmit after sending an SGPIO pattern
> -
> -Example:
> - sata@ffe08000 {
> - compatible = "calxeda,hb-ahci";
> - reg = <0xffe08000 0x1000>;
> - interrupts = <115>;
> - dma-coherent;
> - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
> - &combophy0 2 &combophy0 3>;
> - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
> - calxeda,led-order = <4 0 1 2 3>;
> - calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
> - calxeda,pre-clocks = <10>;
> - calxeda,post-clocks = <0>;
> - };
> diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.yaml b/Documentation/devicetree/bindings/ata/sata_highbank.yaml
> new file mode 100644
> index 000000000000..392a3efc9833
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/sata_highbank.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Calxeda AHCI SATA Controller
> +
> +description: |
> + The Calxeda SATA controller mostly conforms to the AHCI interface
> + with some special extensions to add functionality, to map GPIOs for
> + activity LEDs and for mapping the ComboPHYs.
> +
> +maintainers:
> + - Andre Przywara <andre.przywara@arm.com>
> +
> +properties:
> + compatible:
> + const: calxeda,hb-ahci
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + dma-coherent: true
> +
> + calxeda,pre-clocks:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Indicates the number of additional clock cycles to transmit before
> + sending an SGPIO pattern.
> +
> + calxeda,post-clocks:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Indicates the number of additional clock cycles to transmit after
> + sending an SGPIO pattern.
> +
> + calxeda,led-order:
> + description: Maps port numbers to offsets within the SGPIO bitstream.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32-array
> + - minItems: 1
> + maxItems: 8
> +
> + calxeda,port-phys:
> + description: |
> + phandle-combophy and lane assignment, which maps each SATA port to a
> + combophy and a lane within that combophy
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/phandle-array
> + - minItems: 1
> + maxItems: 8
> +
> + calxeda,tx-atten:
> + description: |
> + Contains TX attenuation override codes, one per port.
> + The upper 24 bits of each entry are always 0 and thus ignored.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32-array
> + - minItems: 1
> + maxItems: 8
> +
> + calxeda,sgpio-gpio:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + phandle-gpio bank, bit offset, and default on or off, which indicates
> + that the driver supports SGPIO indicator lights using the indicated
> + GPIOs.
Ditto, this is being checked already:
https://github.com/devicetree-org/dt-schema/blob/master/schemas/gpio/gpio.yaml#L37
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 07/13] dt-bindings: net: Convert Calxeda Ethernet binding to json-schema
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (5 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 06/13] dt-bindings: sata: Convert Calxeda SATA controller " Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:26 ` Maxime Ripard
2020-02-26 18:08 ` [PATCH 08/13] dt-bindings: phy: Convert Calxeda ComboPHY " Andre Przywara
` (5 subsequent siblings)
12 siblings, 1 reply; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
Convert the Calxeda XGMAC Ethernet device binding to DT schema format
using json-schema.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../devicetree/bindings/net/calxeda-xgmac.txt | 18 -------
.../bindings/net/calxeda-xgmac.yaml | 47 +++++++++++++++++++
2 files changed, 47 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/calxeda-xgmac.txt
create mode 100644 Documentation/devicetree/bindings/net/calxeda-xgmac.yaml
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
deleted file mode 100644
index c8ae996bd8f2..000000000000
--- a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Calxeda Highbank 10Gb XGMAC Ethernet
-
-Required properties:
-- compatible : Should be "calxeda,hb-xgmac"
-- reg : Address and length of the register set for the device
-- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt.
- The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt.
-
-Optional properties:
-- dma-coherent : Present if dma operations are coherent
-
-Example:
-
-ethernet@fff50000 {
- compatible = "calxeda,hb-xgmac";
- reg = <0xfff50000 0x1000>;
- interrupts = <0 77 4 0 78 4 0 79 4>;
-};
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml b/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml
new file mode 100644
index 000000000000..77b8be9ebb20
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/calxeda-xgmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda Highbank 10Gb XGMAC Ethernet controller
+
+description: |
+ The Calxeda XGMAC Ethernet controllers are directly connected to the
+ internal machine "network fabric", which is set up, initialised and
+ managed by the firmware. So there are no PHY properties in this
+ binding. Switches in the fabric take care of routing and mapping the
+ traffic to external network ports.
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+ compatible:
+ const: calxeda,hb-xgmac
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ Can point to at most 3 xgmac interrupts. The 1st one is the main
+ interrupt, the 2nd one is used for power management. The optional
+ 3rd one is the low power state interrupt.
+ minItems: 2
+ maxItems: 3
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ ethernet@fff50000 {
+ compatible = "calxeda,hb-xgmac";
+ reg = <0xfff50000 0x1000>;
+ interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 07/13] dt-bindings: net: Convert Calxeda Ethernet binding to json-schema
2020-02-26 18:08 ` [PATCH 07/13] dt-bindings: net: Convert Calxeda Ethernet binding " Andre Przywara
@ 2020-02-26 18:26 ` Maxime Ripard
0 siblings, 0 replies; 22+ messages in thread
From: Maxime Ripard @ 2020-02-26 18:26 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, linux-arm-kernel, linux-kernel, devicetree,
Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
[-- Attachment #1: Type: text/plain, Size: 2950 bytes --]
On Wed, Feb 26, 2020 at 06:08:55PM +0000, Andre Przywara wrote:
> Convert the Calxeda XGMAC Ethernet device binding to DT schema format
> using json-schema.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../devicetree/bindings/net/calxeda-xgmac.txt | 18 -------
> .../bindings/net/calxeda-xgmac.yaml | 47 +++++++++++++++++++
> 2 files changed, 47 insertions(+), 18 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/net/calxeda-xgmac.txt
> create mode 100644 Documentation/devicetree/bindings/net/calxeda-xgmac.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
> deleted file mode 100644
> index c8ae996bd8f2..000000000000
> --- a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -* Calxeda Highbank 10Gb XGMAC Ethernet
> -
> -Required properties:
> -- compatible : Should be "calxeda,hb-xgmac"
> -- reg : Address and length of the register set for the device
> -- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt.
> - The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt.
> -
> -Optional properties:
> -- dma-coherent : Present if dma operations are coherent
> -
> -Example:
> -
> -ethernet@fff50000 {
> - compatible = "calxeda,hb-xgmac";
> - reg = <0xfff50000 0x1000>;
> - interrupts = <0 77 4 0 78 4 0 79 4>;
> -};
> diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml b/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml
> new file mode 100644
> index 000000000000..77b8be9ebb20
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/calxeda-xgmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Calxeda Highbank 10Gb XGMAC Ethernet controller
> +
> +description: |
> + The Calxeda XGMAC Ethernet controllers are directly connected to the
> + internal machine "network fabric", which is set up, initialised and
> + managed by the firmware. So there are no PHY properties in this
> + binding. Switches in the fabric take care of routing and mapping the
> + traffic to external network ports.
> +
> +maintainers:
> + - Andre Przywara <andre.przywara@arm.com>
> +
> +properties:
> + compatible:
> + const: calxeda,hb-xgmac
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: |
> + Can point to at most 3 xgmac interrupts. The 1st one is the main
> + interrupt, the 2nd one is used for power management. The optional
> + 3rd one is the low power state interrupt.
> + minItems: 2
> + maxItems: 3
> +
> + dma-coherent: true
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
You probably want to add additionalProperties: false here?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 08/13] dt-bindings: phy: Convert Calxeda ComboPHY binding to json-schema
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (6 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 07/13] dt-bindings: net: Convert Calxeda Ethernet binding " Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:26 ` Maxime Ripard
2020-02-26 18:08 ` [PATCH 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller " Andre Przywara
` (4 subsequent siblings)
12 siblings, 1 reply; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
Convert the Calxeda ComboPHY binding to DT schema format using
json-schema.
There is no driver in the Linux kernel matching the compatible
string, but the nodes are parsed by the SATA driver, which links to them
using its port-phys property.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../bindings/phy/calxeda-combophy.txt | 17 -------
.../bindings/phy/calxeda-combophy.yaml | 47 +++++++++++++++++++
2 files changed, 47 insertions(+), 17 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.txt
create mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt b/Documentation/devicetree/bindings/phy/calxeda-combophy.txt
deleted file mode 100644
index 6622bdb2e8bc..000000000000
--- a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Calxeda Highbank Combination Phys for SATA
-
-Properties:
-- compatible : Should be "calxeda,hb-combophy"
-- #phy-cells: Should be 1.
-- reg : Address and size for Combination Phy registers.
-- phydev: device ID for programming the combophy.
-
-Example:
-
- combophy5: combo-phy@fff5d000 {
- compatible = "calxeda,hb-combophy";
- #phy-cells = <1>;
- reg = <0xfff5d000 0x1000>;
- phydev = <31>;
- };
-
diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
new file mode 100644
index 000000000000..2ef68b95fae1
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda Highbank Combination PHYs binding for SATA
+
+description: |
+ The Calxeda Combination PHYs connect the SoC to the internal fabric
+ and to SATA connectors. The PHYs support multiple protocols (SATA,
+ SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
+ controller).
+ Programming the PHYs is typically handled by those device drivers,
+ not by a dedicated PHY driver.
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+ compatible:
+ const: calxeda,hb-combophy
+
+ '#phy-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ phydev:
+ description: device ID for programming the combophy.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - phydev
+ - '#phy-cells'
+
+examples:
+ - |
+ combophy5: combo-phy@fff5d000 {
+ compatible = "calxeda,hb-combophy";
+ #phy-cells = <1>;
+ reg = <0xfff5d000 0x1000>;
+ phydev = <31>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 08/13] dt-bindings: phy: Convert Calxeda ComboPHY binding to json-schema
2020-02-26 18:08 ` [PATCH 08/13] dt-bindings: phy: Convert Calxeda ComboPHY " Andre Przywara
@ 2020-02-26 18:26 ` Maxime Ripard
0 siblings, 0 replies; 22+ messages in thread
From: Maxime Ripard @ 2020-02-26 18:26 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, linux-arm-kernel, linux-kernel, devicetree,
Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
[-- Attachment #1: Type: text/plain, Size: 2810 bytes --]
On Wed, Feb 26, 2020 at 06:08:56PM +0000, Andre Przywara wrote:
> Convert the Calxeda ComboPHY binding to DT schema format using
> json-schema.
> There is no driver in the Linux kernel matching the compatible
> string, but the nodes are parsed by the SATA driver, which links to them
> using its port-phys property.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../bindings/phy/calxeda-combophy.txt | 17 -------
> .../bindings/phy/calxeda-combophy.yaml | 47 +++++++++++++++++++
> 2 files changed, 47 insertions(+), 17 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.txt
> create mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt b/Documentation/devicetree/bindings/phy/calxeda-combophy.txt
> deleted file mode 100644
> index 6622bdb2e8bc..000000000000
> --- a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -Calxeda Highbank Combination Phys for SATA
> -
> -Properties:
> -- compatible : Should be "calxeda,hb-combophy"
> -- #phy-cells: Should be 1.
> -- reg : Address and size for Combination Phy registers.
> -- phydev: device ID for programming the combophy.
> -
> -Example:
> -
> - combophy5: combo-phy@fff5d000 {
> - compatible = "calxeda,hb-combophy";
> - #phy-cells = <1>;
> - reg = <0xfff5d000 0x1000>;
> - phydev = <31>;
> - };
> -
> diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
> new file mode 100644
> index 000000000000..2ef68b95fae1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Calxeda Highbank Combination PHYs binding for SATA
> +
> +description: |
> + The Calxeda Combination PHYs connect the SoC to the internal fabric
> + and to SATA connectors. The PHYs support multiple protocols (SATA,
> + SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
> + controller).
> + Programming the PHYs is typically handled by those device drivers,
> + not by a dedicated PHY driver.
> +
> +maintainers:
> + - Andre Przywara <andre.przywara@arm.com>
> +
> +properties:
> + compatible:
> + const: calxeda,hb-combophy
> +
> + '#phy-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + phydev:
> + description: device ID for programming the combophy.
> + $ref: /schemas/types.yaml#/definitions/uint32
I guess you can limit the range here, or does it cover the whole u32
range?
Maxime
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (7 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 08/13] dt-bindings: phy: Convert Calxeda ComboPHY " Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:08 ` [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR " Andre Przywara
` (3 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
Convert the L2-ECC controller binding to DT schema format using
json-schema.
This is indented to be just used for error reporting.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 --------
.../bindings/arm/calxeda/l2ecc.yaml | 36 +++++++++++++++++++
2 files changed, 36 insertions(+), 15 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
create mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
deleted file mode 100644
index 94e642a33db0..000000000000
--- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Calxeda Highbank L2 cache ECC
-
-Properties:
-- compatible : Should be "calxeda,hb-sregs-l2-ecc"
-- reg : Address and size for ECC error interrupt clear registers.
-- interrupts : Should be single bit error interrupt, then double bit error
- interrupt.
-
-Example:
-
- sregs@fff3c200 {
- compatible = "calxeda,hb-sregs-l2-ecc";
- reg = <0xfff3c200 0x100>;
- interrupts = <0 71 4 0 72 4>;
- };
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
new file mode 100644
index 000000000000..25c022766f0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda Highbank L2 cache ECC
+
+description: |
+ Binding for the Calxeda Highbank L2 cache controller ECC device.
+ This does not cover the actual L2 cache controller control registers,
+ but just the error reporting functionality.
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+ compatible:
+ const: "calxeda,hb-sregs-l2-ecc"
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ Should be single bit error interrupt, then double bit error interrupt.
+ minItems: 2
+ maxItems: 2
+
+examples:
+ - |
+ sregs@fff3c200 {
+ compatible = "calxeda,hb-sregs-l2-ecc";
+ reg = <0xfff3c200 0x100>;
+ interrupts = <0 71 4>, <0 72 4>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR to json-schema
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (8 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller " Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:27 ` Maxime Ripard
2020-02-26 18:08 ` [PATCH 11/13] dt-bindings: ipmi: Convert IPMI-SMIC bindings " Andre Przywara
` (2 subsequent siblings)
12 siblings, 1 reply; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
Convert the Calxeda DDR memory controller binding to DT schema format
using json-schema.
Although this technically covers the whole DRAM controller, the
intention to use it only for error reporting and mapping fault addresses
to DRAM chips.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../memory-controllers/calxeda-ddr-ctrlr.txt | 16 --------
.../memory-controllers/calxeda-ddr-ctrlr.yaml | 41 +++++++++++++++++++
2 files changed, 41 insertions(+), 16 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt
deleted file mode 100644
index 049675944b78..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Calxeda DDR memory controller
-
-Properties:
-- compatible : Should be:
- - "calxeda,hb-ddr-ctrl" for ECX-1000
- - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
-- reg : Address and size for DDR controller registers.
-- interrupts : Interrupt for DDR controller.
-
-Example:
-
- memory-controller@fff00000 {
- compatible = "calxeda,hb-ddr-ctrl";
- reg = <0xfff00000 0x1000>;
- interrupts = <0 91 4>;
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml
new file mode 100644
index 000000000000..c5153127e722
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda DDR memory controller binding
+
+description: |
+ The Calxeda DDR memory controller is initialised and programmed by the
+ firmware, but an OS might want to read its registers for error reporting
+ purposes and to learn about the DRAM topology.
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - calxeda,hb-ddr-ctrl
+ - calxeda,ecx-2000-ddr-ctrl
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ memory-controller@fff00000 {
+ compatible = "calxeda,hb-ddr-ctrl";
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 91 4>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR to json-schema
2020-02-26 18:08 ` [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR " Andre Przywara
@ 2020-02-26 18:27 ` Maxime Ripard
0 siblings, 0 replies; 22+ messages in thread
From: Maxime Ripard @ 2020-02-26 18:27 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, linux-arm-kernel, linux-kernel, devicetree,
Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
[-- Attachment #1: Type: text/plain, Size: 2906 bytes --]
On Wed, Feb 26, 2020 at 06:08:58PM +0000, Andre Przywara wrote:
> Convert the Calxeda DDR memory controller binding to DT schema format
> using json-schema.
> Although this technically covers the whole DRAM controller, the
> intention to use it only for error reporting and mapping fault addresses
> to DRAM chips.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../memory-controllers/calxeda-ddr-ctrlr.txt | 16 --------
> .../memory-controllers/calxeda-ddr-ctrlr.yaml | 41 +++++++++++++++++++
> 2 files changed, 41 insertions(+), 16 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt
> deleted file mode 100644
> index 049675944b78..000000000000
> --- a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -Calxeda DDR memory controller
> -
> -Properties:
> -- compatible : Should be:
> - - "calxeda,hb-ddr-ctrl" for ECX-1000
> - - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
> -- reg : Address and size for DDR controller registers.
> -- interrupts : Interrupt for DDR controller.
> -
> -Example:
> -
> - memory-controller@fff00000 {
> - compatible = "calxeda,hb-ddr-ctrl";
> - reg = <0xfff00000 0x1000>;
> - interrupts = <0 91 4>;
> - };
> diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml
> new file mode 100644
> index 000000000000..c5153127e722
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Calxeda DDR memory controller binding
> +
> +description: |
> + The Calxeda DDR memory controller is initialised and programmed by the
> + firmware, but an OS might want to read its registers for error reporting
> + purposes and to learn about the DRAM topology.
> +
> +maintainers:
> + - Andre Przywara <andre.przywara@arm.com>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - calxeda,hb-ddr-ctrl
> + - calxeda,ecx-2000-ddr-ctrl
You don't need the items here, you can just have the enum directly
(like you did in your other schemas).
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
And you're probably missing additionalProperties too (and in other
schemas).
Maxime
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 11/13] dt-bindings: ipmi: Convert IPMI-SMIC bindings to json-schema
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (9 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 10/13] dt-bindings: memory-controllers: convert Calxeda DDR " Andre Przywara
@ 2020-02-26 18:08 ` Andre Przywara
2020-02-26 18:09 ` [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding Andre Przywara
2020-02-26 18:09 ` [PATCH 13/13] MAINTAINERS: Update Calxeda Highbank maintainership Andre Przywara
12 siblings, 0 replies; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:08 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas, Corey Minyard, openipmi-developer
Convert the generic IPMI controller bindings to DT schema format
using json-schema.
I removed the formerly mandatory device-type property, since this
is deprecated in the DT spec, except for the legacy CPU and memory
nodes.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Cc: Corey Minyard <minyard@acm.org>
Cc: openipmi-developer@lists.sourceforge.net
---
.../devicetree/bindings/ipmi/ipmi-smic.txt | 25 ---------
.../devicetree/bindings/ipmi/ipmi-smic.yaml | 56 +++++++++++++++++++
2 files changed, 56 insertions(+), 25 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ipmi/ipmi-smic.txt
create mode 100644 Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml
diff --git a/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt b/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt
deleted file mode 100644
index d5f1a877ed3e..000000000000
--- a/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-IPMI device
-
-Required properties:
-- compatible: should be one of ipmi-kcs, ipmi-smic, or ipmi-bt
-- device_type: should be ipmi
-- reg: Address and length of the register set for the device
-
-Optional properties:
-- interrupts: The interrupt for the device. Without this the interface
- is polled.
-- reg-size - The size of the register. Defaults to 1
-- reg-spacing - The number of bytes between register starts. Defaults to 1
-- reg-shift - The amount to shift the registers to the right to get the data
- into bit zero.
-
-Example:
-
-smic@fff3a000 {
- compatible = "ipmi-smic";
- device_type = "ipmi";
- reg = <0xfff3a000 0x1000>;
- interrupts = <0 24 4>;
- reg-size = <4>;
- reg-spacing = <4>;
-};
diff --git a/Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml b/Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml
new file mode 100644
index 000000000000..c859e0e959b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ipmi/ipmi-smic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IPMI device bindings
+
+description: IPMI device bindings
+
+maintainers:
+ - Corey Minyard <cminyard@mvista.com>
+
+properties:
+ compatible:
+ enum:
+ - ipmi-kcs
+ - ipmi-smic
+ - ipmi-bt
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Interface is polled if this property is omitted.
+ maxItems: 1
+
+ reg-size:
+ description: The access width of the register in bytes. Defaults to 1.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 4, 8]
+
+ reg-spacing:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The number of bytes between register starts. Defaults to 1.
+
+ reg-shift:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The amount of bits to shift the register content to the right to get
+ the data into bit zero.
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ smic@fff3a000 {
+ compatible = "ipmi-smic";
+ reg = <0xfff3a000 0x1000>;
+ interrupts = <0 24 4>;
+ reg-size = <4>;
+ reg-spacing = <4>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (10 preceding siblings ...)
2020-02-26 18:08 ` [PATCH 11/13] dt-bindings: ipmi: Convert IPMI-SMIC bindings " Andre Przywara
@ 2020-02-26 18:09 ` Andre Przywara
2020-02-26 21:57 ` Rob Herring
2020-02-26 18:09 ` [PATCH 13/13] MAINTAINERS: Update Calxeda Highbank maintainership Andre Przywara
12 siblings, 1 reply; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:09 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
The Calxeda system registers are a collection of MMIO register
controlling several more general aspects of the SoC.
Beside for some power management tasks this node is also somewhat
abused as the container for the clock nodes.
Add a binding in DT schema format using json-schema.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../bindings/arm/calxeda/hb-sregs.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
diff --git a/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml b/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
new file mode 100644
index 000000000000..541c47955a3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Calxeda Highbank system registers
+
+description: |
+ The Calxeda Highbank system has a block of MMIO registers controlling
+ several generic system aspects. Those can be used to control some power
+ management, they also contain some gate and PLL clocks.
+
+maintainers:
+ - Andre Przywara <andre.przywara@arm.com>
+
+properties:
+ compatible:
+ const: calxeda,hb-sregs
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ type: object
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ sregs@fff3c000 {
+ compatible = "calxeda,hb-sregs";
+ reg = <0xfff3c000 0x1000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333000>;
+ };
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding
2020-02-26 18:09 ` [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding Andre Przywara
@ 2020-02-26 21:57 ` Rob Herring
2020-02-27 0:12 ` André Przywara
0 siblings, 1 reply; 22+ messages in thread
From: Rob Herring @ 2020-02-26 21:57 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-arm-kernel, linux-kernel, devicetree, Robert Richter, soc,
Jon Loeliger, Mark Langsdorf, Eric Auger, Will Deacon,
Catalin Marinas
On Wed, 26 Feb 2020 18:09:00 +0000, Andre Przywara wrote:
> The Calxeda system registers are a collection of MMIO register
> controlling several more general aspects of the SoC.
> Beside for some power management tasks this node is also somewhat
> abused as the container for the clock nodes.
>
> Add a binding in DT schema format using json-schema.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../bindings/arm/calxeda/hb-sregs.yaml | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
warning: no schema found in file: Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: ignoring, error in schema: properties: clocks
Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: properties:clocks: {'type': 'object'} is not valid under any of the given schemas (Possible causes of the failure):
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: properties:clocks: 'maxItems' is a required property
Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/arm/calxeda/hb-sregs.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/arm/calxeda/hb-sregs.example.dts] Error 1
Makefile:1263: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1245261
Please check and re-submit.
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding
2020-02-26 21:57 ` Rob Herring
@ 2020-02-27 0:12 ` André Przywara
2020-02-27 14:44 ` Rob Herring
0 siblings, 1 reply; 22+ messages in thread
From: André Przywara @ 2020-02-27 0:12 UTC (permalink / raw)
To: Rob Herring
Cc: linux-arm-kernel, linux-kernel, devicetree, Robert Richter, soc,
Jon Loeliger, Mark Langsdorf, Eric Auger, Will Deacon,
Catalin Marinas
On 26/02/2020 21:57, Rob Herring wrote:
Hi Rob,
thanks for giving it a try!
> On Wed, 26 Feb 2020 18:09:00 +0000, Andre Przywara wrote:
>> The Calxeda system registers are a collection of MMIO register
>> controlling several more general aspects of the SoC.
>> Beside for some power management tasks this node is also somewhat
>> abused as the container for the clock nodes.
>>
>> Add a binding in DT schema format using json-schema.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> .../bindings/arm/calxeda/hb-sregs.yaml | 47 +++++++++++++++++++
>> 1 file changed, 47 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
>>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> warning: no schema found in file: Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: ignoring, error in schema: properties: clocks
> Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: properties:clocks: {'type': 'object'} is not valid under any of the given schemas (Possible causes of the failure):
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: properties:clocks: 'maxItems' is a required property
>
> Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/arm/calxeda/hb-sregs.example.dts' failed
> make[1]: *** [Documentation/devicetree/bindings/arm/calxeda/hb-sregs.example.dts] Error 1
> Makefile:1263: recipe for target 'dt_binding_check' failed
> make: *** [dt_binding_check] Error 2
>
> See https://patchwork.ozlabs.org/patch/1245261
> Please check and re-submit.
Ah, right, I forgot that I actually fixed dt-schema:
It seems like we can cope with "clocks" being just a node name in
schema/clock/clock.yaml [1], but not in meta-schemas/clocks.yaml [2].
I added a similar anyOf ... to the meta-schemas entry, which seems to
fix it for me.
Can you confirm that this is a bug in dt-schema and this is the proper
fix or am I doing something wrong (I have only a smattering in
dt-schema/json)?
Cheers,
Andre
[1]
https://github.com/robherring/dt-schema/blob/master/schemas/clock/clock.yaml#L63-L67
[2]
https://github.com/robherring/dt-schema/blob/master/meta-schemas/clocks.yaml#L10-L11
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding
2020-02-27 0:12 ` André Przywara
@ 2020-02-27 14:44 ` Rob Herring
0 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2020-02-27 14:44 UTC (permalink / raw)
To: André Przywara
Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel, devicetree, Robert Richter, soc, Jon Loeliger,
Mark Langsdorf, Eric Auger, Will Deacon, Catalin Marinas
On Wed, Feb 26, 2020 at 6:12 PM André Przywara <andre.przywara@arm.com> wrote:
>
> On 26/02/2020 21:57, Rob Herring wrote:
>
> Hi Rob,
>
> thanks for giving it a try!
>
> > On Wed, 26 Feb 2020 18:09:00 +0000, Andre Przywara wrote:
> >> The Calxeda system registers are a collection of MMIO register
> >> controlling several more general aspects of the SoC.
> >> Beside for some power management tasks this node is also somewhat
> >> abused as the container for the clock nodes.
> >>
> >> Add a binding in DT schema format using json-schema.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >> ---
> >> .../bindings/arm/calxeda/hb-sregs.yaml | 47 +++++++++++++++++++
> >> 1 file changed, 47 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
> >>
> >
> > My bot found errors running 'make dt_binding_check' on your patch:
> >
> > warning: no schema found in file: Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml
> > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: ignoring, error in schema: properties: clocks
> > Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
> > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: properties:clocks: {'type': 'object'} is not valid under any of the given schemas (Possible causes of the failure):
> > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml: properties:clocks: 'maxItems' is a required property
> >
> > Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/arm/calxeda/hb-sregs.example.dts' failed
> > make[1]: *** [Documentation/devicetree/bindings/arm/calxeda/hb-sregs.example.dts] Error 1
> > Makefile:1263: recipe for target 'dt_binding_check' failed
> > make: *** [dt_binding_check] Error 2
> >
> > See https://patchwork.ozlabs.org/patch/1245261
> > Please check and re-submit.
>
> Ah, right, I forgot that I actually fixed dt-schema:
>
> It seems like we can cope with "clocks" being just a node name in
> schema/clock/clock.yaml [1], but not in meta-schemas/clocks.yaml [2].
>
> I added a similar anyOf ... to the meta-schemas entry, which seems to
> fix it for me.
>
> Can you confirm that this is a bug in dt-schema and this is the proper
> fix or am I doing something wrong (I have only a smattering in
> dt-schema/json)?
Yeah, that's right. Though ideally we'd avoid names that are used as
both properties and nodes, but this one is kind of widely used.
Can you submit a GH pull req with the fix (use the devicetree-org one,
not my tree).
Rob
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 13/13] MAINTAINERS: Update Calxeda Highbank maintainership
2020-02-26 18:08 [PATCH 00/13] arm: calxeda: update DTS, bindings and MAINTAINERS Andre Przywara
` (11 preceding siblings ...)
2020-02-26 18:09 ` [PATCH 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding Andre Przywara
@ 2020-02-26 18:09 ` Andre Przywara
12 siblings, 0 replies; 22+ messages in thread
From: Andre Przywara @ 2020-02-26 18:09 UTC (permalink / raw)
To: Rob Herring, linux-arm-kernel, linux-kernel, devicetree
Cc: Robert Richter, soc, Jon Loeliger, Mark Langsdorf, Eric Auger,
Will Deacon, Catalin Marinas
Rob sees little point in maintaining the Calxeda architecture (early ARM
32-bit server) anymore.
Since I have a machine sitting under my desk, change the maintainership
to not lose support for that platform.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index fcd79fc38928..5354ba7460b8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1605,7 +1605,7 @@ F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
ARM/CALXEDA HIGHBANK ARCHITECTURE
-M: Rob Herring <robh@kernel.org>
+M: Andre Przywara <andre.przywara@arm.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-highbank/
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread